2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
25 #include <asm/mach-ar71xx/ar71xx.h>
30 #define AR71XX_SYS_TYPE_LEN 64
33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq
);
36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq
);
39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq
);
42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq
);
44 enum ar71xx_soc_type ar71xx_soc
;
45 EXPORT_SYMBOL_GPL(ar71xx_soc
);
48 EXPORT_SYMBOL_GPL(ar71xx_soc_rev
);
50 static char ar71xx_sys_type
[AR71XX_SYS_TYPE_LEN
];
52 static void ar71xx_restart(char *command
)
54 ar71xx_device_stop(RESET_MODULE_FULL_CHIP
);
60 static void ar71xx_halt(void)
66 static void __init
ar71xx_detect_mem_size(void)
70 for (size
= AR71XX_MEM_SIZE_MIN
; size
< AR71XX_MEM_SIZE_MAX
;
72 if (!memcmp(ar71xx_detect_mem_size
,
73 ar71xx_detect_mem_size
+ size
, 1024))
77 add_memory_region(0, size
, BOOT_MEM_RAM
);
80 static void __init
ar71xx_detect_sys_type(void)
88 id
= ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID
);
89 major
= id
& REV_ID_MAJOR_MASK
;
92 case REV_ID_MAJOR_AR71XX
:
93 minor
= id
& AR71XX_REV_ID_MINOR_MASK
;
94 rev
= id
>> AR71XX_REV_ID_REVISION_SHIFT
;
95 rev
&= AR71XX_REV_ID_REVISION_MASK
;
97 case AR71XX_REV_ID_MINOR_AR7130
:
98 ar71xx_soc
= AR71XX_SOC_AR7130
;
102 case AR71XX_REV_ID_MINOR_AR7141
:
103 ar71xx_soc
= AR71XX_SOC_AR7141
;
107 case AR71XX_REV_ID_MINOR_AR7161
:
108 ar71xx_soc
= AR71XX_SOC_AR7161
;
114 case REV_ID_MAJOR_AR7240
:
115 ar71xx_soc
= AR71XX_SOC_AR7240
;
117 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
120 case REV_ID_MAJOR_AR7241
:
121 ar71xx_soc
= AR71XX_SOC_AR7241
;
123 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
126 case REV_ID_MAJOR_AR7242
:
127 ar71xx_soc
= AR71XX_SOC_AR7242
;
129 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
132 case REV_ID_MAJOR_AR913X
:
133 minor
= id
& AR91XX_REV_ID_MINOR_MASK
;
134 rev
= id
>> AR91XX_REV_ID_REVISION_SHIFT
;
135 rev
&= AR91XX_REV_ID_REVISION_MASK
;
137 case AR91XX_REV_ID_MINOR_AR9130
:
138 ar71xx_soc
= AR71XX_SOC_AR9130
;
142 case AR91XX_REV_ID_MINOR_AR9132
:
143 ar71xx_soc
= AR71XX_SOC_AR9132
;
149 case REV_ID_MAJOR_AR9330
:
150 ar71xx_soc
= AR71XX_SOC_AR9330
;
152 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
155 case REV_ID_MAJOR_AR9331
:
156 ar71xx_soc
= AR71XX_SOC_AR9331
;
158 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
161 case REV_ID_MAJOR_AR9342
:
162 ar71xx_soc
= AR71XX_SOC_AR9342
;
164 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
167 case REV_ID_MAJOR_AR9344
:
168 ar71xx_soc
= AR71XX_SOC_AR9344
;
170 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
174 panic("ar71xx: unknown chip id:0x%08x\n", id
);
177 ar71xx_soc_rev
= rev
;
179 sprintf(ar71xx_sys_type
, "Atheros AR%s rev %u", chip
, rev
);
180 pr_info("SoC: %s\n", ar71xx_sys_type
);
183 static void __init
ar934x_detect_sys_frequency(void)
185 u32 pll
, out_div
, ref_div
, nint
, frac
, clk_ctrl
, postdiv
;
187 if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP
) & AR934X_REF_CLK_40
)
188 ar71xx_ref_freq
= 40 * 1000 * 1000;
190 ar71xx_ref_freq
= 25 * 1000 * 1000;
192 clk_ctrl
= ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK
);
194 pll
= ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG
);
195 out_div
= AR934X_CPU_PLL_CFG_OUTDIV_GET(pll
);
196 ref_div
= AR934X_CPU_PLL_CFG_REFDIV_GET(pll
);
197 nint
= AR934X_CPU_PLL_CFG_NINT_GET(pll
);
198 frac
= AR934X_CPU_PLL_CFG_NFRAC_GET(pll
);
199 postdiv
= AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl
);
200 ar71xx_cpu_freq
= ((nint
* ar71xx_ref_freq
/ ref_div
) >> out_div
) /
203 out_div
= AR934X_DDR_PLL_CFG_OUTDIV_GET(pll
);
204 ref_div
= AR934X_DDR_PLL_CFG_REFDIV_GET(pll
);
205 nint
= AR934X_DDR_PLL_CFG_NINT_GET(pll
);
206 frac
= AR934X_DDR_PLL_CFG_NFRAC_GET(pll
);
207 postdiv
= AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl
);
208 ar71xx_ddr_freq
= ((nint
* ar71xx_ref_freq
/ ref_div
) >> out_div
) /
211 postdiv
= AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl
);
213 if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl
)) {
214 ar71xx_ahb_freq
= ar71xx_ddr_freq
/ (postdiv
+ 1);
216 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ (postdiv
+ 1);
221 static void __init
ar91xx_detect_sys_frequency(void)
227 ar71xx_ref_freq
= 5 * 1000 * 1000;
229 pll
= ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG
);
231 div
= ((pll
>> AR91XX_PLL_DIV_SHIFT
) & AR91XX_PLL_DIV_MASK
);
232 freq
= div
* ar71xx_ref_freq
;
234 ar71xx_cpu_freq
= freq
;
236 div
= ((pll
>> AR91XX_DDR_DIV_SHIFT
) & AR91XX_DDR_DIV_MASK
) + 1;
237 ar71xx_ddr_freq
= freq
/ div
;
239 div
= (((pll
>> AR91XX_AHB_DIV_SHIFT
) & AR91XX_AHB_DIV_MASK
) + 1) * 2;
240 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
243 static void __init
ar71xx_detect_sys_frequency(void)
249 ar71xx_ref_freq
= 40 * 1000 * 1000;
251 pll
= ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG
);
253 div
= ((pll
>> AR71XX_PLL_DIV_SHIFT
) & AR71XX_PLL_DIV_MASK
) + 1;
254 freq
= div
* ar71xx_ref_freq
;
256 div
= ((pll
>> AR71XX_CPU_DIV_SHIFT
) & AR71XX_CPU_DIV_MASK
) + 1;
257 ar71xx_cpu_freq
= freq
/ div
;
259 div
= ((pll
>> AR71XX_DDR_DIV_SHIFT
) & AR71XX_DDR_DIV_MASK
) + 1;
260 ar71xx_ddr_freq
= freq
/ div
;
262 div
= (((pll
>> AR71XX_AHB_DIV_SHIFT
) & AR71XX_AHB_DIV_MASK
) + 1) * 2;
263 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
266 static void __init
ar724x_detect_sys_frequency(void)
272 ar71xx_ref_freq
= 5 * 1000 * 1000;
274 pll
= ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG
);
276 div
= ((pll
>> AR724X_PLL_DIV_SHIFT
) & AR724X_PLL_DIV_MASK
);
277 freq
= div
* ar71xx_ref_freq
;
279 div
= ((pll
>> AR724X_PLL_REF_DIV_SHIFT
) & AR724X_PLL_REF_DIV_MASK
);
282 ar71xx_cpu_freq
= freq
;
284 div
= ((pll
>> AR724X_DDR_DIV_SHIFT
) & AR724X_DDR_DIV_MASK
) + 1;
285 ar71xx_ddr_freq
= freq
/ div
;
287 div
= (((pll
>> AR724X_AHB_DIV_SHIFT
) & AR724X_AHB_DIV_MASK
) + 1) * 2;
288 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
291 static void __init
ar933x_detect_sys_frequency(void)
298 t
= ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP
);
299 if (t
& AR933X_BOOTSTRAP_REF_CLK_40
)
300 ar71xx_ref_freq
= (40 * 1000 * 1000);
302 ar71xx_ref_freq
= (25 * 1000 * 1000);
304 clock_ctrl
= ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG
);
305 if (clock_ctrl
& AR933X_PLL_CLOCK_CTRL_BYPASS
) {
306 ar71xx_cpu_freq
= ar71xx_ref_freq
;
307 ar71xx_ahb_freq
= ar71xx_ref_freq
;
308 ar71xx_ddr_freq
= ar71xx_ref_freq
;
310 cpu_config
= ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG
);
312 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT
) &
313 AR933X_PLL_CPU_CONFIG_REFDIV_MASK
;
314 freq
= ar71xx_ref_freq
/ t
;
316 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_NINT_SHIFT
) &
317 AR933X_PLL_CPU_CONFIG_NINT_MASK
;
320 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT
) &
321 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK
;
327 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT
) &
328 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK
) + 1;
329 ar71xx_cpu_freq
= freq
/ t
;
331 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT
) &
332 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK
) + 1;
333 ar71xx_ddr_freq
= freq
/ t
;
335 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT
) &
336 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK
) + 1;
337 ar71xx_ahb_freq
= freq
/ t
;
341 static void __init
detect_sys_frequency(void)
343 switch (ar71xx_soc
) {
344 case AR71XX_SOC_AR7130
:
345 case AR71XX_SOC_AR7141
:
346 case AR71XX_SOC_AR7161
:
347 ar71xx_detect_sys_frequency();
350 case AR71XX_SOC_AR7240
:
351 case AR71XX_SOC_AR7241
:
352 case AR71XX_SOC_AR7242
:
353 ar724x_detect_sys_frequency();
356 case AR71XX_SOC_AR9130
:
357 case AR71XX_SOC_AR9132
:
358 ar91xx_detect_sys_frequency();
361 case AR71XX_SOC_AR9330
:
362 case AR71XX_SOC_AR9331
:
363 ar933x_detect_sys_frequency();
366 case AR71XX_SOC_AR9341
:
367 case AR71XX_SOC_AR9342
:
368 case AR71XX_SOC_AR9344
:
369 ar934x_detect_sys_frequency();
376 const char *get_system_type(void)
378 return ar71xx_sys_type
;
381 unsigned int __cpuinit
get_c0_compare_irq(void)
383 return CP0_LEGACY_COMPARE_IRQ
;
386 void __init
plat_mem_setup(void)
388 set_io_port_base(KSEG1
);
390 ar71xx_ddr_base
= ioremap_nocache(AR71XX_DDR_CTRL_BASE
,
391 AR71XX_DDR_CTRL_SIZE
);
393 ar71xx_pll_base
= ioremap_nocache(AR71XX_PLL_BASE
,
396 ar71xx_reset_base
= ioremap_nocache(AR71XX_RESET_BASE
,
399 ar71xx_gpio_base
= ioremap_nocache(AR71XX_GPIO_BASE
, AR71XX_GPIO_SIZE
);
401 ar71xx_usb_ctrl_base
= ioremap_nocache(AR71XX_USB_CTRL_BASE
,
402 AR71XX_USB_CTRL_SIZE
);
404 ar71xx_detect_mem_size();
405 ar71xx_detect_sys_type();
406 detect_sys_frequency();
408 pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
410 ar71xx_cpu_freq
/ 1000000, (ar71xx_cpu_freq
/ 1000) % 1000,
411 ar71xx_ddr_freq
/ 1000000, (ar71xx_ddr_freq
/ 1000) % 1000,
412 ar71xx_ahb_freq
/ 1000000, (ar71xx_ahb_freq
/ 1000) % 1000,
413 ar71xx_ref_freq
/ 1000000, (ar71xx_ref_freq
/ 1000) % 1000);
415 _machine_restart
= ar71xx_restart
;
416 _machine_halt
= ar71xx_halt
;
417 pm_power_off
= ar71xx_halt
;
420 void __init
plat_time_init(void)
422 mips_hpt_frequency
= ar71xx_cpu_freq
/ 2;
425 __setup("board=", mips_machtype_setup
);
427 static int __init
ar71xx_machine_setup(void)
431 ar71xx_add_device_uart();
432 ar71xx_add_device_wdt();
434 mips_machine_setup();
438 arch_initcall(ar71xx_machine_setup
);
440 static void __init
ar71xx_generic_init(void)
445 MIPS_MACHINE(AR71XX_MACH_GENERIC
, "Generic", "Generic AR71xx board",
446 ar71xx_generic_init
);