2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/serial_8250.h>
20 #include <linux/bootmem.h>
22 #include <asm/bootinfo.h>
23 #include <asm/traps.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
25 #include <asm/reboot.h> /* for _machine_{restart,halt} */
26 #include <asm/mips_machine.h>
28 #include <asm/mach-ar71xx/ar71xx.h>
29 #include <asm/mach-ar71xx/pci.h>
33 #define AR71XX_SYS_TYPE_LEN 64
34 #define AR71XX_BASE_FREQ 40000000
35 #define AR91XX_BASE_FREQ 5000000
36 #define AR724X_BASE_FREQ 5000000
38 enum ar71xx_mach_type ar71xx_mach
;
41 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq
);
44 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq
);
47 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq
);
49 enum ar71xx_soc_type ar71xx_soc
;
50 EXPORT_SYMBOL_GPL(ar71xx_soc
);
52 int (*ar71xx_pci_bios_init
)(unsigned nr_irqs
,
53 struct ar71xx_pci_irq
*map
) __initdata
;
55 int (*ar71xx_pci_be_handler
)(int is_fixup
);
57 static char ar71xx_sys_type
[AR71XX_SYS_TYPE_LEN
];
59 static void ar71xx_restart(char *command
)
61 ar71xx_device_stop(RESET_MODULE_FULL_CHIP
);
67 static void ar71xx_halt(void)
73 static int ar71xx_be_handler(struct pt_regs
*regs
, int is_fixup
)
77 if (ar71xx_pci_be_handler
)
78 err
= ar71xx_pci_be_handler(is_fixup
);
80 return (is_fixup
&& !err
) ? MIPS_BE_FIXUP
: MIPS_BE_FATAL
;
83 int __init
ar71xx_pci_init(unsigned nr_irqs
, struct ar71xx_pci_irq
*map
)
85 if (!ar71xx_pci_bios_init
)
88 return ar71xx_pci_bios_init(nr_irqs
, map
);
91 static void __init
ar71xx_detect_mem_size(void)
95 for (size
= AR71XX_MEM_SIZE_MIN
; size
< AR71XX_MEM_SIZE_MAX
;
97 if (!memcmp(ar71xx_detect_mem_size
,
98 ar71xx_detect_mem_size
+ size
, 1024))
102 add_memory_region(0, size
, BOOT_MEM_RAM
);
105 static void __init
ar71xx_detect_sys_type(void)
113 id
= ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID
);
114 major
= id
& REV_ID_MAJOR_MASK
;
117 case REV_ID_MAJOR_AR71XX
:
118 minor
= id
& AR71XX_REV_ID_MINOR_MASK
;
119 rev
= id
>> AR71XX_REV_ID_REVISION_SHIFT
;
120 rev
&= AR71XX_REV_ID_REVISION_MASK
;
122 case AR71XX_REV_ID_MINOR_AR7130
:
123 ar71xx_soc
= AR71XX_SOC_AR7130
;
127 case AR71XX_REV_ID_MINOR_AR7141
:
128 ar71xx_soc
= AR71XX_SOC_AR7141
;
132 case AR71XX_REV_ID_MINOR_AR7161
:
133 ar71xx_soc
= AR71XX_SOC_AR7161
;
139 case REV_ID_MAJOR_AR724X
:
140 ar71xx_soc
= AR71XX_SOC_AR7240
;
142 rev
= (id
& AR724X_REV_ID_REVISION_MASK
);
145 case REV_ID_MAJOR_AR913X
:
146 minor
= id
& AR91XX_REV_ID_MINOR_MASK
;
147 rev
= id
>> AR91XX_REV_ID_REVISION_SHIFT
;
148 rev
&= AR91XX_REV_ID_REVISION_MASK
;
150 case AR91XX_REV_ID_MINOR_AR9130
:
151 ar71xx_soc
= AR71XX_SOC_AR9130
;
155 case AR91XX_REV_ID_MINOR_AR9132
:
156 ar71xx_soc
= AR71XX_SOC_AR9132
;
163 panic("ar71xx: unknown chip id:0x%08x\n", id
);
166 sprintf(ar71xx_sys_type
, "Atheros AR%s rev %u", chip
, rev
);
169 static void __init
ar91xx_detect_sys_frequency(void)
175 pll
= ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG
);
177 div
= ((pll
>> AR91XX_PLL_DIV_SHIFT
) & AR91XX_PLL_DIV_MASK
);
178 freq
= div
* AR91XX_BASE_FREQ
;
180 ar71xx_cpu_freq
= freq
;
182 div
= ((pll
>> AR91XX_DDR_DIV_SHIFT
) & AR91XX_DDR_DIV_MASK
) + 1;
183 ar71xx_ddr_freq
= freq
/ div
;
185 div
= (((pll
>> AR91XX_AHB_DIV_SHIFT
) & AR91XX_AHB_DIV_MASK
) + 1) * 2;
186 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
189 static void __init
ar71xx_detect_sys_frequency(void)
195 pll
= ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG
);
197 div
= ((pll
>> AR71XX_PLL_DIV_SHIFT
) & AR71XX_PLL_DIV_MASK
) + 1;
198 freq
= div
* AR71XX_BASE_FREQ
;
200 div
= ((pll
>> AR71XX_CPU_DIV_SHIFT
) & AR71XX_CPU_DIV_MASK
) + 1;
201 ar71xx_cpu_freq
= freq
/ div
;
203 div
= ((pll
>> AR71XX_DDR_DIV_SHIFT
) & AR71XX_DDR_DIV_MASK
) + 1;
204 ar71xx_ddr_freq
= freq
/ div
;
206 div
= (((pll
>> AR71XX_AHB_DIV_SHIFT
) & AR71XX_AHB_DIV_MASK
) + 1) * 2;
207 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
210 static void __init
ar724x_detect_sys_frequency(void)
216 pll
= ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG
);
218 div
= ((pll
>> AR724X_PLL_DIV_SHIFT
) & AR724X_PLL_DIV_MASK
);
219 freq
= div
* AR724X_BASE_FREQ
;
221 div
= ((pll
>> AR724X_PLL_REF_DIV_SHIFT
) & AR724X_PLL_REF_DIV_MASK
);
224 ar71xx_cpu_freq
= freq
;
226 div
= ((pll
>> AR724X_DDR_DIV_SHIFT
) & AR724X_DDR_DIV_MASK
) + 1;
227 ar71xx_ddr_freq
= freq
/ div
;
229 div
= (((pll
>> AR724X_AHB_DIV_SHIFT
) & AR724X_AHB_DIV_MASK
) + 1) * 2;
230 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
233 static void __init
detect_sys_frequency(void)
235 switch (ar71xx_soc
) {
236 case AR71XX_SOC_AR7130
:
237 case AR71XX_SOC_AR7141
:
238 case AR71XX_SOC_AR7161
:
239 ar71xx_detect_sys_frequency();
242 case AR71XX_SOC_AR7240
:
243 ar724x_detect_sys_frequency();
246 case AR71XX_SOC_AR9130
:
247 case AR71XX_SOC_AR9132
:
248 ar91xx_detect_sys_frequency();
256 #ifdef CONFIG_AR71XX_EARLY_SERIAL
257 static void __init
ar71xx_early_serial_setup(void)
261 memset(&p
, 0, sizeof(p
));
263 p
.flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
;
264 p
.iotype
= UPIO_MEM32
;
265 p
.uartclk
= ar71xx_ahb_freq
;
266 p
.irq
= AR71XX_MISC_IRQ_UART
;
268 p
.mapbase
= AR71XX_UART_BASE
;
270 early_serial_setup(&p
);
273 static inline void ar71xx_early_serial_setup(void) {};
274 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
276 const char *get_system_type(void)
278 return ar71xx_sys_type
;
281 unsigned int __cpuinit
get_c0_compare_irq(void)
283 return CP0_LEGACY_COMPARE_IRQ
;
286 void __init
plat_mem_setup(void)
288 set_io_port_base(KSEG1
);
290 ar71xx_ddr_base
= ioremap_nocache(AR71XX_DDR_CTRL_BASE
,
291 AR71XX_DDR_CTRL_SIZE
);
293 ar71xx_pll_base
= ioremap_nocache(AR71XX_PLL_BASE
,
296 ar71xx_reset_base
= ioremap_nocache(AR71XX_RESET_BASE
,
299 ar71xx_gpio_base
= ioremap_nocache(AR71XX_GPIO_BASE
, AR71XX_GPIO_SIZE
);
301 ar71xx_usb_ctrl_base
= ioremap_nocache(AR71XX_USB_CTRL_BASE
,
302 AR71XX_USB_CTRL_SIZE
);
304 ar71xx_detect_mem_size();
305 ar71xx_detect_sys_type();
306 detect_sys_frequency();
309 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
311 ar71xx_cpu_freq
/ 1000000, (ar71xx_cpu_freq
/ 1000) % 1000,
312 ar71xx_ahb_freq
/ 1000000, (ar71xx_ahb_freq
/ 1000) % 1000,
313 ar71xx_ddr_freq
/ 1000000, (ar71xx_ddr_freq
/ 1000) % 1000);
315 _machine_restart
= ar71xx_restart
;
316 _machine_halt
= ar71xx_halt
;
317 pm_power_off
= ar71xx_halt
;
319 board_be_handler
= ar71xx_be_handler
;
321 ar71xx_early_serial_setup();
324 void __init
plat_time_init(void)
326 mips_hpt_frequency
= ar71xx_cpu_freq
/ 2;
329 static int __init
ar71xx_machine_setup(void)
333 ar71xx_add_device_uart();
334 ar71xx_add_device_wdt();
336 mips_machine_setup(ar71xx_mach
);
340 arch_initcall(ar71xx_machine_setup
);