2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
||
187 ath79_soc
== ATH79_SOC_QCA956X
)
193 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
198 case ATH79_SOC_AR7241
:
199 case ATH79_SOC_AR9330
:
200 case ATH79_SOC_AR9331
:
201 case ATH79_SOC_QCA9533
:
202 case ATH79_SOC_TP9343
:
203 mdio_dev
= &ath79_mdio1_device
;
204 mdio_data
= &ath79_mdio1_data
;
207 case ATH79_SOC_AR9341
:
208 case ATH79_SOC_AR9342
:
209 case ATH79_SOC_AR9344
:
210 case ATH79_SOC_QCA9556
:
211 case ATH79_SOC_QCA9558
:
212 case ATH79_SOC_QCA956X
:
214 mdio_dev
= &ath79_mdio0_device
;
215 mdio_data
= &ath79_mdio0_data
;
217 mdio_dev
= &ath79_mdio1_device
;
218 mdio_data
= &ath79_mdio1_data
;
222 case ATH79_SOC_AR7242
:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
224 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT
);
228 mdio_dev
= &ath79_mdio0_device
;
229 mdio_data
= &ath79_mdio0_data
;
233 mdio_data
->phy_mask
= phy_mask
;
236 case ATH79_SOC_AR7240
:
237 mdio_data
->is_ar7240
= 1;
239 case ATH79_SOC_AR7241
:
240 mdio_data
->builtin_switch
= 1;
243 case ATH79_SOC_AR9330
:
244 mdio_data
->is_ar9330
= 1;
246 case ATH79_SOC_AR9331
:
247 mdio_data
->builtin_switch
= 1;
250 case ATH79_SOC_AR9341
:
251 case ATH79_SOC_AR9342
:
252 case ATH79_SOC_AR9344
:
254 mdio_data
->builtin_switch
= 1;
255 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
256 mdio_data
->mdio_clock
= 6250000;
258 mdio_data
->is_ar934x
= 1;
261 case ATH79_SOC_QCA9533
:
262 case ATH79_SOC_TP9343
:
263 mdio_data
->builtin_switch
= 1;
266 case ATH79_SOC_QCA9556
:
267 case ATH79_SOC_QCA9558
:
268 mdio_data
->is_ar934x
= 1;
271 case ATH79_SOC_QCA956X
:
273 mdio_data
->builtin_switch
= 1;
280 platform_device_register(mdio_dev
);
283 struct ath79_eth_pll_data ath79_eth0_pll_data
;
284 struct ath79_eth_pll_data ath79_eth1_pll_data
;
286 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
288 struct ath79_eth_pll_data
*pll_data
;
293 pll_data
= &ath79_eth0_pll_data
;
296 pll_data
= &ath79_eth1_pll_data
;
304 pll_val
= pll_data
->pll_10
;
307 pll_val
= pll_data
->pll_100
;
310 pll_val
= pll_data
->pll_1000
;
319 static void ath79_set_speed_ge0(int speed
)
321 u32 val
= ath79_get_eth_pll(0, speed
);
323 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
324 val
, AR71XX_ETH0_PLL_SHIFT
);
325 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
328 static void ath79_set_speed_ge1(int speed
)
330 u32 val
= ath79_get_eth_pll(1, speed
);
332 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
333 val
, AR71XX_ETH1_PLL_SHIFT
);
334 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
337 static void ar7242_set_speed_ge0(int speed
)
339 u32 val
= ath79_get_eth_pll(0, speed
);
342 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
343 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
347 static void ar91xx_set_speed_ge0(int speed
)
349 u32 val
= ath79_get_eth_pll(0, speed
);
351 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
352 val
, AR913X_ETH0_PLL_SHIFT
);
353 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
356 static void ar91xx_set_speed_ge1(int speed
)
358 u32 val
= ath79_get_eth_pll(1, speed
);
360 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
361 val
, AR913X_ETH1_PLL_SHIFT
);
362 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
365 static void ar934x_set_speed_ge0(int speed
)
368 u32 val
= ath79_get_eth_pll(0, speed
);
370 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
371 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
375 static void qca955x_set_speed_xmii(int speed
)
378 u32 val
= ath79_get_eth_pll(0, speed
);
380 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
381 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
385 static void qca955x_set_speed_sgmii(int speed
)
388 u32 val
= ath79_get_eth_pll(1, speed
);
390 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
391 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
395 static void qca956x_set_speed_sgmii(int speed
)
398 u32 val
= ath79_get_eth_pll(0, speed
);
400 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
401 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
405 static void ath79_set_speed_dummy(int speed
)
409 static void ath79_ddr_no_flush(void)
413 static void ath79_ddr_flush_ge0(void)
415 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
418 static void ath79_ddr_flush_ge1(void)
420 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
423 static void ar724x_ddr_flush_ge0(void)
425 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
428 static void ar724x_ddr_flush_ge1(void)
430 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
433 static void ar91xx_ddr_flush_ge0(void)
435 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
438 static void ar91xx_ddr_flush_ge1(void)
440 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
443 static void ar933x_ddr_flush_ge0(void)
445 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
448 static void ar933x_ddr_flush_ge1(void)
450 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
453 static struct resource ath79_eth0_resources
[] = {
456 .flags
= IORESOURCE_MEM
,
457 .start
= AR71XX_GE0_BASE
,
458 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
461 .flags
= IORESOURCE_IRQ
,
462 .start
= ATH79_CPU_IRQ(4),
463 .end
= ATH79_CPU_IRQ(4),
467 struct ag71xx_platform_data ath79_eth0_data
= {
468 .reset_bit
= AR71XX_RESET_GE0_MAC
,
471 struct platform_device ath79_eth0_device
= {
474 .resource
= ath79_eth0_resources
,
475 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
477 .platform_data
= &ath79_eth0_data
,
481 static struct resource ath79_eth1_resources
[] = {
484 .flags
= IORESOURCE_MEM
,
485 .start
= AR71XX_GE1_BASE
,
486 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
489 .flags
= IORESOURCE_IRQ
,
490 .start
= ATH79_CPU_IRQ(5),
491 .end
= ATH79_CPU_IRQ(5),
495 struct ag71xx_platform_data ath79_eth1_data
= {
496 .reset_bit
= AR71XX_RESET_GE1_MAC
,
499 struct platform_device ath79_eth1_device
= {
502 .resource
= ath79_eth1_resources
,
503 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
505 .platform_data
= &ath79_eth1_data
,
509 struct ag71xx_switch_platform_data ath79_switch_data
;
511 #define AR71XX_PLL_VAL_1000 0x00110000
512 #define AR71XX_PLL_VAL_100 0x00001099
513 #define AR71XX_PLL_VAL_10 0x00991099
515 #define AR724X_PLL_VAL_1000 0x00110000
516 #define AR724X_PLL_VAL_100 0x00001099
517 #define AR724X_PLL_VAL_10 0x00991099
519 #define AR7242_PLL_VAL_1000 0x16000000
520 #define AR7242_PLL_VAL_100 0x00000101
521 #define AR7242_PLL_VAL_10 0x00001616
523 #define AR913X_PLL_VAL_1000 0x1a000000
524 #define AR913X_PLL_VAL_100 0x13000a44
525 #define AR913X_PLL_VAL_10 0x00441099
527 #define AR933X_PLL_VAL_1000 0x00110000
528 #define AR933X_PLL_VAL_100 0x00001099
529 #define AR933X_PLL_VAL_10 0x00991099
531 #define AR934X_PLL_VAL_1000 0x16000000
532 #define AR934X_PLL_VAL_100 0x00000101
533 #define AR934X_PLL_VAL_10 0x00001616
535 #define QCA956X_PLL_VAL_1000 0x03000000
536 #define QCA956X_PLL_VAL_100 0x00000101
537 #define QCA956X_PLL_VAL_10 0x00001919
539 static void __init
ath79_init_eth_pll_data(unsigned int id
)
541 struct ath79_eth_pll_data
*pll_data
;
542 u32 pll_10
, pll_100
, pll_1000
;
546 pll_data
= &ath79_eth0_pll_data
;
549 pll_data
= &ath79_eth1_pll_data
;
556 case ATH79_SOC_AR7130
:
557 case ATH79_SOC_AR7141
:
558 case ATH79_SOC_AR7161
:
559 pll_10
= AR71XX_PLL_VAL_10
;
560 pll_100
= AR71XX_PLL_VAL_100
;
561 pll_1000
= AR71XX_PLL_VAL_1000
;
564 case ATH79_SOC_AR7240
:
565 case ATH79_SOC_AR7241
:
566 pll_10
= AR724X_PLL_VAL_10
;
567 pll_100
= AR724X_PLL_VAL_100
;
568 pll_1000
= AR724X_PLL_VAL_1000
;
571 case ATH79_SOC_AR7242
:
572 pll_10
= AR7242_PLL_VAL_10
;
573 pll_100
= AR7242_PLL_VAL_100
;
574 pll_1000
= AR7242_PLL_VAL_1000
;
577 case ATH79_SOC_AR9130
:
578 case ATH79_SOC_AR9132
:
579 pll_10
= AR913X_PLL_VAL_10
;
580 pll_100
= AR913X_PLL_VAL_100
;
581 pll_1000
= AR913X_PLL_VAL_1000
;
584 case ATH79_SOC_AR9330
:
585 case ATH79_SOC_AR9331
:
586 pll_10
= AR933X_PLL_VAL_10
;
587 pll_100
= AR933X_PLL_VAL_100
;
588 pll_1000
= AR933X_PLL_VAL_1000
;
591 case ATH79_SOC_AR9341
:
592 case ATH79_SOC_AR9342
:
593 case ATH79_SOC_AR9344
:
594 case ATH79_SOC_QCA9533
:
595 case ATH79_SOC_QCA9556
:
596 case ATH79_SOC_QCA9558
:
597 case ATH79_SOC_TP9343
:
598 pll_10
= AR934X_PLL_VAL_10
;
599 pll_100
= AR934X_PLL_VAL_100
;
600 pll_1000
= AR934X_PLL_VAL_1000
;
603 case ATH79_SOC_QCA956X
:
604 pll_10
= QCA956X_PLL_VAL_10
;
605 pll_100
= QCA956X_PLL_VAL_100
;
606 pll_1000
= QCA956X_PLL_VAL_1000
;
613 if (!pll_data
->pll_10
)
614 pll_data
->pll_10
= pll_10
;
616 if (!pll_data
->pll_100
)
617 pll_data
->pll_100
= pll_100
;
619 if (!pll_data
->pll_1000
)
620 pll_data
->pll_1000
= pll_1000
;
623 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
624 struct ag71xx_platform_data
*pdata
)
631 case ATH79_SOC_AR7130
:
632 case ATH79_SOC_AR7141
:
633 case ATH79_SOC_AR7161
:
634 case ATH79_SOC_AR9130
:
635 case ATH79_SOC_AR9132
:
636 switch (pdata
->phy_if_mode
) {
637 case PHY_INTERFACE_MODE_MII
:
638 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
640 case PHY_INTERFACE_MODE_GMII
:
641 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
643 case PHY_INTERFACE_MODE_RGMII
:
644 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
646 case PHY_INTERFACE_MODE_RMII
:
647 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
652 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
655 case ATH79_SOC_AR7240
:
656 case ATH79_SOC_AR7241
:
657 case ATH79_SOC_AR9330
:
658 case ATH79_SOC_AR9331
:
659 case ATH79_SOC_QCA9533
:
660 case ATH79_SOC_TP9343
:
661 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
664 case ATH79_SOC_AR7242
:
667 case ATH79_SOC_AR9341
:
668 case ATH79_SOC_AR9342
:
669 case ATH79_SOC_AR9344
:
670 switch (pdata
->phy_if_mode
) {
671 case PHY_INTERFACE_MODE_MII
:
672 case PHY_INTERFACE_MODE_GMII
:
673 case PHY_INTERFACE_MODE_RGMII
:
674 case PHY_INTERFACE_MODE_RMII
:
681 case ATH79_SOC_QCA9556
:
682 case ATH79_SOC_QCA9558
:
683 case ATH79_SOC_QCA956X
:
684 switch (pdata
->phy_if_mode
) {
685 case PHY_INTERFACE_MODE_MII
:
686 case PHY_INTERFACE_MODE_RGMII
:
687 case PHY_INTERFACE_MODE_SGMII
:
700 case ATH79_SOC_AR7130
:
701 case ATH79_SOC_AR7141
:
702 case ATH79_SOC_AR7161
:
703 case ATH79_SOC_AR9130
:
704 case ATH79_SOC_AR9132
:
705 switch (pdata
->phy_if_mode
) {
706 case PHY_INTERFACE_MODE_RMII
:
707 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
709 case PHY_INTERFACE_MODE_RGMII
:
710 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
715 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
718 case ATH79_SOC_AR7240
:
719 case ATH79_SOC_AR7241
:
720 case ATH79_SOC_AR9330
:
721 case ATH79_SOC_AR9331
:
722 case ATH79_SOC_QCA956X
:
723 case ATH79_SOC_TP9343
:
724 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
727 case ATH79_SOC_AR7242
:
730 case ATH79_SOC_AR9341
:
731 case ATH79_SOC_AR9342
:
732 case ATH79_SOC_AR9344
:
733 case ATH79_SOC_QCA9533
:
734 switch (pdata
->phy_if_mode
) {
735 case PHY_INTERFACE_MODE_MII
:
736 case PHY_INTERFACE_MODE_GMII
:
743 case ATH79_SOC_QCA9556
:
744 case ATH79_SOC_QCA9558
:
745 switch (pdata
->phy_if_mode
) {
746 case PHY_INTERFACE_MODE_MII
:
747 case PHY_INTERFACE_MODE_RGMII
:
748 case PHY_INTERFACE_MODE_SGMII
:
764 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
769 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
771 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
772 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
774 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
776 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
777 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
782 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
787 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
789 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
791 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
792 AR934X_ETH_CFG_MII_GMAC0
|
793 AR934X_ETH_CFG_GMII_GMAC0
|
794 AR934X_ETH_CFG_SW_ONLY_MODE
|
795 AR934X_ETH_CFG_SW_PHY_SWAP
);
799 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
801 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
806 void __init
ath79_setup_ar934x_eth_rx_delay(unsigned int rxd
,
812 rxd
&= AR934X_ETH_CFG_RXD_DELAY_MASK
;
813 rxdv
&= AR934X_ETH_CFG_RDV_DELAY_MASK
;
815 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
817 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
819 t
&= ~(AR934X_ETH_CFG_RXD_DELAY_MASK
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
820 AR934X_ETH_CFG_RDV_DELAY_MASK
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
822 t
|= (rxd
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
823 rxdv
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
825 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
827 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
832 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
)
837 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
839 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
841 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
845 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
850 static int ath79_eth_instance __initdata
;
851 void __init
ath79_register_eth(unsigned int id
)
853 struct platform_device
*pdev
;
854 struct ag71xx_platform_data
*pdata
;
858 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
862 ath79_init_eth_pll_data(id
);
865 pdev
= &ath79_eth0_device
;
867 pdev
= &ath79_eth1_device
;
869 pdata
= pdev
->dev
.platform_data
;
871 pdata
->max_frame_len
= 1540;
872 pdata
->desc_pktlen_mask
= 0xfff;
874 err
= ath79_setup_phy_if_mode(id
, pdata
);
877 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
882 case ATH79_SOC_AR7130
:
884 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
885 pdata
->set_speed
= ath79_set_speed_ge0
;
887 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
888 pdata
->set_speed
= ath79_set_speed_ge1
;
892 case ATH79_SOC_AR7141
:
893 case ATH79_SOC_AR7161
:
895 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
896 pdata
->set_speed
= ath79_set_speed_ge0
;
898 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
899 pdata
->set_speed
= ath79_set_speed_ge1
;
904 case ATH79_SOC_AR7242
:
906 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
907 AR71XX_RESET_GE0_PHY
;
908 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
909 pdata
->set_speed
= ar7242_set_speed_ge0
;
911 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
912 AR71XX_RESET_GE1_PHY
;
913 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
914 pdata
->set_speed
= ath79_set_speed_dummy
;
917 pdata
->is_ar724x
= 1;
919 if (!pdata
->fifo_cfg1
)
920 pdata
->fifo_cfg1
= 0x0010ffff;
921 if (!pdata
->fifo_cfg2
)
922 pdata
->fifo_cfg2
= 0x015500aa;
923 if (!pdata
->fifo_cfg3
)
924 pdata
->fifo_cfg3
= 0x01f00140;
927 case ATH79_SOC_AR7241
:
929 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
931 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
933 case ATH79_SOC_AR7240
:
935 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
936 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
937 pdata
->set_speed
= ath79_set_speed_dummy
;
939 pdata
->phy_mask
= BIT(4);
941 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
942 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
943 pdata
->set_speed
= ath79_set_speed_dummy
;
945 pdata
->speed
= SPEED_1000
;
946 pdata
->duplex
= DUPLEX_FULL
;
947 pdata
->switch_data
= &ath79_switch_data
;
949 ath79_switch_data
.phy_poll_mask
|= BIT(4);
952 pdata
->is_ar724x
= 1;
953 if (ath79_soc
== ATH79_SOC_AR7240
)
954 pdata
->is_ar7240
= 1;
956 if (!pdata
->fifo_cfg1
)
957 pdata
->fifo_cfg1
= 0x0010ffff;
958 if (!pdata
->fifo_cfg2
)
959 pdata
->fifo_cfg2
= 0x015500aa;
960 if (!pdata
->fifo_cfg3
)
961 pdata
->fifo_cfg3
= 0x01f00140;
964 case ATH79_SOC_AR9130
:
966 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
967 pdata
->set_speed
= ar91xx_set_speed_ge0
;
969 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
970 pdata
->set_speed
= ar91xx_set_speed_ge1
;
972 pdata
->is_ar91xx
= 1;
975 case ATH79_SOC_AR9132
:
977 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
978 pdata
->set_speed
= ar91xx_set_speed_ge0
;
980 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
981 pdata
->set_speed
= ar91xx_set_speed_ge1
;
983 pdata
->is_ar91xx
= 1;
987 case ATH79_SOC_AR9330
:
988 case ATH79_SOC_AR9331
:
990 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
991 AR933X_RESET_GE0_MDIO
;
992 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
993 pdata
->set_speed
= ath79_set_speed_dummy
;
995 pdata
->phy_mask
= BIT(4);
997 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
998 AR933X_RESET_GE1_MDIO
;
999 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
1000 pdata
->set_speed
= ath79_set_speed_dummy
;
1002 pdata
->speed
= SPEED_1000
;
1003 pdata
->has_gbit
= 1;
1004 pdata
->duplex
= DUPLEX_FULL
;
1005 pdata
->switch_data
= &ath79_switch_data
;
1007 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1010 pdata
->is_ar724x
= 1;
1012 if (!pdata
->fifo_cfg1
)
1013 pdata
->fifo_cfg1
= 0x0010ffff;
1014 if (!pdata
->fifo_cfg2
)
1015 pdata
->fifo_cfg2
= 0x015500aa;
1016 if (!pdata
->fifo_cfg3
)
1017 pdata
->fifo_cfg3
= 0x01f00140;
1020 case ATH79_SOC_AR9341
:
1021 case ATH79_SOC_AR9342
:
1022 case ATH79_SOC_AR9344
:
1023 case ATH79_SOC_QCA9533
:
1025 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
1026 AR934X_RESET_GE0_MDIO
;
1027 pdata
->set_speed
= ar934x_set_speed_ge0
;
1029 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
1030 AR934X_RESET_GE1_MDIO
;
1031 pdata
->set_speed
= ath79_set_speed_dummy
;
1033 pdata
->switch_data
= &ath79_switch_data
;
1035 /* reset the built-in switch */
1036 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1037 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1040 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1041 pdata
->has_gbit
= 1;
1042 pdata
->is_ar724x
= 1;
1044 pdata
->max_frame_len
= SZ_16K
- 1;
1045 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1047 if (!pdata
->fifo_cfg1
)
1048 pdata
->fifo_cfg1
= 0x0010ffff;
1049 if (!pdata
->fifo_cfg2
)
1050 pdata
->fifo_cfg2
= 0x015500aa;
1051 if (!pdata
->fifo_cfg3
)
1052 pdata
->fifo_cfg3
= 0x01f00140;
1055 case ATH79_SOC_TP9343
:
1057 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1058 AR933X_RESET_GE0_MDIO
;
1059 pdata
->set_speed
= ath79_set_speed_dummy
;
1061 if (!pdata
->phy_mask
)
1062 pdata
->phy_mask
= BIT(4);
1064 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1065 AR933X_RESET_GE1_MDIO
;
1066 pdata
->set_speed
= ath79_set_speed_dummy
;
1068 pdata
->speed
= SPEED_1000
;
1069 pdata
->duplex
= DUPLEX_FULL
;
1070 pdata
->switch_data
= &ath79_switch_data
;
1072 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1075 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1076 pdata
->has_gbit
= 1;
1077 pdata
->is_ar724x
= 1;
1079 if (!pdata
->fifo_cfg1
)
1080 pdata
->fifo_cfg1
= 0x0010ffff;
1081 if (!pdata
->fifo_cfg2
)
1082 pdata
->fifo_cfg2
= 0x015500aa;
1083 if (!pdata
->fifo_cfg3
)
1084 pdata
->fifo_cfg3
= 0x01f00140;
1087 case ATH79_SOC_QCA9556
:
1088 case ATH79_SOC_QCA9558
:
1090 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1091 QCA955X_RESET_GE0_MDIO
;
1092 pdata
->set_speed
= qca955x_set_speed_xmii
;
1094 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1095 QCA955X_RESET_GE1_MDIO
;
1096 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1099 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1100 pdata
->has_gbit
= 1;
1101 pdata
->is_ar724x
= 1;
1104 * Limit the maximum frame length to 4095 bytes.
1105 * Although the documentation says that the hardware
1106 * limit is 16383 bytes but that does not work in
1107 * practice. It seems that the hardware only updates
1108 * the lowest 12 bits of the packet length field
1109 * in the RX descriptor.
1111 pdata
->max_frame_len
= SZ_4K
- 1;
1112 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1114 if (!pdata
->fifo_cfg1
)
1115 pdata
->fifo_cfg1
= 0x0010ffff;
1116 if (!pdata
->fifo_cfg2
)
1117 pdata
->fifo_cfg2
= 0x015500aa;
1118 if (!pdata
->fifo_cfg3
)
1119 pdata
->fifo_cfg3
= 0x01f00140;
1122 case ATH79_SOC_QCA956X
:
1124 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1125 QCA955X_RESET_GE0_MDIO
;
1126 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_SGMII
)
1127 pdata
->set_speed
= qca956x_set_speed_sgmii
;
1130 pdata
->set_speed
= ath79_set_speed_dummy
;
1132 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1133 QCA955X_RESET_GE1_MDIO
;
1135 pdata
->set_speed
= ath79_set_speed_dummy
;
1138 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1139 pdata
->has_gbit
= 1;
1140 pdata
->is_ar724x
= 1;
1142 if (!pdata
->fifo_cfg1
)
1143 pdata
->fifo_cfg1
= 0x0010ffff;
1144 if (!pdata
->fifo_cfg2
)
1145 pdata
->fifo_cfg2
= 0x015500aa;
1146 if (!pdata
->fifo_cfg3
)
1147 pdata
->fifo_cfg3
= 0x01f00140;
1154 switch (pdata
->phy_if_mode
) {
1155 case PHY_INTERFACE_MODE_GMII
:
1156 case PHY_INTERFACE_MODE_RGMII
:
1157 case PHY_INTERFACE_MODE_SGMII
:
1158 if (!pdata
->has_gbit
) {
1159 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1168 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1169 random_ether_addr(pdata
->mac_addr
);
1171 "ar71xx: using random MAC address for eth%d\n",
1172 ath79_eth_instance
);
1175 if (pdata
->mii_bus_dev
== NULL
) {
1176 switch (ath79_soc
) {
1177 case ATH79_SOC_AR9341
:
1178 case ATH79_SOC_AR9342
:
1179 case ATH79_SOC_AR9344
:
1181 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1183 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1186 case ATH79_SOC_AR7241
:
1187 case ATH79_SOC_AR9330
:
1188 case ATH79_SOC_AR9331
:
1189 case ATH79_SOC_QCA9533
:
1190 case ATH79_SOC_TP9343
:
1191 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1194 case ATH79_SOC_QCA9556
:
1195 case ATH79_SOC_QCA9558
:
1196 /* don't assign any MDIO device by default */
1200 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1205 /* Reset the device */
1206 ath79_device_reset_set(pdata
->reset_bit
);
1209 ath79_device_reset_clear(pdata
->reset_bit
);
1212 platform_device_register(pdev
);
1213 ath79_eth_instance
++;
1216 void __init
ath79_set_mac_base(unsigned char *mac
)
1218 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1221 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1225 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1226 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1229 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1230 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1232 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1233 memset(mac
, 0, ETH_ALEN
);
1234 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1239 static void __init
ath79_set_mac_base_ascii(char *str
)
1243 ath79_parse_ascii_mac(str
, mac
);
1244 ath79_set_mac_base(mac
);
1247 static int __init
ath79_ethaddr_setup(char *str
)
1249 ath79_set_mac_base_ascii(str
);
1252 __setup("ethaddr=", ath79_ethaddr_setup
);
1254 static int __init
ath79_kmac_setup(char *str
)
1256 ath79_set_mac_base_ascii(str
);
1259 __setup("kmac=", ath79_kmac_setup
);
1261 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1269 if (!src
|| !is_valid_ether_addr(src
)) {
1270 memset(dst
, '\0', ETH_ALEN
);
1274 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1280 dst
[3] = (t
>> 16) & 0xff;
1281 dst
[4] = (t
>> 8) & 0xff;
1285 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1292 if (!src
|| !is_valid_ether_addr(src
)) {
1293 memset(dst
, '\0', ETH_ALEN
);
1297 for (i
= 0; i
< ETH_ALEN
; i
++)