2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
)
192 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
197 case ATH79_SOC_AR7241
:
198 case ATH79_SOC_AR9330
:
199 case ATH79_SOC_AR9331
:
200 case ATH79_SOC_QCA9533
:
201 case ATH79_SOC_TP9343
:
202 mdio_dev
= &ath79_mdio1_device
;
203 mdio_data
= &ath79_mdio1_data
;
206 case ATH79_SOC_AR9341
:
207 case ATH79_SOC_AR9342
:
208 case ATH79_SOC_AR9344
:
209 case ATH79_SOC_QCA9556
:
210 case ATH79_SOC_QCA9558
:
211 case ATH79_SOC_QCA956X
:
213 mdio_dev
= &ath79_mdio0_device
;
214 mdio_data
= &ath79_mdio0_data
;
216 mdio_dev
= &ath79_mdio1_device
;
217 mdio_data
= &ath79_mdio1_data
;
221 case ATH79_SOC_AR7242
:
222 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
223 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
224 AR71XX_ETH0_PLL_SHIFT
);
227 mdio_dev
= &ath79_mdio0_device
;
228 mdio_data
= &ath79_mdio0_data
;
232 mdio_data
->phy_mask
= phy_mask
;
235 case ATH79_SOC_AR7240
:
236 mdio_data
->is_ar7240
= 1;
238 case ATH79_SOC_AR7241
:
239 mdio_data
->builtin_switch
= 1;
242 case ATH79_SOC_AR9330
:
243 mdio_data
->is_ar9330
= 1;
245 case ATH79_SOC_AR9331
:
246 mdio_data
->builtin_switch
= 1;
249 case ATH79_SOC_AR9341
:
250 case ATH79_SOC_AR9342
:
251 case ATH79_SOC_AR9344
:
253 mdio_data
->builtin_switch
= 1;
254 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
255 mdio_data
->mdio_clock
= 6250000;
257 mdio_data
->is_ar934x
= 1;
260 case ATH79_SOC_QCA9533
:
261 case ATH79_SOC_TP9343
:
262 mdio_data
->builtin_switch
= 1;
265 case ATH79_SOC_QCA9556
:
266 case ATH79_SOC_QCA9558
:
267 mdio_data
->is_ar934x
= 1;
270 case ATH79_SOC_QCA956X
:
272 mdio_data
->builtin_switch
= 1;
279 platform_device_register(mdio_dev
);
282 struct ath79_eth_pll_data ath79_eth0_pll_data
;
283 struct ath79_eth_pll_data ath79_eth1_pll_data
;
285 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
287 struct ath79_eth_pll_data
*pll_data
;
292 pll_data
= &ath79_eth0_pll_data
;
295 pll_data
= &ath79_eth1_pll_data
;
303 pll_val
= pll_data
->pll_10
;
306 pll_val
= pll_data
->pll_100
;
309 pll_val
= pll_data
->pll_1000
;
318 static void ath79_set_speed_ge0(int speed
)
320 u32 val
= ath79_get_eth_pll(0, speed
);
322 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
323 val
, AR71XX_ETH0_PLL_SHIFT
);
324 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
327 static void ath79_set_speed_ge1(int speed
)
329 u32 val
= ath79_get_eth_pll(1, speed
);
331 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
332 val
, AR71XX_ETH1_PLL_SHIFT
);
333 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
336 static void ar7242_set_speed_ge0(int speed
)
338 u32 val
= ath79_get_eth_pll(0, speed
);
341 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
342 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
346 static void ar91xx_set_speed_ge0(int speed
)
348 u32 val
= ath79_get_eth_pll(0, speed
);
350 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
351 val
, AR913X_ETH0_PLL_SHIFT
);
352 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
355 static void ar91xx_set_speed_ge1(int speed
)
357 u32 val
= ath79_get_eth_pll(1, speed
);
359 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
360 val
, AR913X_ETH1_PLL_SHIFT
);
361 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
364 static void ar934x_set_speed_ge0(int speed
)
367 u32 val
= ath79_get_eth_pll(0, speed
);
369 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
370 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
374 static void qca955x_set_speed_xmii(int speed
)
377 u32 val
= ath79_get_eth_pll(0, speed
);
379 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
380 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
384 static void qca955x_set_speed_sgmii(int speed
)
387 u32 val
= ath79_get_eth_pll(1, speed
);
389 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
390 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
394 static void qca956x_set_speed_sgmii(int speed
)
397 u32 val
= ath79_get_eth_pll(0, speed
);
399 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
400 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
404 static void ath79_set_speed_dummy(int speed
)
408 static void ath79_ddr_no_flush(void)
412 static void ath79_ddr_flush_ge0(void)
414 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
417 static void ath79_ddr_flush_ge1(void)
419 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
422 static void ar724x_ddr_flush_ge0(void)
424 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
427 static void ar724x_ddr_flush_ge1(void)
429 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
432 static void ar91xx_ddr_flush_ge0(void)
434 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
437 static void ar91xx_ddr_flush_ge1(void)
439 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
442 static void ar933x_ddr_flush_ge0(void)
444 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
447 static void ar933x_ddr_flush_ge1(void)
449 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
452 static struct resource ath79_eth0_resources
[] = {
455 .flags
= IORESOURCE_MEM
,
456 .start
= AR71XX_GE0_BASE
,
457 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
460 .flags
= IORESOURCE_IRQ
,
461 .start
= ATH79_CPU_IRQ(4),
462 .end
= ATH79_CPU_IRQ(4),
466 struct ag71xx_platform_data ath79_eth0_data
= {
467 .reset_bit
= AR71XX_RESET_GE0_MAC
,
470 struct platform_device ath79_eth0_device
= {
473 .resource
= ath79_eth0_resources
,
474 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
476 .platform_data
= &ath79_eth0_data
,
480 static struct resource ath79_eth1_resources
[] = {
483 .flags
= IORESOURCE_MEM
,
484 .start
= AR71XX_GE1_BASE
,
485 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
488 .flags
= IORESOURCE_IRQ
,
489 .start
= ATH79_CPU_IRQ(5),
490 .end
= ATH79_CPU_IRQ(5),
494 struct ag71xx_platform_data ath79_eth1_data
= {
495 .reset_bit
= AR71XX_RESET_GE1_MAC
,
498 struct platform_device ath79_eth1_device
= {
501 .resource
= ath79_eth1_resources
,
502 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
504 .platform_data
= &ath79_eth1_data
,
508 struct ag71xx_switch_platform_data ath79_switch_data
;
510 #define AR71XX_PLL_VAL_1000 0x00110000
511 #define AR71XX_PLL_VAL_100 0x00001099
512 #define AR71XX_PLL_VAL_10 0x00991099
514 #define AR724X_PLL_VAL_1000 0x00110000
515 #define AR724X_PLL_VAL_100 0x00001099
516 #define AR724X_PLL_VAL_10 0x00991099
518 #define AR7242_PLL_VAL_1000 0x16000000
519 #define AR7242_PLL_VAL_100 0x00000101
520 #define AR7242_PLL_VAL_10 0x00001616
522 #define AR913X_PLL_VAL_1000 0x1a000000
523 #define AR913X_PLL_VAL_100 0x13000a44
524 #define AR913X_PLL_VAL_10 0x00441099
526 #define AR933X_PLL_VAL_1000 0x00110000
527 #define AR933X_PLL_VAL_100 0x00001099
528 #define AR933X_PLL_VAL_10 0x00991099
530 #define AR934X_PLL_VAL_1000 0x16000000
531 #define AR934X_PLL_VAL_100 0x00000101
532 #define AR934X_PLL_VAL_10 0x00001616
534 #define QCA956X_PLL_VAL_1000 0x03000000
535 #define QCA956X_PLL_VAL_100 0x00000101
536 #define QCA956X_PLL_VAL_10 0x00001919
538 static void __init
ath79_init_eth_pll_data(unsigned int id
)
540 struct ath79_eth_pll_data
*pll_data
;
541 u32 pll_10
, pll_100
, pll_1000
;
545 pll_data
= &ath79_eth0_pll_data
;
548 pll_data
= &ath79_eth1_pll_data
;
555 case ATH79_SOC_AR7130
:
556 case ATH79_SOC_AR7141
:
557 case ATH79_SOC_AR7161
:
558 pll_10
= AR71XX_PLL_VAL_10
;
559 pll_100
= AR71XX_PLL_VAL_100
;
560 pll_1000
= AR71XX_PLL_VAL_1000
;
563 case ATH79_SOC_AR7240
:
564 case ATH79_SOC_AR7241
:
565 pll_10
= AR724X_PLL_VAL_10
;
566 pll_100
= AR724X_PLL_VAL_100
;
567 pll_1000
= AR724X_PLL_VAL_1000
;
570 case ATH79_SOC_AR7242
:
571 pll_10
= AR7242_PLL_VAL_10
;
572 pll_100
= AR7242_PLL_VAL_100
;
573 pll_1000
= AR7242_PLL_VAL_1000
;
576 case ATH79_SOC_AR9130
:
577 case ATH79_SOC_AR9132
:
578 pll_10
= AR913X_PLL_VAL_10
;
579 pll_100
= AR913X_PLL_VAL_100
;
580 pll_1000
= AR913X_PLL_VAL_1000
;
583 case ATH79_SOC_AR9330
:
584 case ATH79_SOC_AR9331
:
585 pll_10
= AR933X_PLL_VAL_10
;
586 pll_100
= AR933X_PLL_VAL_100
;
587 pll_1000
= AR933X_PLL_VAL_1000
;
590 case ATH79_SOC_AR9341
:
591 case ATH79_SOC_AR9342
:
592 case ATH79_SOC_AR9344
:
593 case ATH79_SOC_QCA9533
:
594 case ATH79_SOC_QCA9556
:
595 case ATH79_SOC_QCA9558
:
596 case ATH79_SOC_TP9343
:
597 pll_10
= AR934X_PLL_VAL_10
;
598 pll_100
= AR934X_PLL_VAL_100
;
599 pll_1000
= AR934X_PLL_VAL_1000
;
602 case ATH79_SOC_QCA956X
:
603 pll_10
= QCA956X_PLL_VAL_10
;
604 pll_100
= QCA956X_PLL_VAL_100
;
605 pll_1000
= QCA956X_PLL_VAL_1000
;
612 if (!pll_data
->pll_10
)
613 pll_data
->pll_10
= pll_10
;
615 if (!pll_data
->pll_100
)
616 pll_data
->pll_100
= pll_100
;
618 if (!pll_data
->pll_1000
)
619 pll_data
->pll_1000
= pll_1000
;
622 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
623 struct ag71xx_platform_data
*pdata
)
630 case ATH79_SOC_AR7130
:
631 case ATH79_SOC_AR7141
:
632 case ATH79_SOC_AR7161
:
633 case ATH79_SOC_AR9130
:
634 case ATH79_SOC_AR9132
:
635 switch (pdata
->phy_if_mode
) {
636 case PHY_INTERFACE_MODE_MII
:
637 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
639 case PHY_INTERFACE_MODE_GMII
:
640 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
642 case PHY_INTERFACE_MODE_RGMII
:
643 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
645 case PHY_INTERFACE_MODE_RMII
:
646 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
651 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
654 case ATH79_SOC_AR7240
:
655 case ATH79_SOC_AR7241
:
656 case ATH79_SOC_AR9330
:
657 case ATH79_SOC_AR9331
:
658 case ATH79_SOC_QCA9533
:
659 case ATH79_SOC_TP9343
:
660 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
663 case ATH79_SOC_AR7242
:
666 case ATH79_SOC_AR9341
:
667 case ATH79_SOC_AR9342
:
668 case ATH79_SOC_AR9344
:
669 switch (pdata
->phy_if_mode
) {
670 case PHY_INTERFACE_MODE_MII
:
671 case PHY_INTERFACE_MODE_GMII
:
672 case PHY_INTERFACE_MODE_RGMII
:
673 case PHY_INTERFACE_MODE_RMII
:
680 case ATH79_SOC_QCA9556
:
681 case ATH79_SOC_QCA9558
:
682 case ATH79_SOC_QCA956X
:
683 switch (pdata
->phy_if_mode
) {
684 case PHY_INTERFACE_MODE_MII
:
685 case PHY_INTERFACE_MODE_RGMII
:
686 case PHY_INTERFACE_MODE_SGMII
:
699 case ATH79_SOC_AR7130
:
700 case ATH79_SOC_AR7141
:
701 case ATH79_SOC_AR7161
:
702 case ATH79_SOC_AR9130
:
703 case ATH79_SOC_AR9132
:
704 switch (pdata
->phy_if_mode
) {
705 case PHY_INTERFACE_MODE_RMII
:
706 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
708 case PHY_INTERFACE_MODE_RGMII
:
709 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
714 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
717 case ATH79_SOC_AR7240
:
718 case ATH79_SOC_AR7241
:
719 case ATH79_SOC_AR9330
:
720 case ATH79_SOC_AR9331
:
721 case ATH79_SOC_QCA956X
:
722 case ATH79_SOC_TP9343
:
723 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
726 case ATH79_SOC_AR7242
:
729 case ATH79_SOC_AR9341
:
730 case ATH79_SOC_AR9342
:
731 case ATH79_SOC_AR9344
:
732 case ATH79_SOC_QCA9533
:
733 switch (pdata
->phy_if_mode
) {
734 case PHY_INTERFACE_MODE_MII
:
735 case PHY_INTERFACE_MODE_GMII
:
742 case ATH79_SOC_QCA9556
:
743 case ATH79_SOC_QCA9558
:
744 switch (pdata
->phy_if_mode
) {
745 case PHY_INTERFACE_MODE_MII
:
746 case PHY_INTERFACE_MODE_RGMII
:
747 case PHY_INTERFACE_MODE_SGMII
:
763 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
768 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
770 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
771 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
773 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
775 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
776 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
781 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
786 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
788 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
790 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
791 AR934X_ETH_CFG_MII_GMAC0
|
792 AR934X_ETH_CFG_GMII_GMAC0
|
793 AR934X_ETH_CFG_SW_ONLY_MODE
|
794 AR934X_ETH_CFG_SW_PHY_SWAP
);
798 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
800 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
805 void __init
ath79_setup_ar934x_eth_rx_delay(unsigned int rxd
,
811 rxd
&= AR934X_ETH_CFG_RXD_DELAY_MASK
;
812 rxdv
&= AR934X_ETH_CFG_RDV_DELAY_MASK
;
814 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
816 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
818 t
&= ~(AR934X_ETH_CFG_RXD_DELAY_MASK
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
819 AR934X_ETH_CFG_RDV_DELAY_MASK
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
821 t
|= (rxd
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
822 rxdv
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
824 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
826 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
831 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
)
836 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
838 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
840 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
844 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
849 static int ath79_eth_instance __initdata
;
850 void __init
ath79_register_eth(unsigned int id
)
852 struct platform_device
*pdev
;
853 struct ag71xx_platform_data
*pdata
;
857 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
861 ath79_init_eth_pll_data(id
);
864 pdev
= &ath79_eth0_device
;
866 pdev
= &ath79_eth1_device
;
868 pdata
= pdev
->dev
.platform_data
;
870 pdata
->max_frame_len
= 1540;
871 pdata
->desc_pktlen_mask
= 0xfff;
873 err
= ath79_setup_phy_if_mode(id
, pdata
);
876 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
881 case ATH79_SOC_AR7130
:
883 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
884 pdata
->set_speed
= ath79_set_speed_ge0
;
886 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
887 pdata
->set_speed
= ath79_set_speed_ge1
;
891 case ATH79_SOC_AR7141
:
892 case ATH79_SOC_AR7161
:
894 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
895 pdata
->set_speed
= ath79_set_speed_ge0
;
897 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
898 pdata
->set_speed
= ath79_set_speed_ge1
;
903 case ATH79_SOC_AR7242
:
905 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
906 AR71XX_RESET_GE0_PHY
;
907 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
908 pdata
->set_speed
= ar7242_set_speed_ge0
;
910 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
911 AR71XX_RESET_GE1_PHY
;
912 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
913 pdata
->set_speed
= ath79_set_speed_dummy
;
916 pdata
->is_ar724x
= 1;
918 if (!pdata
->fifo_cfg1
)
919 pdata
->fifo_cfg1
= 0x0010ffff;
920 if (!pdata
->fifo_cfg2
)
921 pdata
->fifo_cfg2
= 0x015500aa;
922 if (!pdata
->fifo_cfg3
)
923 pdata
->fifo_cfg3
= 0x01f00140;
926 case ATH79_SOC_AR7241
:
928 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
930 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
932 case ATH79_SOC_AR7240
:
934 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
935 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
936 pdata
->set_speed
= ath79_set_speed_dummy
;
938 pdata
->phy_mask
= BIT(4);
940 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
941 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
942 pdata
->set_speed
= ath79_set_speed_dummy
;
944 pdata
->speed
= SPEED_1000
;
945 pdata
->duplex
= DUPLEX_FULL
;
946 pdata
->switch_data
= &ath79_switch_data
;
948 ath79_switch_data
.phy_poll_mask
|= BIT(4);
951 pdata
->is_ar724x
= 1;
952 if (ath79_soc
== ATH79_SOC_AR7240
)
953 pdata
->is_ar7240
= 1;
955 if (!pdata
->fifo_cfg1
)
956 pdata
->fifo_cfg1
= 0x0010ffff;
957 if (!pdata
->fifo_cfg2
)
958 pdata
->fifo_cfg2
= 0x015500aa;
959 if (!pdata
->fifo_cfg3
)
960 pdata
->fifo_cfg3
= 0x01f00140;
963 case ATH79_SOC_AR9130
:
965 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
966 pdata
->set_speed
= ar91xx_set_speed_ge0
;
968 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
969 pdata
->set_speed
= ar91xx_set_speed_ge1
;
971 pdata
->is_ar91xx
= 1;
974 case ATH79_SOC_AR9132
:
976 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
977 pdata
->set_speed
= ar91xx_set_speed_ge0
;
979 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
980 pdata
->set_speed
= ar91xx_set_speed_ge1
;
982 pdata
->is_ar91xx
= 1;
986 case ATH79_SOC_AR9330
:
987 case ATH79_SOC_AR9331
:
989 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
990 AR933X_RESET_GE0_MDIO
;
991 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
992 pdata
->set_speed
= ath79_set_speed_dummy
;
994 pdata
->phy_mask
= BIT(4);
996 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
997 AR933X_RESET_GE1_MDIO
;
998 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
999 pdata
->set_speed
= ath79_set_speed_dummy
;
1001 pdata
->speed
= SPEED_1000
;
1002 pdata
->has_gbit
= 1;
1003 pdata
->duplex
= DUPLEX_FULL
;
1004 pdata
->switch_data
= &ath79_switch_data
;
1006 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1009 pdata
->is_ar724x
= 1;
1011 if (!pdata
->fifo_cfg1
)
1012 pdata
->fifo_cfg1
= 0x0010ffff;
1013 if (!pdata
->fifo_cfg2
)
1014 pdata
->fifo_cfg2
= 0x015500aa;
1015 if (!pdata
->fifo_cfg3
)
1016 pdata
->fifo_cfg3
= 0x01f00140;
1019 case ATH79_SOC_AR9341
:
1020 case ATH79_SOC_AR9342
:
1021 case ATH79_SOC_AR9344
:
1022 case ATH79_SOC_QCA9533
:
1024 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
1025 AR934X_RESET_GE0_MDIO
;
1026 pdata
->set_speed
= ar934x_set_speed_ge0
;
1028 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
1029 AR934X_RESET_GE1_MDIO
;
1030 pdata
->set_speed
= ath79_set_speed_dummy
;
1032 pdata
->switch_data
= &ath79_switch_data
;
1034 /* reset the built-in switch */
1035 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1036 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1039 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1040 pdata
->has_gbit
= 1;
1041 pdata
->is_ar724x
= 1;
1043 pdata
->max_frame_len
= SZ_16K
- 1;
1044 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1046 if (!pdata
->fifo_cfg1
)
1047 pdata
->fifo_cfg1
= 0x0010ffff;
1048 if (!pdata
->fifo_cfg2
)
1049 pdata
->fifo_cfg2
= 0x015500aa;
1050 if (!pdata
->fifo_cfg3
)
1051 pdata
->fifo_cfg3
= 0x01f00140;
1054 case ATH79_SOC_TP9343
:
1056 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1057 AR933X_RESET_GE0_MDIO
;
1058 pdata
->set_speed
= ath79_set_speed_dummy
;
1060 if (!pdata
->phy_mask
)
1061 pdata
->phy_mask
= BIT(4);
1063 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1064 AR933X_RESET_GE1_MDIO
;
1065 pdata
->set_speed
= ath79_set_speed_dummy
;
1067 pdata
->speed
= SPEED_1000
;
1068 pdata
->duplex
= DUPLEX_FULL
;
1069 pdata
->switch_data
= &ath79_switch_data
;
1071 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1074 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1075 pdata
->has_gbit
= 1;
1076 pdata
->is_ar724x
= 1;
1078 if (!pdata
->fifo_cfg1
)
1079 pdata
->fifo_cfg1
= 0x0010ffff;
1080 if (!pdata
->fifo_cfg2
)
1081 pdata
->fifo_cfg2
= 0x015500aa;
1082 if (!pdata
->fifo_cfg3
)
1083 pdata
->fifo_cfg3
= 0x01f00140;
1086 case ATH79_SOC_QCA9556
:
1087 case ATH79_SOC_QCA9558
:
1089 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1090 QCA955X_RESET_GE0_MDIO
;
1091 pdata
->set_speed
= qca955x_set_speed_xmii
;
1093 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1094 QCA955X_RESET_GE1_MDIO
;
1095 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1098 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1099 pdata
->has_gbit
= 1;
1100 pdata
->is_ar724x
= 1;
1103 * Limit the maximum frame length to 4095 bytes.
1104 * Although the documentation says that the hardware
1105 * limit is 16383 bytes but that does not work in
1106 * practice. It seems that the hardware only updates
1107 * the lowest 12 bits of the packet length field
1108 * in the RX descriptor.
1110 pdata
->max_frame_len
= SZ_4K
- 1;
1111 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1113 if (!pdata
->fifo_cfg1
)
1114 pdata
->fifo_cfg1
= 0x0010ffff;
1115 if (!pdata
->fifo_cfg2
)
1116 pdata
->fifo_cfg2
= 0x015500aa;
1117 if (!pdata
->fifo_cfg3
)
1118 pdata
->fifo_cfg3
= 0x01f00140;
1121 case ATH79_SOC_QCA956X
:
1123 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1124 QCA955X_RESET_GE0_MDIO
;
1125 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_SGMII
)
1126 pdata
->set_speed
= qca956x_set_speed_sgmii
;
1129 pdata
->set_speed
= ath79_set_speed_dummy
;
1131 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1132 QCA955X_RESET_GE1_MDIO
;
1134 pdata
->set_speed
= ath79_set_speed_dummy
;
1137 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1138 pdata
->has_gbit
= 1;
1139 pdata
->is_ar724x
= 1;
1141 if (!pdata
->fifo_cfg1
)
1142 pdata
->fifo_cfg1
= 0x0010ffff;
1143 if (!pdata
->fifo_cfg2
)
1144 pdata
->fifo_cfg2
= 0x015500aa;
1145 if (!pdata
->fifo_cfg3
)
1146 pdata
->fifo_cfg3
= 0x01f00140;
1153 switch (pdata
->phy_if_mode
) {
1154 case PHY_INTERFACE_MODE_GMII
:
1155 case PHY_INTERFACE_MODE_RGMII
:
1156 case PHY_INTERFACE_MODE_SGMII
:
1157 if (!pdata
->has_gbit
) {
1158 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1167 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1168 random_ether_addr(pdata
->mac_addr
);
1170 "ar71xx: using random MAC address for eth%d\n",
1171 ath79_eth_instance
);
1174 if (pdata
->mii_bus_dev
== NULL
) {
1175 switch (ath79_soc
) {
1176 case ATH79_SOC_AR9341
:
1177 case ATH79_SOC_AR9342
:
1178 case ATH79_SOC_AR9344
:
1180 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1182 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1185 case ATH79_SOC_AR7241
:
1186 case ATH79_SOC_AR9330
:
1187 case ATH79_SOC_AR9331
:
1188 case ATH79_SOC_QCA9533
:
1189 case ATH79_SOC_TP9343
:
1190 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1193 case ATH79_SOC_QCA9556
:
1194 case ATH79_SOC_QCA9558
:
1195 /* don't assign any MDIO device by default */
1199 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1204 /* Reset the device */
1205 ath79_device_reset_set(pdata
->reset_bit
);
1208 ath79_device_reset_clear(pdata
->reset_bit
);
1211 platform_device_register(pdev
);
1212 ath79_eth_instance
++;
1215 void __init
ath79_set_mac_base(unsigned char *mac
)
1217 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1220 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1224 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1225 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1228 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1229 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1231 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1232 memset(mac
, 0, ETH_ALEN
);
1233 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1238 static void __init
ath79_set_mac_base_ascii(char *str
)
1242 ath79_parse_ascii_mac(str
, mac
);
1243 ath79_set_mac_base(mac
);
1246 static int __init
ath79_ethaddr_setup(char *str
)
1248 ath79_set_mac_base_ascii(str
);
1251 __setup("ethaddr=", ath79_ethaddr_setup
);
1253 static int __init
ath79_kmac_setup(char *str
)
1255 ath79_set_mac_base_ascii(str
);
1258 __setup("kmac=", ath79_kmac_setup
);
1260 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1268 if (!src
|| !is_valid_ether_addr(src
)) {
1269 memset(dst
, '\0', ETH_ALEN
);
1273 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1279 dst
[3] = (t
>> 16) & 0xff;
1280 dst
[4] = (t
>> 8) & 0xff;
1284 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1291 if (!src
|| !is_valid_ether_addr(src
)) {
1292 memset(dst
, '\0', ETH_ALEN
);
1296 for (i
= 0; i
< ETH_ALEN
; i
++)