2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
)
192 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
197 case ATH79_SOC_AR7241
:
198 case ATH79_SOC_AR9330
:
199 case ATH79_SOC_AR9331
:
200 case ATH79_SOC_QCA9533
:
201 case ATH79_SOC_QCA9561
:
202 case ATH79_SOC_TP9343
:
203 mdio_dev
= &ath79_mdio1_device
;
204 mdio_data
= &ath79_mdio1_data
;
207 case ATH79_SOC_AR9341
:
208 case ATH79_SOC_AR9342
:
209 case ATH79_SOC_AR9344
:
210 case ATH79_SOC_QCA9556
:
211 case ATH79_SOC_QCA9558
:
213 mdio_dev
= &ath79_mdio0_device
;
214 mdio_data
= &ath79_mdio0_data
;
216 mdio_dev
= &ath79_mdio1_device
;
217 mdio_data
= &ath79_mdio1_data
;
221 case ATH79_SOC_AR7242
:
222 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
223 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
224 AR71XX_ETH0_PLL_SHIFT
);
227 mdio_dev
= &ath79_mdio0_device
;
228 mdio_data
= &ath79_mdio0_data
;
232 mdio_data
->phy_mask
= phy_mask
;
235 case ATH79_SOC_AR7240
:
236 mdio_data
->is_ar7240
= 1;
238 case ATH79_SOC_AR7241
:
239 mdio_data
->builtin_switch
= 1;
242 case ATH79_SOC_AR9330
:
243 mdio_data
->is_ar9330
= 1;
245 case ATH79_SOC_AR9331
:
246 mdio_data
->builtin_switch
= 1;
249 case ATH79_SOC_AR9341
:
250 case ATH79_SOC_AR9342
:
251 case ATH79_SOC_AR9344
:
253 mdio_data
->builtin_switch
= 1;
254 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
255 mdio_data
->mdio_clock
= 6250000;
257 mdio_data
->is_ar934x
= 1;
260 case ATH79_SOC_QCA9533
:
261 case ATH79_SOC_QCA9561
:
262 case ATH79_SOC_TP9343
:
263 mdio_data
->builtin_switch
= 1;
266 case ATH79_SOC_QCA9556
:
267 case ATH79_SOC_QCA9558
:
268 mdio_data
->is_ar934x
= 1;
275 platform_device_register(mdio_dev
);
278 struct ath79_eth_pll_data ath79_eth0_pll_data
;
279 struct ath79_eth_pll_data ath79_eth1_pll_data
;
281 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
283 struct ath79_eth_pll_data
*pll_data
;
288 pll_data
= &ath79_eth0_pll_data
;
291 pll_data
= &ath79_eth1_pll_data
;
299 pll_val
= pll_data
->pll_10
;
302 pll_val
= pll_data
->pll_100
;
305 pll_val
= pll_data
->pll_1000
;
314 static void ath79_set_speed_ge0(int speed
)
316 u32 val
= ath79_get_eth_pll(0, speed
);
318 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
319 val
, AR71XX_ETH0_PLL_SHIFT
);
320 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
323 static void ath79_set_speed_ge1(int speed
)
325 u32 val
= ath79_get_eth_pll(1, speed
);
327 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
328 val
, AR71XX_ETH1_PLL_SHIFT
);
329 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
332 static void ar7242_set_speed_ge0(int speed
)
334 u32 val
= ath79_get_eth_pll(0, speed
);
337 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
338 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
342 static void ar91xx_set_speed_ge0(int speed
)
344 u32 val
= ath79_get_eth_pll(0, speed
);
346 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
347 val
, AR913X_ETH0_PLL_SHIFT
);
348 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
351 static void ar91xx_set_speed_ge1(int speed
)
353 u32 val
= ath79_get_eth_pll(1, speed
);
355 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
356 val
, AR913X_ETH1_PLL_SHIFT
);
357 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
360 static void ar934x_set_speed_ge0(int speed
)
363 u32 val
= ath79_get_eth_pll(0, speed
);
365 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
366 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
370 static void qca955x_set_speed_xmii(int speed
)
373 u32 val
= ath79_get_eth_pll(0, speed
);
375 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
376 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
380 static void qca955x_set_speed_sgmii(int speed
)
383 u32 val
= ath79_get_eth_pll(1, speed
);
385 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
386 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
390 static void ath79_set_speed_dummy(int speed
)
394 static void ath79_ddr_no_flush(void)
398 static void ath79_ddr_flush_ge0(void)
400 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
403 static void ath79_ddr_flush_ge1(void)
405 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
408 static void ar724x_ddr_flush_ge0(void)
410 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
413 static void ar724x_ddr_flush_ge1(void)
415 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
418 static void ar91xx_ddr_flush_ge0(void)
420 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
423 static void ar91xx_ddr_flush_ge1(void)
425 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
428 static void ar933x_ddr_flush_ge0(void)
430 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
433 static void ar933x_ddr_flush_ge1(void)
435 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
438 static struct resource ath79_eth0_resources
[] = {
441 .flags
= IORESOURCE_MEM
,
442 .start
= AR71XX_GE0_BASE
,
443 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
446 .flags
= IORESOURCE_IRQ
,
447 .start
= ATH79_CPU_IRQ(4),
448 .end
= ATH79_CPU_IRQ(4),
452 struct ag71xx_platform_data ath79_eth0_data
= {
453 .reset_bit
= AR71XX_RESET_GE0_MAC
,
456 struct platform_device ath79_eth0_device
= {
459 .resource
= ath79_eth0_resources
,
460 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
462 .platform_data
= &ath79_eth0_data
,
466 static struct resource ath79_eth1_resources
[] = {
469 .flags
= IORESOURCE_MEM
,
470 .start
= AR71XX_GE1_BASE
,
471 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
474 .flags
= IORESOURCE_IRQ
,
475 .start
= ATH79_CPU_IRQ(5),
476 .end
= ATH79_CPU_IRQ(5),
480 struct ag71xx_platform_data ath79_eth1_data
= {
481 .reset_bit
= AR71XX_RESET_GE1_MAC
,
484 struct platform_device ath79_eth1_device
= {
487 .resource
= ath79_eth1_resources
,
488 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
490 .platform_data
= &ath79_eth1_data
,
494 struct ag71xx_switch_platform_data ath79_switch_data
;
496 #define AR71XX_PLL_VAL_1000 0x00110000
497 #define AR71XX_PLL_VAL_100 0x00001099
498 #define AR71XX_PLL_VAL_10 0x00991099
500 #define AR724X_PLL_VAL_1000 0x00110000
501 #define AR724X_PLL_VAL_100 0x00001099
502 #define AR724X_PLL_VAL_10 0x00991099
504 #define AR7242_PLL_VAL_1000 0x16000000
505 #define AR7242_PLL_VAL_100 0x00000101
506 #define AR7242_PLL_VAL_10 0x00001616
508 #define AR913X_PLL_VAL_1000 0x1a000000
509 #define AR913X_PLL_VAL_100 0x13000a44
510 #define AR913X_PLL_VAL_10 0x00441099
512 #define AR933X_PLL_VAL_1000 0x00110000
513 #define AR933X_PLL_VAL_100 0x00001099
514 #define AR933X_PLL_VAL_10 0x00991099
516 #define AR934X_PLL_VAL_1000 0x16000000
517 #define AR934X_PLL_VAL_100 0x00000101
518 #define AR934X_PLL_VAL_10 0x00001616
520 static void __init
ath79_init_eth_pll_data(unsigned int id
)
522 struct ath79_eth_pll_data
*pll_data
;
523 u32 pll_10
, pll_100
, pll_1000
;
527 pll_data
= &ath79_eth0_pll_data
;
530 pll_data
= &ath79_eth1_pll_data
;
537 case ATH79_SOC_AR7130
:
538 case ATH79_SOC_AR7141
:
539 case ATH79_SOC_AR7161
:
540 pll_10
= AR71XX_PLL_VAL_10
;
541 pll_100
= AR71XX_PLL_VAL_100
;
542 pll_1000
= AR71XX_PLL_VAL_1000
;
545 case ATH79_SOC_AR7240
:
546 case ATH79_SOC_AR7241
:
547 pll_10
= AR724X_PLL_VAL_10
;
548 pll_100
= AR724X_PLL_VAL_100
;
549 pll_1000
= AR724X_PLL_VAL_1000
;
552 case ATH79_SOC_AR7242
:
553 pll_10
= AR7242_PLL_VAL_10
;
554 pll_100
= AR7242_PLL_VAL_100
;
555 pll_1000
= AR7242_PLL_VAL_1000
;
558 case ATH79_SOC_AR9130
:
559 case ATH79_SOC_AR9132
:
560 pll_10
= AR913X_PLL_VAL_10
;
561 pll_100
= AR913X_PLL_VAL_100
;
562 pll_1000
= AR913X_PLL_VAL_1000
;
565 case ATH79_SOC_AR9330
:
566 case ATH79_SOC_AR9331
:
567 pll_10
= AR933X_PLL_VAL_10
;
568 pll_100
= AR933X_PLL_VAL_100
;
569 pll_1000
= AR933X_PLL_VAL_1000
;
572 case ATH79_SOC_AR9341
:
573 case ATH79_SOC_AR9342
:
574 case ATH79_SOC_AR9344
:
575 case ATH79_SOC_QCA9533
:
576 case ATH79_SOC_QCA9556
:
577 case ATH79_SOC_QCA9558
:
578 case ATH79_SOC_QCA9561
:
579 case ATH79_SOC_TP9343
:
580 pll_10
= AR934X_PLL_VAL_10
;
581 pll_100
= AR934X_PLL_VAL_100
;
582 pll_1000
= AR934X_PLL_VAL_1000
;
589 if (!pll_data
->pll_10
)
590 pll_data
->pll_10
= pll_10
;
592 if (!pll_data
->pll_100
)
593 pll_data
->pll_100
= pll_100
;
595 if (!pll_data
->pll_1000
)
596 pll_data
->pll_1000
= pll_1000
;
599 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
600 struct ag71xx_platform_data
*pdata
)
607 case ATH79_SOC_AR7130
:
608 case ATH79_SOC_AR7141
:
609 case ATH79_SOC_AR7161
:
610 case ATH79_SOC_AR9130
:
611 case ATH79_SOC_AR9132
:
612 switch (pdata
->phy_if_mode
) {
613 case PHY_INTERFACE_MODE_MII
:
614 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
616 case PHY_INTERFACE_MODE_GMII
:
617 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
619 case PHY_INTERFACE_MODE_RGMII
:
620 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
622 case PHY_INTERFACE_MODE_RMII
:
623 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
628 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
631 case ATH79_SOC_AR7240
:
632 case ATH79_SOC_AR7241
:
633 case ATH79_SOC_AR9330
:
634 case ATH79_SOC_AR9331
:
635 case ATH79_SOC_QCA9533
:
636 case ATH79_SOC_TP9343
:
637 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
640 case ATH79_SOC_AR7242
:
643 case ATH79_SOC_AR9341
:
644 case ATH79_SOC_AR9342
:
645 case ATH79_SOC_AR9344
:
646 switch (pdata
->phy_if_mode
) {
647 case PHY_INTERFACE_MODE_MII
:
648 case PHY_INTERFACE_MODE_GMII
:
649 case PHY_INTERFACE_MODE_RGMII
:
650 case PHY_INTERFACE_MODE_RMII
:
657 case ATH79_SOC_QCA9556
:
658 case ATH79_SOC_QCA9558
:
659 switch (pdata
->phy_if_mode
) {
660 case PHY_INTERFACE_MODE_MII
:
661 case PHY_INTERFACE_MODE_RGMII
:
662 case PHY_INTERFACE_MODE_SGMII
:
669 case ATH79_SOC_QCA9561
:
670 if (!pdata
->phy_if_mode
)
671 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
680 case ATH79_SOC_AR7130
:
681 case ATH79_SOC_AR7141
:
682 case ATH79_SOC_AR7161
:
683 case ATH79_SOC_AR9130
:
684 case ATH79_SOC_AR9132
:
685 switch (pdata
->phy_if_mode
) {
686 case PHY_INTERFACE_MODE_RMII
:
687 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
689 case PHY_INTERFACE_MODE_RGMII
:
690 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
695 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
698 case ATH79_SOC_AR7240
:
699 case ATH79_SOC_AR7241
:
700 case ATH79_SOC_AR9330
:
701 case ATH79_SOC_AR9331
:
702 case ATH79_SOC_QCA9561
:
703 case ATH79_SOC_TP9343
:
704 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
707 case ATH79_SOC_AR7242
:
710 case ATH79_SOC_AR9341
:
711 case ATH79_SOC_AR9342
:
712 case ATH79_SOC_AR9344
:
713 case ATH79_SOC_QCA9533
:
714 switch (pdata
->phy_if_mode
) {
715 case PHY_INTERFACE_MODE_MII
:
716 case PHY_INTERFACE_MODE_GMII
:
723 case ATH79_SOC_QCA9556
:
724 case ATH79_SOC_QCA9558
:
725 switch (pdata
->phy_if_mode
) {
726 case PHY_INTERFACE_MODE_MII
:
727 case PHY_INTERFACE_MODE_RGMII
:
728 case PHY_INTERFACE_MODE_SGMII
:
744 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
749 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
751 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
752 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
754 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
756 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
757 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
762 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
767 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
769 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
771 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
772 AR934X_ETH_CFG_MII_GMAC0
|
773 AR934X_ETH_CFG_GMII_GMAC0
|
774 AR934X_ETH_CFG_SW_ONLY_MODE
|
775 AR934X_ETH_CFG_SW_PHY_SWAP
);
779 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
781 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
786 void __init
ath79_setup_ar934x_eth_rx_delay(unsigned int rxd
,
792 rxd
&= AR934X_ETH_CFG_RXD_DELAY_MASK
;
793 rxdv
&= AR934X_ETH_CFG_RDV_DELAY_MASK
;
795 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
797 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
799 t
&= ~(AR934X_ETH_CFG_RXD_DELAY_MASK
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
800 AR934X_ETH_CFG_RDV_DELAY_MASK
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
802 t
|= (rxd
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
803 rxdv
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
805 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
807 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
812 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
)
817 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
819 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
821 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
825 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
830 static int ath79_eth_instance __initdata
;
831 void __init
ath79_register_eth(unsigned int id
)
833 struct platform_device
*pdev
;
834 struct ag71xx_platform_data
*pdata
;
838 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
842 ath79_init_eth_pll_data(id
);
845 pdev
= &ath79_eth0_device
;
847 pdev
= &ath79_eth1_device
;
849 pdata
= pdev
->dev
.platform_data
;
851 pdata
->max_frame_len
= 1540;
852 pdata
->desc_pktlen_mask
= 0xfff;
854 err
= ath79_setup_phy_if_mode(id
, pdata
);
857 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
862 case ATH79_SOC_AR7130
:
864 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
865 pdata
->set_speed
= ath79_set_speed_ge0
;
867 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
868 pdata
->set_speed
= ath79_set_speed_ge1
;
872 case ATH79_SOC_AR7141
:
873 case ATH79_SOC_AR7161
:
875 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
876 pdata
->set_speed
= ath79_set_speed_ge0
;
878 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
879 pdata
->set_speed
= ath79_set_speed_ge1
;
884 case ATH79_SOC_AR7242
:
886 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
887 AR71XX_RESET_GE0_PHY
;
888 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
889 pdata
->set_speed
= ar7242_set_speed_ge0
;
891 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
892 AR71XX_RESET_GE1_PHY
;
893 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
894 pdata
->set_speed
= ath79_set_speed_dummy
;
897 pdata
->is_ar724x
= 1;
899 if (!pdata
->fifo_cfg1
)
900 pdata
->fifo_cfg1
= 0x0010ffff;
901 if (!pdata
->fifo_cfg2
)
902 pdata
->fifo_cfg2
= 0x015500aa;
903 if (!pdata
->fifo_cfg3
)
904 pdata
->fifo_cfg3
= 0x01f00140;
907 case ATH79_SOC_AR7241
:
909 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
911 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
913 case ATH79_SOC_AR7240
:
915 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
916 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
917 pdata
->set_speed
= ath79_set_speed_dummy
;
919 pdata
->phy_mask
= BIT(4);
921 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
922 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
923 pdata
->set_speed
= ath79_set_speed_dummy
;
925 pdata
->speed
= SPEED_1000
;
926 pdata
->duplex
= DUPLEX_FULL
;
927 pdata
->switch_data
= &ath79_switch_data
;
929 ath79_switch_data
.phy_poll_mask
|= BIT(4);
932 pdata
->is_ar724x
= 1;
933 if (ath79_soc
== ATH79_SOC_AR7240
)
934 pdata
->is_ar7240
= 1;
936 if (!pdata
->fifo_cfg1
)
937 pdata
->fifo_cfg1
= 0x0010ffff;
938 if (!pdata
->fifo_cfg2
)
939 pdata
->fifo_cfg2
= 0x015500aa;
940 if (!pdata
->fifo_cfg3
)
941 pdata
->fifo_cfg3
= 0x01f00140;
944 case ATH79_SOC_AR9130
:
946 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
947 pdata
->set_speed
= ar91xx_set_speed_ge0
;
949 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
950 pdata
->set_speed
= ar91xx_set_speed_ge1
;
952 pdata
->is_ar91xx
= 1;
955 case ATH79_SOC_AR9132
:
957 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
958 pdata
->set_speed
= ar91xx_set_speed_ge0
;
960 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
961 pdata
->set_speed
= ar91xx_set_speed_ge1
;
963 pdata
->is_ar91xx
= 1;
967 case ATH79_SOC_AR9330
:
968 case ATH79_SOC_AR9331
:
970 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
971 AR933X_RESET_GE0_MDIO
;
972 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
973 pdata
->set_speed
= ath79_set_speed_dummy
;
975 pdata
->phy_mask
= BIT(4);
977 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
978 AR933X_RESET_GE1_MDIO
;
979 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
980 pdata
->set_speed
= ath79_set_speed_dummy
;
982 pdata
->speed
= SPEED_1000
;
984 pdata
->duplex
= DUPLEX_FULL
;
985 pdata
->switch_data
= &ath79_switch_data
;
987 ath79_switch_data
.phy_poll_mask
|= BIT(4);
990 pdata
->is_ar724x
= 1;
992 if (!pdata
->fifo_cfg1
)
993 pdata
->fifo_cfg1
= 0x0010ffff;
994 if (!pdata
->fifo_cfg2
)
995 pdata
->fifo_cfg2
= 0x015500aa;
996 if (!pdata
->fifo_cfg3
)
997 pdata
->fifo_cfg3
= 0x01f00140;
1000 case ATH79_SOC_AR9341
:
1001 case ATH79_SOC_AR9342
:
1002 case ATH79_SOC_AR9344
:
1003 case ATH79_SOC_QCA9533
:
1005 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
1006 AR934X_RESET_GE0_MDIO
;
1007 pdata
->set_speed
= ar934x_set_speed_ge0
;
1009 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
1010 AR934X_RESET_GE1_MDIO
;
1011 pdata
->set_speed
= ath79_set_speed_dummy
;
1013 pdata
->switch_data
= &ath79_switch_data
;
1015 /* reset the built-in switch */
1016 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1017 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1020 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1021 pdata
->has_gbit
= 1;
1022 pdata
->is_ar724x
= 1;
1024 pdata
->max_frame_len
= SZ_16K
- 1;
1025 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1027 if (!pdata
->fifo_cfg1
)
1028 pdata
->fifo_cfg1
= 0x0010ffff;
1029 if (!pdata
->fifo_cfg2
)
1030 pdata
->fifo_cfg2
= 0x015500aa;
1031 if (!pdata
->fifo_cfg3
)
1032 pdata
->fifo_cfg3
= 0x01f00140;
1035 case ATH79_SOC_QCA9561
:
1036 case ATH79_SOC_TP9343
:
1038 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1039 AR933X_RESET_GE0_MDIO
;
1040 pdata
->set_speed
= ath79_set_speed_dummy
;
1042 if (!pdata
->phy_mask
)
1043 pdata
->phy_mask
= BIT(4);
1045 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1046 AR933X_RESET_GE1_MDIO
;
1047 pdata
->set_speed
= ath79_set_speed_dummy
;
1049 pdata
->speed
= SPEED_1000
;
1050 pdata
->duplex
= DUPLEX_FULL
;
1051 pdata
->switch_data
= &ath79_switch_data
;
1053 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1056 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1057 pdata
->has_gbit
= 1;
1058 pdata
->is_ar724x
= 1;
1060 if (!pdata
->fifo_cfg1
)
1061 pdata
->fifo_cfg1
= 0x0010ffff;
1062 if (!pdata
->fifo_cfg2
)
1063 pdata
->fifo_cfg2
= 0x015500aa;
1064 if (!pdata
->fifo_cfg3
)
1065 pdata
->fifo_cfg3
= 0x01f00140;
1068 case ATH79_SOC_QCA9556
:
1069 case ATH79_SOC_QCA9558
:
1071 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1072 QCA955X_RESET_GE0_MDIO
;
1073 pdata
->set_speed
= qca955x_set_speed_xmii
;
1075 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1076 QCA955X_RESET_GE1_MDIO
;
1077 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1080 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1081 pdata
->has_gbit
= 1;
1082 pdata
->is_ar724x
= 1;
1085 * Limit the maximum frame length to 4095 bytes.
1086 * Although the documentation says that the hardware
1087 * limit is 16383 bytes but that does not work in
1088 * practice. It seems that the hardware only updates
1089 * the lowest 12 bits of the packet length field
1090 * in the RX descriptor.
1092 pdata
->max_frame_len
= SZ_4K
- 1;
1093 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1095 if (!pdata
->fifo_cfg1
)
1096 pdata
->fifo_cfg1
= 0x0010ffff;
1097 if (!pdata
->fifo_cfg2
)
1098 pdata
->fifo_cfg2
= 0x015500aa;
1099 if (!pdata
->fifo_cfg3
)
1100 pdata
->fifo_cfg3
= 0x01f00140;
1107 switch (pdata
->phy_if_mode
) {
1108 case PHY_INTERFACE_MODE_GMII
:
1109 case PHY_INTERFACE_MODE_RGMII
:
1110 case PHY_INTERFACE_MODE_SGMII
:
1111 if (!pdata
->has_gbit
) {
1112 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1121 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1122 random_ether_addr(pdata
->mac_addr
);
1124 "ar71xx: using random MAC address for eth%d\n",
1125 ath79_eth_instance
);
1128 if (pdata
->mii_bus_dev
== NULL
) {
1129 switch (ath79_soc
) {
1130 case ATH79_SOC_AR9341
:
1131 case ATH79_SOC_AR9342
:
1132 case ATH79_SOC_AR9344
:
1134 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1136 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1139 case ATH79_SOC_AR7241
:
1140 case ATH79_SOC_AR9330
:
1141 case ATH79_SOC_AR9331
:
1142 case ATH79_SOC_QCA9533
:
1143 case ATH79_SOC_QCA9561
:
1144 case ATH79_SOC_TP9343
:
1145 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1148 case ATH79_SOC_QCA9556
:
1149 case ATH79_SOC_QCA9558
:
1150 /* don't assign any MDIO device by default */
1154 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1159 /* Reset the device */
1160 ath79_device_reset_set(pdata
->reset_bit
);
1163 ath79_device_reset_clear(pdata
->reset_bit
);
1166 platform_device_register(pdev
);
1167 ath79_eth_instance
++;
1170 void __init
ath79_set_mac_base(unsigned char *mac
)
1172 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1175 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1179 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1180 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1183 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1184 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1186 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1187 memset(mac
, 0, ETH_ALEN
);
1188 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1193 static void __init
ath79_set_mac_base_ascii(char *str
)
1197 ath79_parse_ascii_mac(str
, mac
);
1198 ath79_set_mac_base(mac
);
1201 static int __init
ath79_ethaddr_setup(char *str
)
1203 ath79_set_mac_base_ascii(str
);
1206 __setup("ethaddr=", ath79_ethaddr_setup
);
1208 static int __init
ath79_kmac_setup(char *str
)
1210 ath79_set_mac_base_ascii(str
);
1213 __setup("kmac=", ath79_kmac_setup
);
1215 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1223 if (!src
|| !is_valid_ether_addr(src
)) {
1224 memset(dst
, '\0', ETH_ALEN
);
1228 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1234 dst
[3] = (t
>> 16) & 0xff;
1235 dst
[4] = (t
>> 8) & 0xff;
1239 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1246 if (!src
|| !is_valid_ether_addr(src
)) {
1247 memset(dst
, '\0', ETH_ALEN
);
1251 for (i
= 0; i
< ETH_ALEN
; i
++)