2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
||
187 ath79_soc
== ATH79_SOC_QCA956X
)
193 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
198 case ATH79_SOC_AR7241
:
199 case ATH79_SOC_AR9330
:
200 case ATH79_SOC_AR9331
:
201 case ATH79_SOC_QCA9533
:
202 case ATH79_SOC_TP9343
:
203 mdio_dev
= &ath79_mdio1_device
;
204 mdio_data
= &ath79_mdio1_data
;
207 case ATH79_SOC_AR9341
:
208 case ATH79_SOC_AR9342
:
209 case ATH79_SOC_AR9344
:
210 case ATH79_SOC_QCA9556
:
211 case ATH79_SOC_QCA9558
:
212 case ATH79_SOC_QCA956X
:
214 mdio_dev
= &ath79_mdio0_device
;
215 mdio_data
= &ath79_mdio0_data
;
217 mdio_dev
= &ath79_mdio1_device
;
218 mdio_data
= &ath79_mdio1_data
;
222 case ATH79_SOC_AR7242
:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
224 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT
);
228 mdio_dev
= &ath79_mdio0_device
;
229 mdio_data
= &ath79_mdio0_data
;
233 mdio_data
->phy_mask
= phy_mask
;
236 case ATH79_SOC_AR7240
:
237 mdio_data
->is_ar7240
= 1;
239 case ATH79_SOC_AR7241
:
240 mdio_data
->builtin_switch
= 1;
243 case ATH79_SOC_AR9330
:
244 mdio_data
->is_ar9330
= 1;
246 case ATH79_SOC_AR9331
:
247 mdio_data
->builtin_switch
= 1;
250 case ATH79_SOC_AR9341
:
251 case ATH79_SOC_AR9342
:
252 case ATH79_SOC_AR9344
:
254 mdio_data
->builtin_switch
= 1;
255 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
256 mdio_data
->mdio_clock
= 6250000;
258 mdio_data
->is_ar934x
= 1;
261 case ATH79_SOC_QCA9533
:
262 case ATH79_SOC_TP9343
:
263 mdio_data
->builtin_switch
= 1;
266 case ATH79_SOC_QCA9556
:
267 case ATH79_SOC_QCA9558
:
268 mdio_data
->is_ar934x
= 1;
271 case ATH79_SOC_QCA956X
:
273 mdio_data
->builtin_switch
= 1;
274 mdio_data
->is_ar934x
= 1;
281 platform_device_register(mdio_dev
);
284 struct ath79_eth_pll_data ath79_eth0_pll_data
;
285 struct ath79_eth_pll_data ath79_eth1_pll_data
;
287 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
289 struct ath79_eth_pll_data
*pll_data
;
294 pll_data
= &ath79_eth0_pll_data
;
297 pll_data
= &ath79_eth1_pll_data
;
305 pll_val
= pll_data
->pll_10
;
308 pll_val
= pll_data
->pll_100
;
311 pll_val
= pll_data
->pll_1000
;
320 static void ath79_set_speed_ge0(int speed
)
322 u32 val
= ath79_get_eth_pll(0, speed
);
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
325 val
, AR71XX_ETH0_PLL_SHIFT
);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
329 static void ath79_set_speed_ge1(int speed
)
331 u32 val
= ath79_get_eth_pll(1, speed
);
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
334 val
, AR71XX_ETH1_PLL_SHIFT
);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
338 static void ar7242_set_speed_ge0(int speed
)
340 u32 val
= ath79_get_eth_pll(0, speed
);
343 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
344 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
348 static void ar91xx_set_speed_ge0(int speed
)
350 u32 val
= ath79_get_eth_pll(0, speed
);
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
353 val
, AR913X_ETH0_PLL_SHIFT
);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
357 static void ar91xx_set_speed_ge1(int speed
)
359 u32 val
= ath79_get_eth_pll(1, speed
);
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
362 val
, AR913X_ETH1_PLL_SHIFT
);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
366 static void ar934x_set_speed_ge0(int speed
)
369 u32 val
= ath79_get_eth_pll(0, speed
);
371 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
372 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
376 static void qca955x_set_speed_xmii(int speed
)
379 u32 val
= ath79_get_eth_pll(0, speed
);
381 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
382 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
386 static void qca955x_set_speed_sgmii(int speed
)
389 u32 val
= ath79_get_eth_pll(1, speed
);
391 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
392 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
396 static void qca956x_set_speed_sgmii(int speed
)
399 u32 val
= ath79_get_eth_pll(0, speed
);
401 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
402 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
406 static void ath79_set_speed_dummy(int speed
)
410 static void ath79_ddr_no_flush(void)
414 static void ath79_ddr_flush_ge0(void)
416 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
419 static void ath79_ddr_flush_ge1(void)
421 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
424 static void ar724x_ddr_flush_ge0(void)
426 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
429 static void ar724x_ddr_flush_ge1(void)
431 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
434 static void ar91xx_ddr_flush_ge0(void)
436 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
439 static void ar91xx_ddr_flush_ge1(void)
441 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
444 static void ar933x_ddr_flush_ge0(void)
446 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
449 static void ar933x_ddr_flush_ge1(void)
451 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
454 static struct resource ath79_eth0_resources
[] = {
457 .flags
= IORESOURCE_MEM
,
458 .start
= AR71XX_GE0_BASE
,
459 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
462 .flags
= IORESOURCE_IRQ
,
463 .start
= ATH79_CPU_IRQ(4),
464 .end
= ATH79_CPU_IRQ(4),
468 struct ag71xx_platform_data ath79_eth0_data
= {
469 .reset_bit
= AR71XX_RESET_GE0_MAC
,
472 struct platform_device ath79_eth0_device
= {
475 .resource
= ath79_eth0_resources
,
476 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
478 .platform_data
= &ath79_eth0_data
,
482 static struct resource ath79_eth1_resources
[] = {
485 .flags
= IORESOURCE_MEM
,
486 .start
= AR71XX_GE1_BASE
,
487 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
490 .flags
= IORESOURCE_IRQ
,
491 .start
= ATH79_CPU_IRQ(5),
492 .end
= ATH79_CPU_IRQ(5),
496 struct ag71xx_platform_data ath79_eth1_data
= {
497 .reset_bit
= AR71XX_RESET_GE1_MAC
,
500 struct platform_device ath79_eth1_device
= {
503 .resource
= ath79_eth1_resources
,
504 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
506 .platform_data
= &ath79_eth1_data
,
510 struct ag71xx_switch_platform_data ath79_switch_data
;
512 #define AR71XX_PLL_VAL_1000 0x00110000
513 #define AR71XX_PLL_VAL_100 0x00001099
514 #define AR71XX_PLL_VAL_10 0x00991099
516 #define AR724X_PLL_VAL_1000 0x00110000
517 #define AR724X_PLL_VAL_100 0x00001099
518 #define AR724X_PLL_VAL_10 0x00991099
520 #define AR7242_PLL_VAL_1000 0x16000000
521 #define AR7242_PLL_VAL_100 0x00000101
522 #define AR7242_PLL_VAL_10 0x00001616
524 #define AR913X_PLL_VAL_1000 0x1a000000
525 #define AR913X_PLL_VAL_100 0x13000a44
526 #define AR913X_PLL_VAL_10 0x00441099
528 #define AR933X_PLL_VAL_1000 0x00110000
529 #define AR933X_PLL_VAL_100 0x00001099
530 #define AR933X_PLL_VAL_10 0x00991099
532 #define AR934X_PLL_VAL_1000 0x16000000
533 #define AR934X_PLL_VAL_100 0x00000101
534 #define AR934X_PLL_VAL_10 0x00001616
536 #define QCA956X_PLL_VAL_1000 0x03000000
537 #define QCA956X_PLL_VAL_100 0x00000101
538 #define QCA956X_PLL_VAL_10 0x00001919
540 static void __init
ath79_init_eth_pll_data(unsigned int id
)
542 struct ath79_eth_pll_data
*pll_data
;
543 u32 pll_10
, pll_100
, pll_1000
;
547 pll_data
= &ath79_eth0_pll_data
;
550 pll_data
= &ath79_eth1_pll_data
;
557 case ATH79_SOC_AR7130
:
558 case ATH79_SOC_AR7141
:
559 case ATH79_SOC_AR7161
:
560 pll_10
= AR71XX_PLL_VAL_10
;
561 pll_100
= AR71XX_PLL_VAL_100
;
562 pll_1000
= AR71XX_PLL_VAL_1000
;
565 case ATH79_SOC_AR7240
:
566 case ATH79_SOC_AR7241
:
567 pll_10
= AR724X_PLL_VAL_10
;
568 pll_100
= AR724X_PLL_VAL_100
;
569 pll_1000
= AR724X_PLL_VAL_1000
;
572 case ATH79_SOC_AR7242
:
573 pll_10
= AR7242_PLL_VAL_10
;
574 pll_100
= AR7242_PLL_VAL_100
;
575 pll_1000
= AR7242_PLL_VAL_1000
;
578 case ATH79_SOC_AR9130
:
579 case ATH79_SOC_AR9132
:
580 pll_10
= AR913X_PLL_VAL_10
;
581 pll_100
= AR913X_PLL_VAL_100
;
582 pll_1000
= AR913X_PLL_VAL_1000
;
585 case ATH79_SOC_AR9330
:
586 case ATH79_SOC_AR9331
:
587 pll_10
= AR933X_PLL_VAL_10
;
588 pll_100
= AR933X_PLL_VAL_100
;
589 pll_1000
= AR933X_PLL_VAL_1000
;
592 case ATH79_SOC_AR9341
:
593 case ATH79_SOC_AR9342
:
594 case ATH79_SOC_AR9344
:
595 case ATH79_SOC_QCA9533
:
596 case ATH79_SOC_QCA9556
:
597 case ATH79_SOC_QCA9558
:
598 case ATH79_SOC_TP9343
:
599 pll_10
= AR934X_PLL_VAL_10
;
600 pll_100
= AR934X_PLL_VAL_100
;
601 pll_1000
= AR934X_PLL_VAL_1000
;
604 case ATH79_SOC_QCA956X
:
605 pll_10
= QCA956X_PLL_VAL_10
;
606 pll_100
= QCA956X_PLL_VAL_100
;
607 pll_1000
= QCA956X_PLL_VAL_1000
;
614 if (!pll_data
->pll_10
)
615 pll_data
->pll_10
= pll_10
;
617 if (!pll_data
->pll_100
)
618 pll_data
->pll_100
= pll_100
;
620 if (!pll_data
->pll_1000
)
621 pll_data
->pll_1000
= pll_1000
;
624 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
625 struct ag71xx_platform_data
*pdata
)
632 case ATH79_SOC_AR7130
:
633 case ATH79_SOC_AR7141
:
634 case ATH79_SOC_AR7161
:
635 case ATH79_SOC_AR9130
:
636 case ATH79_SOC_AR9132
:
637 switch (pdata
->phy_if_mode
) {
638 case PHY_INTERFACE_MODE_MII
:
639 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
641 case PHY_INTERFACE_MODE_GMII
:
642 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
644 case PHY_INTERFACE_MODE_RGMII
:
645 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
647 case PHY_INTERFACE_MODE_RMII
:
648 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
653 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
656 case ATH79_SOC_AR7240
:
657 case ATH79_SOC_AR7241
:
658 case ATH79_SOC_AR9330
:
659 case ATH79_SOC_AR9331
:
660 case ATH79_SOC_QCA9533
:
661 case ATH79_SOC_TP9343
:
662 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
665 case ATH79_SOC_AR7242
:
668 case ATH79_SOC_AR9341
:
669 case ATH79_SOC_AR9342
:
670 case ATH79_SOC_AR9344
:
671 switch (pdata
->phy_if_mode
) {
672 case PHY_INTERFACE_MODE_MII
:
673 case PHY_INTERFACE_MODE_GMII
:
674 case PHY_INTERFACE_MODE_RGMII
:
675 case PHY_INTERFACE_MODE_RMII
:
682 case ATH79_SOC_QCA9556
:
683 case ATH79_SOC_QCA9558
:
684 case ATH79_SOC_QCA956X
:
685 switch (pdata
->phy_if_mode
) {
686 case PHY_INTERFACE_MODE_MII
:
687 case PHY_INTERFACE_MODE_RGMII
:
688 case PHY_INTERFACE_MODE_SGMII
:
701 case ATH79_SOC_AR7130
:
702 case ATH79_SOC_AR7141
:
703 case ATH79_SOC_AR7161
:
704 case ATH79_SOC_AR9130
:
705 case ATH79_SOC_AR9132
:
706 switch (pdata
->phy_if_mode
) {
707 case PHY_INTERFACE_MODE_RMII
:
708 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
710 case PHY_INTERFACE_MODE_RGMII
:
711 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
716 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
719 case ATH79_SOC_AR7240
:
720 case ATH79_SOC_AR7241
:
721 case ATH79_SOC_AR9330
:
722 case ATH79_SOC_AR9331
:
723 case ATH79_SOC_QCA956X
:
724 case ATH79_SOC_TP9343
:
725 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
728 case ATH79_SOC_AR7242
:
731 case ATH79_SOC_AR9341
:
732 case ATH79_SOC_AR9342
:
733 case ATH79_SOC_AR9344
:
734 case ATH79_SOC_QCA9533
:
735 switch (pdata
->phy_if_mode
) {
736 case PHY_INTERFACE_MODE_MII
:
737 case PHY_INTERFACE_MODE_GMII
:
744 case ATH79_SOC_QCA9556
:
745 case ATH79_SOC_QCA9558
:
746 switch (pdata
->phy_if_mode
) {
747 case PHY_INTERFACE_MODE_MII
:
748 case PHY_INTERFACE_MODE_RGMII
:
749 case PHY_INTERFACE_MODE_SGMII
:
765 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
770 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
772 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
773 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
775 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
777 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
778 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
783 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
788 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
790 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
792 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
793 AR934X_ETH_CFG_MII_GMAC0
|
794 AR934X_ETH_CFG_GMII_GMAC0
|
795 AR934X_ETH_CFG_SW_ONLY_MODE
|
796 AR934X_ETH_CFG_SW_PHY_SWAP
);
800 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
802 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
807 void __init
ath79_setup_ar934x_eth_rx_delay(unsigned int rxd
,
813 rxd
&= AR934X_ETH_CFG_RXD_DELAY_MASK
;
814 rxdv
&= AR934X_ETH_CFG_RDV_DELAY_MASK
;
816 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
818 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
820 t
&= ~(AR934X_ETH_CFG_RXD_DELAY_MASK
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
821 AR934X_ETH_CFG_RDV_DELAY_MASK
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
823 t
|= (rxd
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
824 rxdv
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
826 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
828 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
833 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
,
834 unsigned int rxd
, unsigned int rxdv
,
835 unsigned int txd
, unsigned int txe
)
840 m
= QCA955X_ETH_CFG_RGMII_EN
|
841 QCA955X_ETH_CFG_MII_GE0
|
842 QCA955X_ETH_CFG_GMII_GE0
|
843 QCA955X_ETH_CFG_MII_GE0_MASTER
|
844 QCA955X_ETH_CFG_MII_GE0_SLAVE
|
845 QCA955X_ETH_CFG_GE0_ERR_EN
|
846 QCA955X_ETH_CFG_GE0_SGMII
|
847 QCA955X_ETH_CFG_RMII_GE0
|
848 QCA955X_ETH_CFG_MII_CNTL_SPEED
|
849 QCA955X_ETH_CFG_RMII_GE0_MASTER
;
850 m
|= QCA955X_ETH_CFG_RXD_DELAY_MASK
<< QCA955X_ETH_CFG_RXD_DELAY_SHIFT
;
851 m
|= QCA955X_ETH_CFG_RDV_DELAY_MASK
<< QCA955X_ETH_CFG_RDV_DELAY_SHIFT
;
852 m
|= QCA955X_ETH_CFG_TXD_DELAY_MASK
<< QCA955X_ETH_CFG_TXD_DELAY_SHIFT
;
853 m
|= QCA955X_ETH_CFG_TXE_DELAY_MASK
<< QCA955X_ETH_CFG_TXE_DELAY_SHIFT
;
855 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
857 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
861 t
|= rxd
<< QCA955X_ETH_CFG_RXD_DELAY_SHIFT
;
862 t
|= rxdv
<< QCA955X_ETH_CFG_RDV_DELAY_SHIFT
;
863 t
|= txd
<< QCA955X_ETH_CFG_TXD_DELAY_SHIFT
;
864 t
|= txe
<< QCA955X_ETH_CFG_TXE_DELAY_SHIFT
;
866 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
871 static int ath79_eth_instance __initdata
;
872 void __init
ath79_register_eth(unsigned int id
)
874 struct platform_device
*pdev
;
875 struct ag71xx_platform_data
*pdata
;
879 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
883 ath79_init_eth_pll_data(id
);
886 pdev
= &ath79_eth0_device
;
888 pdev
= &ath79_eth1_device
;
890 pdata
= pdev
->dev
.platform_data
;
892 pdata
->max_frame_len
= 1540;
893 pdata
->desc_pktlen_mask
= 0xfff;
895 err
= ath79_setup_phy_if_mode(id
, pdata
);
898 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
903 case ATH79_SOC_AR7130
:
905 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
906 pdata
->set_speed
= ath79_set_speed_ge0
;
908 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
909 pdata
->set_speed
= ath79_set_speed_ge1
;
913 case ATH79_SOC_AR7141
:
914 case ATH79_SOC_AR7161
:
916 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
917 pdata
->set_speed
= ath79_set_speed_ge0
;
919 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
920 pdata
->set_speed
= ath79_set_speed_ge1
;
925 case ATH79_SOC_AR7242
:
927 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
928 AR71XX_RESET_GE0_PHY
;
929 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
930 pdata
->set_speed
= ar7242_set_speed_ge0
;
932 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
933 AR71XX_RESET_GE1_PHY
;
934 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
935 pdata
->set_speed
= ath79_set_speed_dummy
;
938 pdata
->is_ar724x
= 1;
940 if (!pdata
->fifo_cfg1
)
941 pdata
->fifo_cfg1
= 0x0010ffff;
942 if (!pdata
->fifo_cfg2
)
943 pdata
->fifo_cfg2
= 0x015500aa;
944 if (!pdata
->fifo_cfg3
)
945 pdata
->fifo_cfg3
= 0x01f00140;
948 case ATH79_SOC_AR7241
:
950 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
952 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
954 case ATH79_SOC_AR7240
:
956 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
957 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
958 pdata
->set_speed
= ath79_set_speed_dummy
;
960 pdata
->phy_mask
= BIT(4);
962 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
963 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
964 pdata
->set_speed
= ath79_set_speed_dummy
;
966 pdata
->speed
= SPEED_1000
;
967 pdata
->duplex
= DUPLEX_FULL
;
968 pdata
->switch_data
= &ath79_switch_data
;
970 ath79_switch_data
.phy_poll_mask
|= BIT(4);
973 pdata
->is_ar724x
= 1;
974 if (ath79_soc
== ATH79_SOC_AR7240
)
975 pdata
->is_ar7240
= 1;
977 if (!pdata
->fifo_cfg1
)
978 pdata
->fifo_cfg1
= 0x0010ffff;
979 if (!pdata
->fifo_cfg2
)
980 pdata
->fifo_cfg2
= 0x015500aa;
981 if (!pdata
->fifo_cfg3
)
982 pdata
->fifo_cfg3
= 0x01f00140;
985 case ATH79_SOC_AR9130
:
987 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
988 pdata
->set_speed
= ar91xx_set_speed_ge0
;
990 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
991 pdata
->set_speed
= ar91xx_set_speed_ge1
;
993 pdata
->is_ar91xx
= 1;
996 case ATH79_SOC_AR9132
:
998 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
999 pdata
->set_speed
= ar91xx_set_speed_ge0
;
1001 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
1002 pdata
->set_speed
= ar91xx_set_speed_ge1
;
1004 pdata
->is_ar91xx
= 1;
1005 pdata
->has_gbit
= 1;
1008 case ATH79_SOC_AR9330
:
1009 case ATH79_SOC_AR9331
:
1011 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1012 AR933X_RESET_GE0_MDIO
;
1013 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
1014 pdata
->set_speed
= ath79_set_speed_dummy
;
1016 pdata
->phy_mask
= BIT(4);
1018 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1019 AR933X_RESET_GE1_MDIO
;
1020 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
1021 pdata
->set_speed
= ath79_set_speed_dummy
;
1023 pdata
->speed
= SPEED_1000
;
1024 pdata
->has_gbit
= 1;
1025 pdata
->duplex
= DUPLEX_FULL
;
1026 pdata
->switch_data
= &ath79_switch_data
;
1028 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1031 pdata
->is_ar724x
= 1;
1033 if (!pdata
->fifo_cfg1
)
1034 pdata
->fifo_cfg1
= 0x0010ffff;
1035 if (!pdata
->fifo_cfg2
)
1036 pdata
->fifo_cfg2
= 0x015500aa;
1037 if (!pdata
->fifo_cfg3
)
1038 pdata
->fifo_cfg3
= 0x01f00140;
1041 case ATH79_SOC_AR9341
:
1042 case ATH79_SOC_AR9342
:
1043 case ATH79_SOC_AR9344
:
1044 case ATH79_SOC_QCA9533
:
1046 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
1047 AR934X_RESET_GE0_MDIO
;
1048 pdata
->set_speed
= ar934x_set_speed_ge0
;
1050 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
1051 AR934X_RESET_GE1_MDIO
;
1052 pdata
->set_speed
= ath79_set_speed_dummy
;
1054 pdata
->switch_data
= &ath79_switch_data
;
1056 /* reset the built-in switch */
1057 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1058 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1061 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1062 pdata
->has_gbit
= 1;
1063 pdata
->is_ar724x
= 1;
1065 pdata
->max_frame_len
= SZ_16K
- 1;
1066 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1068 if (!pdata
->fifo_cfg1
)
1069 pdata
->fifo_cfg1
= 0x0010ffff;
1070 if (!pdata
->fifo_cfg2
)
1071 pdata
->fifo_cfg2
= 0x015500aa;
1072 if (!pdata
->fifo_cfg3
)
1073 pdata
->fifo_cfg3
= 0x01f00140;
1076 case ATH79_SOC_TP9343
:
1078 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1079 AR933X_RESET_GE0_MDIO
;
1080 pdata
->set_speed
= ath79_set_speed_dummy
;
1082 if (!pdata
->phy_mask
)
1083 pdata
->phy_mask
= BIT(4);
1085 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1086 AR933X_RESET_GE1_MDIO
;
1087 pdata
->set_speed
= ath79_set_speed_dummy
;
1089 pdata
->speed
= SPEED_1000
;
1090 pdata
->duplex
= DUPLEX_FULL
;
1091 pdata
->switch_data
= &ath79_switch_data
;
1093 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1096 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1097 pdata
->has_gbit
= 1;
1098 pdata
->is_ar724x
= 1;
1100 if (!pdata
->fifo_cfg1
)
1101 pdata
->fifo_cfg1
= 0x0010ffff;
1102 if (!pdata
->fifo_cfg2
)
1103 pdata
->fifo_cfg2
= 0x015500aa;
1104 if (!pdata
->fifo_cfg3
)
1105 pdata
->fifo_cfg3
= 0x01f00140;
1108 case ATH79_SOC_QCA9556
:
1109 case ATH79_SOC_QCA9558
:
1111 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1112 QCA955X_RESET_GE0_MDIO
;
1113 pdata
->set_speed
= qca955x_set_speed_xmii
;
1115 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1116 QCA955X_RESET_GE1_MDIO
;
1117 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1120 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1121 pdata
->has_gbit
= 1;
1122 pdata
->is_ar724x
= 1;
1125 * Limit the maximum frame length to 4095 bytes.
1126 * Although the documentation says that the hardware
1127 * limit is 16383 bytes but that does not work in
1128 * practice. It seems that the hardware only updates
1129 * the lowest 12 bits of the packet length field
1130 * in the RX descriptor.
1132 pdata
->max_frame_len
= SZ_4K
- 1;
1133 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1135 if (!pdata
->fifo_cfg1
)
1136 pdata
->fifo_cfg1
= 0x0010ffff;
1137 if (!pdata
->fifo_cfg2
)
1138 pdata
->fifo_cfg2
= 0x015500aa;
1139 if (!pdata
->fifo_cfg3
)
1140 pdata
->fifo_cfg3
= 0x01f00140;
1143 case ATH79_SOC_QCA956X
:
1145 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1146 QCA955X_RESET_GE0_MDIO
;
1148 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_SGMII
)
1149 pdata
->set_speed
= qca956x_set_speed_sgmii
;
1151 pdata
->set_speed
= ath79_set_speed_ge0
;
1153 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1154 QCA955X_RESET_GE1_MDIO
;
1156 pdata
->set_speed
= ath79_set_speed_dummy
;
1158 pdata
->switch_data
= &ath79_switch_data
;
1160 pdata
->speed
= SPEED_1000
;
1161 pdata
->duplex
= DUPLEX_FULL
;
1163 /* reset the built-in switch */
1164 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1165 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1168 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1169 pdata
->has_gbit
= 1;
1170 pdata
->is_ar724x
= 1;
1172 if (!pdata
->fifo_cfg1
)
1173 pdata
->fifo_cfg1
= 0x0010ffff;
1174 if (!pdata
->fifo_cfg2
)
1175 pdata
->fifo_cfg2
= 0x015500aa;
1176 if (!pdata
->fifo_cfg3
)
1177 pdata
->fifo_cfg3
= 0x01f00140;
1184 switch (pdata
->phy_if_mode
) {
1185 case PHY_INTERFACE_MODE_GMII
:
1186 case PHY_INTERFACE_MODE_RGMII
:
1187 case PHY_INTERFACE_MODE_SGMII
:
1188 if (!pdata
->has_gbit
) {
1189 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1198 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1199 random_ether_addr(pdata
->mac_addr
);
1201 "ar71xx: using random MAC address for eth%d\n",
1202 ath79_eth_instance
);
1205 if (pdata
->mii_bus_dev
== NULL
) {
1206 switch (ath79_soc
) {
1207 case ATH79_SOC_AR9341
:
1208 case ATH79_SOC_AR9342
:
1209 case ATH79_SOC_AR9344
:
1211 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1213 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1216 case ATH79_SOC_AR7241
:
1217 case ATH79_SOC_AR9330
:
1218 case ATH79_SOC_AR9331
:
1219 case ATH79_SOC_QCA9533
:
1220 case ATH79_SOC_TP9343
:
1221 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1224 case ATH79_SOC_QCA9556
:
1225 case ATH79_SOC_QCA9558
:
1226 /* don't assign any MDIO device by default */
1229 case ATH79_SOC_QCA956X
:
1230 if (pdata
->phy_if_mode
!= PHY_INTERFACE_MODE_SGMII
)
1231 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1235 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1240 /* Reset the device */
1241 ath79_device_reset_set(pdata
->reset_bit
);
1244 ath79_device_reset_clear(pdata
->reset_bit
);
1247 platform_device_register(pdev
);
1248 ath79_eth_instance
++;
1251 void __init
ath79_set_mac_base(unsigned char *mac
)
1253 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1256 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1260 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1261 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1264 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1265 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1267 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1268 memset(mac
, 0, ETH_ALEN
);
1269 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1274 static void __init
ath79_set_mac_base_ascii(char *str
)
1278 ath79_parse_ascii_mac(str
, mac
);
1279 ath79_set_mac_base(mac
);
1282 static int __init
ath79_ethaddr_setup(char *str
)
1284 ath79_set_mac_base_ascii(str
);
1287 __setup("ethaddr=", ath79_ethaddr_setup
);
1289 static int __init
ath79_kmac_setup(char *str
)
1291 ath79_set_mac_base_ascii(str
);
1294 __setup("kmac=", ath79_kmac_setup
);
1296 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1304 if (!src
|| !is_valid_ether_addr(src
)) {
1305 memset(dst
, '\0', ETH_ALEN
);
1309 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1315 dst
[3] = (t
>> 16) & 0xff;
1316 dst
[4] = (t
>> 8) & 0xff;
1320 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1327 if (!src
|| !is_valid_ether_addr(src
)) {
1328 memset(dst
, '\0', ETH_ALEN
);
1332 for (i
= 0; i
< ETH_ALEN
; i
++)