2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
||
187 ath79_soc
== ATH79_SOC_QCA956X
)
193 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
198 case ATH79_SOC_AR7241
:
199 case ATH79_SOC_AR9330
:
200 case ATH79_SOC_AR9331
:
201 case ATH79_SOC_QCA9533
:
202 case ATH79_SOC_TP9343
:
203 mdio_dev
= &ath79_mdio1_device
;
204 mdio_data
= &ath79_mdio1_data
;
207 case ATH79_SOC_AR9341
:
208 case ATH79_SOC_AR9342
:
209 case ATH79_SOC_AR9344
:
210 case ATH79_SOC_QCA9556
:
211 case ATH79_SOC_QCA9558
:
212 case ATH79_SOC_QCA956X
:
214 mdio_dev
= &ath79_mdio0_device
;
215 mdio_data
= &ath79_mdio0_data
;
217 mdio_dev
= &ath79_mdio1_device
;
218 mdio_data
= &ath79_mdio1_data
;
222 case ATH79_SOC_AR7242
:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
224 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT
);
228 mdio_dev
= &ath79_mdio0_device
;
229 mdio_data
= &ath79_mdio0_data
;
233 mdio_data
->phy_mask
= phy_mask
;
236 case ATH79_SOC_AR7240
:
237 mdio_data
->is_ar7240
= 1;
239 case ATH79_SOC_AR7241
:
240 mdio_data
->builtin_switch
= 1;
243 case ATH79_SOC_AR9330
:
244 mdio_data
->is_ar9330
= 1;
246 case ATH79_SOC_AR9331
:
247 mdio_data
->builtin_switch
= 1;
250 case ATH79_SOC_AR9341
:
251 case ATH79_SOC_AR9342
:
252 case ATH79_SOC_AR9344
:
254 mdio_data
->builtin_switch
= 1;
255 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
256 mdio_data
->mdio_clock
= 6250000;
258 mdio_data
->is_ar934x
= 1;
261 case ATH79_SOC_QCA9533
:
262 case ATH79_SOC_TP9343
:
263 mdio_data
->builtin_switch
= 1;
266 case ATH79_SOC_QCA9556
:
267 case ATH79_SOC_QCA9558
:
268 mdio_data
->is_ar934x
= 1;
271 case ATH79_SOC_QCA956X
:
273 mdio_data
->builtin_switch
= 1;
274 mdio_data
->is_ar934x
= 1;
281 platform_device_register(mdio_dev
);
284 struct ath79_eth_pll_data ath79_eth0_pll_data
;
285 struct ath79_eth_pll_data ath79_eth1_pll_data
;
287 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
289 struct ath79_eth_pll_data
*pll_data
;
294 pll_data
= &ath79_eth0_pll_data
;
297 pll_data
= &ath79_eth1_pll_data
;
305 pll_val
= pll_data
->pll_10
;
308 pll_val
= pll_data
->pll_100
;
311 pll_val
= pll_data
->pll_1000
;
320 static void ath79_set_speed_ge0(int speed
)
322 u32 val
= ath79_get_eth_pll(0, speed
);
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
325 val
, AR71XX_ETH0_PLL_SHIFT
);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
329 static void ath79_set_speed_ge1(int speed
)
331 u32 val
= ath79_get_eth_pll(1, speed
);
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
334 val
, AR71XX_ETH1_PLL_SHIFT
);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
338 static void ar7242_set_speed_ge0(int speed
)
340 u32 val
= ath79_get_eth_pll(0, speed
);
343 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
344 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
348 static void ar91xx_set_speed_ge0(int speed
)
350 u32 val
= ath79_get_eth_pll(0, speed
);
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
353 val
, AR913X_ETH0_PLL_SHIFT
);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
357 static void ar91xx_set_speed_ge1(int speed
)
359 u32 val
= ath79_get_eth_pll(1, speed
);
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
362 val
, AR913X_ETH1_PLL_SHIFT
);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
366 static void ar934x_set_speed_ge0(int speed
)
369 u32 val
= ath79_get_eth_pll(0, speed
);
371 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
372 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
376 static void qca955x_set_speed_xmii(int speed
)
379 u32 val
= ath79_get_eth_pll(0, speed
);
381 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
382 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
386 static void qca955x_set_speed_sgmii(int speed
)
389 u32 val
= ath79_get_eth_pll(1, speed
);
391 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
392 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
396 static void qca956x_set_speed_sgmii(int speed
)
399 u32 val
= ath79_get_eth_pll(0, speed
);
401 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
402 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
406 static void ath79_set_speed_dummy(int speed
)
410 static void ath79_ddr_flush_ge0(void)
412 ath79_ddr_wb_flush(0);
415 static void ath79_ddr_flush_ge1(void)
417 ath79_ddr_wb_flush(1);
420 static struct resource ath79_eth0_resources
[] = {
423 .flags
= IORESOURCE_MEM
,
424 .start
= AR71XX_GE0_BASE
,
425 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
428 .flags
= IORESOURCE_IRQ
,
429 .start
= ATH79_CPU_IRQ(4),
430 .end
= ATH79_CPU_IRQ(4),
434 struct ag71xx_platform_data ath79_eth0_data
= {
435 .reset_bit
= AR71XX_RESET_GE0_MAC
,
438 struct platform_device ath79_eth0_device
= {
441 .resource
= ath79_eth0_resources
,
442 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
444 .platform_data
= &ath79_eth0_data
,
448 static struct resource ath79_eth1_resources
[] = {
451 .flags
= IORESOURCE_MEM
,
452 .start
= AR71XX_GE1_BASE
,
453 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
456 .flags
= IORESOURCE_IRQ
,
457 .start
= ATH79_CPU_IRQ(5),
458 .end
= ATH79_CPU_IRQ(5),
462 struct ag71xx_platform_data ath79_eth1_data
= {
463 .reset_bit
= AR71XX_RESET_GE1_MAC
,
466 struct platform_device ath79_eth1_device
= {
469 .resource
= ath79_eth1_resources
,
470 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
472 .platform_data
= &ath79_eth1_data
,
476 struct ag71xx_switch_platform_data ath79_switch_data
;
478 #define AR71XX_PLL_VAL_1000 0x00110000
479 #define AR71XX_PLL_VAL_100 0x00001099
480 #define AR71XX_PLL_VAL_10 0x00991099
482 #define AR724X_PLL_VAL_1000 0x00110000
483 #define AR724X_PLL_VAL_100 0x00001099
484 #define AR724X_PLL_VAL_10 0x00991099
486 #define AR7242_PLL_VAL_1000 0x16000000
487 #define AR7242_PLL_VAL_100 0x00000101
488 #define AR7242_PLL_VAL_10 0x00001616
490 #define AR913X_PLL_VAL_1000 0x1a000000
491 #define AR913X_PLL_VAL_100 0x13000a44
492 #define AR913X_PLL_VAL_10 0x00441099
494 #define AR933X_PLL_VAL_1000 0x00110000
495 #define AR933X_PLL_VAL_100 0x00001099
496 #define AR933X_PLL_VAL_10 0x00991099
498 #define AR934X_PLL_VAL_1000 0x16000000
499 #define AR934X_PLL_VAL_100 0x00000101
500 #define AR934X_PLL_VAL_10 0x00001616
502 #define QCA956X_PLL_VAL_1000 0x03000000
503 #define QCA956X_PLL_VAL_100 0x00000101
504 #define QCA956X_PLL_VAL_10 0x00001919
506 static void __init
ath79_init_eth_pll_data(unsigned int id
)
508 struct ath79_eth_pll_data
*pll_data
;
509 u32 pll_10
, pll_100
, pll_1000
;
513 pll_data
= &ath79_eth0_pll_data
;
516 pll_data
= &ath79_eth1_pll_data
;
523 case ATH79_SOC_AR7130
:
524 case ATH79_SOC_AR7141
:
525 case ATH79_SOC_AR7161
:
526 pll_10
= AR71XX_PLL_VAL_10
;
527 pll_100
= AR71XX_PLL_VAL_100
;
528 pll_1000
= AR71XX_PLL_VAL_1000
;
531 case ATH79_SOC_AR7240
:
532 case ATH79_SOC_AR7241
:
533 pll_10
= AR724X_PLL_VAL_10
;
534 pll_100
= AR724X_PLL_VAL_100
;
535 pll_1000
= AR724X_PLL_VAL_1000
;
538 case ATH79_SOC_AR7242
:
539 pll_10
= AR7242_PLL_VAL_10
;
540 pll_100
= AR7242_PLL_VAL_100
;
541 pll_1000
= AR7242_PLL_VAL_1000
;
544 case ATH79_SOC_AR9130
:
545 case ATH79_SOC_AR9132
:
546 pll_10
= AR913X_PLL_VAL_10
;
547 pll_100
= AR913X_PLL_VAL_100
;
548 pll_1000
= AR913X_PLL_VAL_1000
;
551 case ATH79_SOC_AR9330
:
552 case ATH79_SOC_AR9331
:
553 pll_10
= AR933X_PLL_VAL_10
;
554 pll_100
= AR933X_PLL_VAL_100
;
555 pll_1000
= AR933X_PLL_VAL_1000
;
558 case ATH79_SOC_AR9341
:
559 case ATH79_SOC_AR9342
:
560 case ATH79_SOC_AR9344
:
561 case ATH79_SOC_QCA9533
:
562 case ATH79_SOC_QCA9556
:
563 case ATH79_SOC_QCA9558
:
564 case ATH79_SOC_TP9343
:
565 pll_10
= AR934X_PLL_VAL_10
;
566 pll_100
= AR934X_PLL_VAL_100
;
567 pll_1000
= AR934X_PLL_VAL_1000
;
570 case ATH79_SOC_QCA956X
:
571 pll_10
= QCA956X_PLL_VAL_10
;
572 pll_100
= QCA956X_PLL_VAL_100
;
573 pll_1000
= QCA956X_PLL_VAL_1000
;
580 if (!pll_data
->pll_10
)
581 pll_data
->pll_10
= pll_10
;
583 if (!pll_data
->pll_100
)
584 pll_data
->pll_100
= pll_100
;
586 if (!pll_data
->pll_1000
)
587 pll_data
->pll_1000
= pll_1000
;
590 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
591 struct ag71xx_platform_data
*pdata
)
598 case ATH79_SOC_AR7130
:
599 case ATH79_SOC_AR7141
:
600 case ATH79_SOC_AR7161
:
601 case ATH79_SOC_AR9130
:
602 case ATH79_SOC_AR9132
:
603 switch (pdata
->phy_if_mode
) {
604 case PHY_INTERFACE_MODE_MII
:
605 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
607 case PHY_INTERFACE_MODE_GMII
:
608 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
610 case PHY_INTERFACE_MODE_RGMII
:
611 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
613 case PHY_INTERFACE_MODE_RMII
:
614 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
619 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
622 case ATH79_SOC_AR7240
:
623 case ATH79_SOC_AR7241
:
624 case ATH79_SOC_AR9330
:
625 case ATH79_SOC_AR9331
:
626 case ATH79_SOC_QCA9533
:
627 case ATH79_SOC_TP9343
:
628 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
631 case ATH79_SOC_AR7242
:
634 case ATH79_SOC_AR9341
:
635 case ATH79_SOC_AR9342
:
636 case ATH79_SOC_AR9344
:
637 switch (pdata
->phy_if_mode
) {
638 case PHY_INTERFACE_MODE_MII
:
639 case PHY_INTERFACE_MODE_GMII
:
640 case PHY_INTERFACE_MODE_RGMII
:
641 case PHY_INTERFACE_MODE_RMII
:
648 case ATH79_SOC_QCA9556
:
649 case ATH79_SOC_QCA9558
:
650 case ATH79_SOC_QCA956X
:
651 switch (pdata
->phy_if_mode
) {
652 case PHY_INTERFACE_MODE_MII
:
653 case PHY_INTERFACE_MODE_RGMII
:
654 case PHY_INTERFACE_MODE_SGMII
:
667 case ATH79_SOC_AR7130
:
668 case ATH79_SOC_AR7141
:
669 case ATH79_SOC_AR7161
:
670 case ATH79_SOC_AR9130
:
671 case ATH79_SOC_AR9132
:
672 switch (pdata
->phy_if_mode
) {
673 case PHY_INTERFACE_MODE_RMII
:
674 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
676 case PHY_INTERFACE_MODE_RGMII
:
677 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
682 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
685 case ATH79_SOC_AR7240
:
686 case ATH79_SOC_AR7241
:
687 case ATH79_SOC_AR9330
:
688 case ATH79_SOC_AR9331
:
689 case ATH79_SOC_TP9343
:
690 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
693 case ATH79_SOC_AR7242
:
696 case ATH79_SOC_AR9341
:
697 case ATH79_SOC_AR9342
:
698 case ATH79_SOC_AR9344
:
699 case ATH79_SOC_QCA9533
:
700 case ATH79_SOC_QCA956X
:
701 switch (pdata
->phy_if_mode
) {
702 case PHY_INTERFACE_MODE_MII
:
703 case PHY_INTERFACE_MODE_GMII
:
710 case ATH79_SOC_QCA9556
:
711 case ATH79_SOC_QCA9558
:
712 switch (pdata
->phy_if_mode
) {
713 case PHY_INTERFACE_MODE_MII
:
714 case PHY_INTERFACE_MODE_RGMII
:
715 case PHY_INTERFACE_MODE_SGMII
:
731 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
736 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
738 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
739 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
741 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
743 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
744 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
749 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
754 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
756 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
758 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
759 AR934X_ETH_CFG_MII_GMAC0
|
760 AR934X_ETH_CFG_GMII_GMAC0
|
761 AR934X_ETH_CFG_SW_ONLY_MODE
|
762 AR934X_ETH_CFG_SW_PHY_SWAP
);
766 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
768 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
773 void __init
ath79_setup_ar934x_eth_rx_delay(unsigned int rxd
,
779 rxd
&= AR934X_ETH_CFG_RXD_DELAY_MASK
;
780 rxdv
&= AR934X_ETH_CFG_RDV_DELAY_MASK
;
782 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
784 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
786 t
&= ~(AR934X_ETH_CFG_RXD_DELAY_MASK
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
787 AR934X_ETH_CFG_RDV_DELAY_MASK
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
789 t
|= (rxd
<< AR934X_ETH_CFG_RXD_DELAY_SHIFT
|
790 rxdv
<< AR934X_ETH_CFG_RDV_DELAY_SHIFT
);
792 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
794 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
799 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
)
804 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
806 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
808 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
812 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
817 void __init
ath79_setup_qca956x_eth_cfg(u32 mask
)
822 base
= ioremap(QCA956X_GMAC_BASE
, QCA956X_GMAC_SIZE
);
824 t
= __raw_readl(base
+ QCA956X_GMAC_REG_ETH_CFG
);
826 t
&= ~(QCA956X_ETH_CFG_SW_ONLY_MODE
|
827 QCA956X_ETH_CFG_SW_PHY_SWAP
);
831 __raw_writel(t
, base
+ QCA956X_GMAC_REG_ETH_CFG
);
833 __raw_readl(base
+ QCA956X_GMAC_REG_ETH_CFG
);
838 static int ath79_eth_instance __initdata
;
839 void __init
ath79_register_eth(unsigned int id
)
841 struct platform_device
*pdev
;
842 struct ag71xx_platform_data
*pdata
;
846 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
850 ath79_init_eth_pll_data(id
);
853 pdev
= &ath79_eth0_device
;
855 pdev
= &ath79_eth1_device
;
857 pdata
= pdev
->dev
.platform_data
;
859 pdata
->max_frame_len
= 1540;
860 pdata
->desc_pktlen_mask
= 0xfff;
862 err
= ath79_setup_phy_if_mode(id
, pdata
);
865 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
870 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
872 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
875 case ATH79_SOC_AR7130
:
877 pdata
->set_speed
= ath79_set_speed_ge0
;
879 pdata
->set_speed
= ath79_set_speed_ge1
;
882 case ATH79_SOC_AR7141
:
883 case ATH79_SOC_AR7161
:
885 pdata
->set_speed
= ath79_set_speed_ge0
;
887 pdata
->set_speed
= ath79_set_speed_ge1
;
891 case ATH79_SOC_AR7242
:
893 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
894 AR71XX_RESET_GE0_PHY
;
895 pdata
->set_speed
= ar7242_set_speed_ge0
;
897 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
898 AR71XX_RESET_GE1_PHY
;
899 pdata
->set_speed
= ath79_set_speed_dummy
;
902 pdata
->is_ar724x
= 1;
904 if (!pdata
->fifo_cfg1
)
905 pdata
->fifo_cfg1
= 0x0010ffff;
906 if (!pdata
->fifo_cfg2
)
907 pdata
->fifo_cfg2
= 0x015500aa;
908 if (!pdata
->fifo_cfg3
)
909 pdata
->fifo_cfg3
= 0x01f00140;
912 case ATH79_SOC_AR7241
:
914 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
916 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
918 case ATH79_SOC_AR7240
:
920 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
921 pdata
->set_speed
= ath79_set_speed_dummy
;
923 pdata
->phy_mask
= BIT(4);
925 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
926 pdata
->set_speed
= ath79_set_speed_dummy
;
928 pdata
->speed
= SPEED_1000
;
929 pdata
->duplex
= DUPLEX_FULL
;
930 pdata
->switch_data
= &ath79_switch_data
;
931 pdata
->use_flow_control
= 1;
933 ath79_switch_data
.phy_poll_mask
|= BIT(4);
936 pdata
->is_ar724x
= 1;
937 if (ath79_soc
== ATH79_SOC_AR7240
)
938 pdata
->is_ar7240
= 1;
940 if (!pdata
->fifo_cfg1
)
941 pdata
->fifo_cfg1
= 0x0010ffff;
942 if (!pdata
->fifo_cfg2
)
943 pdata
->fifo_cfg2
= 0x015500aa;
944 if (!pdata
->fifo_cfg3
)
945 pdata
->fifo_cfg3
= 0x01f00140;
948 case ATH79_SOC_AR9132
:
951 case ATH79_SOC_AR9130
:
953 pdata
->set_speed
= ar91xx_set_speed_ge0
;
955 pdata
->set_speed
= ar91xx_set_speed_ge1
;
956 pdata
->is_ar91xx
= 1;
959 case ATH79_SOC_AR9330
:
960 case ATH79_SOC_AR9331
:
962 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
963 AR933X_RESET_GE0_MDIO
;
964 pdata
->set_speed
= ath79_set_speed_dummy
;
966 pdata
->phy_mask
= BIT(4);
968 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
969 AR933X_RESET_GE1_MDIO
;
970 pdata
->set_speed
= ath79_set_speed_dummy
;
972 pdata
->speed
= SPEED_1000
;
974 pdata
->duplex
= DUPLEX_FULL
;
975 pdata
->switch_data
= &ath79_switch_data
;
976 pdata
->use_flow_control
= 1;
978 ath79_switch_data
.phy_poll_mask
|= BIT(4);
981 pdata
->is_ar724x
= 1;
983 if (!pdata
->fifo_cfg1
)
984 pdata
->fifo_cfg1
= 0x0010ffff;
985 if (!pdata
->fifo_cfg2
)
986 pdata
->fifo_cfg2
= 0x015500aa;
987 if (!pdata
->fifo_cfg3
)
988 pdata
->fifo_cfg3
= 0x01f00140;
991 case ATH79_SOC_AR9341
:
992 case ATH79_SOC_AR9342
:
993 case ATH79_SOC_AR9344
:
994 case ATH79_SOC_QCA9533
:
996 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
997 AR934X_RESET_GE0_MDIO
;
998 pdata
->set_speed
= ar934x_set_speed_ge0
;
1000 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
1001 AR934X_RESET_GE1_MDIO
;
1002 pdata
->set_speed
= ath79_set_speed_dummy
;
1004 pdata
->switch_data
= &ath79_switch_data
;
1006 /* reset the built-in switch */
1007 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1008 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1011 pdata
->has_gbit
= 1;
1012 pdata
->is_ar724x
= 1;
1014 pdata
->max_frame_len
= SZ_16K
- 1;
1015 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1017 if (!pdata
->fifo_cfg1
)
1018 pdata
->fifo_cfg1
= 0x0010ffff;
1019 if (!pdata
->fifo_cfg2
)
1020 pdata
->fifo_cfg2
= 0x015500aa;
1021 if (!pdata
->fifo_cfg3
)
1022 pdata
->fifo_cfg3
= 0x01f00140;
1025 case ATH79_SOC_TP9343
:
1027 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
1028 AR933X_RESET_GE0_MDIO
;
1029 pdata
->set_speed
= ath79_set_speed_dummy
;
1031 if (!pdata
->phy_mask
)
1032 pdata
->phy_mask
= BIT(4);
1034 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1035 AR933X_RESET_GE1_MDIO
;
1036 pdata
->set_speed
= ath79_set_speed_dummy
;
1038 pdata
->speed
= SPEED_1000
;
1039 pdata
->duplex
= DUPLEX_FULL
;
1040 pdata
->switch_data
= &ath79_switch_data
;
1041 pdata
->use_flow_control
= 1;
1043 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1046 pdata
->has_gbit
= 1;
1047 pdata
->is_ar724x
= 1;
1049 if (!pdata
->fifo_cfg1
)
1050 pdata
->fifo_cfg1
= 0x0010ffff;
1051 if (!pdata
->fifo_cfg2
)
1052 pdata
->fifo_cfg2
= 0x015500aa;
1053 if (!pdata
->fifo_cfg3
)
1054 pdata
->fifo_cfg3
= 0x01f00140;
1057 case ATH79_SOC_QCA9556
:
1058 case ATH79_SOC_QCA9558
:
1060 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1061 QCA955X_RESET_GE0_MDIO
;
1062 pdata
->set_speed
= qca955x_set_speed_xmii
;
1064 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1065 QCA955X_RESET_GE1_MDIO
;
1066 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1069 pdata
->has_gbit
= 1;
1070 pdata
->is_ar724x
= 1;
1073 * Limit the maximum frame length to 4095 bytes.
1074 * Although the documentation says that the hardware
1075 * limit is 16383 bytes but that does not work in
1076 * practice. It seems that the hardware only updates
1077 * the lowest 12 bits of the packet length field
1078 * in the RX descriptor.
1080 pdata
->max_frame_len
= SZ_4K
- 1;
1081 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1083 if (!pdata
->fifo_cfg1
)
1084 pdata
->fifo_cfg1
= 0x0010ffff;
1085 if (!pdata
->fifo_cfg2
)
1086 pdata
->fifo_cfg2
= 0x015500aa;
1087 if (!pdata
->fifo_cfg3
)
1088 pdata
->fifo_cfg3
= 0x01f00140;
1091 case ATH79_SOC_QCA956X
:
1093 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1094 QCA955X_RESET_GE0_MDIO
;
1096 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_SGMII
)
1097 pdata
->set_speed
= qca956x_set_speed_sgmii
;
1099 pdata
->set_speed
= ar934x_set_speed_ge0
;
1101 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1102 QCA955X_RESET_GE1_MDIO
;
1104 pdata
->set_speed
= ath79_set_speed_dummy
;
1106 pdata
->switch_data
= &ath79_switch_data
;
1108 pdata
->speed
= SPEED_1000
;
1109 pdata
->duplex
= DUPLEX_FULL
;
1110 pdata
->use_flow_control
= 1;
1112 /* reset the built-in switch */
1113 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
1114 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
1117 pdata
->has_gbit
= 1;
1118 pdata
->is_ar724x
= 1;
1120 if (!pdata
->fifo_cfg1
)
1121 pdata
->fifo_cfg1
= 0x0010ffff;
1122 if (!pdata
->fifo_cfg2
)
1123 pdata
->fifo_cfg2
= 0x015500aa;
1124 if (!pdata
->fifo_cfg3
)
1125 pdata
->fifo_cfg3
= 0x01f00140;
1132 switch (pdata
->phy_if_mode
) {
1133 case PHY_INTERFACE_MODE_GMII
:
1134 case PHY_INTERFACE_MODE_RGMII
:
1135 case PHY_INTERFACE_MODE_SGMII
:
1136 if (!pdata
->has_gbit
) {
1137 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1146 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1147 random_ether_addr(pdata
->mac_addr
);
1149 "ar71xx: using random MAC address for eth%d\n",
1150 ath79_eth_instance
);
1153 if (pdata
->mii_bus_dev
== NULL
) {
1154 switch (ath79_soc
) {
1155 case ATH79_SOC_AR9341
:
1156 case ATH79_SOC_AR9342
:
1157 case ATH79_SOC_AR9344
:
1159 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1161 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1164 case ATH79_SOC_AR7241
:
1165 case ATH79_SOC_AR9330
:
1166 case ATH79_SOC_AR9331
:
1167 case ATH79_SOC_QCA9533
:
1168 case ATH79_SOC_TP9343
:
1169 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1172 case ATH79_SOC_QCA9556
:
1173 case ATH79_SOC_QCA9558
:
1174 /* don't assign any MDIO device by default */
1177 case ATH79_SOC_QCA956X
:
1178 if (pdata
->phy_if_mode
!= PHY_INTERFACE_MODE_SGMII
)
1179 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1183 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1188 /* Reset the device */
1189 ath79_device_reset_set(pdata
->reset_bit
);
1192 ath79_device_reset_clear(pdata
->reset_bit
);
1195 platform_device_register(pdev
);
1196 ath79_eth_instance
++;
1199 void __init
ath79_set_mac_base(unsigned char *mac
)
1201 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1204 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1208 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1209 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1212 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1213 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1215 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1216 memset(mac
, 0, ETH_ALEN
);
1217 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1222 static void __init
ath79_set_mac_base_ascii(char *str
)
1226 ath79_parse_ascii_mac(str
, mac
);
1227 ath79_set_mac_base(mac
);
1230 static int __init
ath79_ethaddr_setup(char *str
)
1232 ath79_set_mac_base_ascii(str
);
1235 __setup("ethaddr=", ath79_ethaddr_setup
);
1237 static int __init
ath79_kmac_setup(char *str
)
1239 ath79_set_mac_base_ascii(str
);
1242 __setup("kmac=", ath79_kmac_setup
);
1244 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1252 if (!src
|| !is_valid_ether_addr(src
)) {
1253 memset(dst
, '\0', ETH_ALEN
);
1257 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1263 dst
[3] = (t
>> 16) & 0xff;
1264 dst
[4] = (t
>> 8) & 0xff;
1268 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1275 if (!src
|| !is_valid_ether_addr(src
)) {
1276 memset(dst
, '\0', ETH_ALEN
);
1280 for (i
= 0; i
< ETH_ALEN
; i
++)