ar71xx: configure OBS4 line on TL-WR841N-v8/MR3420v2
[openwrt/staging/chunkeey.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-dir-505-a1.c
1 /*
2 * DLink DIR-505 A1 board support
3 *
4 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/gpio.h>
12
13 #include <asm/mach-ath79/ath79.h>
14 #include <asm/mach-ath79/ar71xx_regs.h>
15
16 #include "common.h"
17 #include "dev-eth.h"
18 #include "dev-gpio-buttons.h"
19 #include "dev-leds-gpio.h"
20 #include "dev-m25p80.h"
21 #include "dev-wmac.h"
22 #include "dev-usb.h"
23 #include "machtypes.h"
24
25 #define DIR_505A1_GPIO_BTN_WPS 11 /* verify */
26 #define DIR_505A1_GPIO_BTN_RESET 12 /* verify */
27
28 #define DIR_505A1_GPIO_LED_RED 26 /* unused, fyi */
29 #define DIR_505A1_GPIO_LED_GREEN 27
30
31 #define DIR_505A1_GPIO_WAN_LED_ENABLE 1
32
33 #define DIR_505A1_KEYS_POLL_INTERVAL 20 /* msecs */
34 #define DIR_505A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_505A1_KEYS_POLL_INTERVAL)
35
36 #define DIR_505A1_ART_ADDRESS 0x1f010000
37 #define DIR_505A1_CALDATA_OFFSET 0x1000
38 #define DIR_505A1_LAN_MAC_ADDRESS 0x1f020004
39 #define DIR_505A1_WAN_MAC_ADDRESS 0x1f020016
40
41 static struct gpio_led dir_505_a1_leds_gpio[] __initdata = {
42 {
43 .name = "d-link:green:power",
44 .gpio = DIR_505A1_GPIO_LED_GREEN,
45 .active_low = 1,
46 }, {
47 .name = "d-link:red:status",
48 .gpio = DIR_505A1_GPIO_LED_RED,
49 .active_low = 1,
50 },
51 };
52
53 static struct gpio_keys_button dir_505_a1_gpio_keys[] __initdata = {
54 {
55 .desc = "Reset button",
56 .type = EV_KEY,
57 .code = KEY_RESTART,
58 .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL,
59 .gpio = DIR_505A1_GPIO_BTN_RESET,
60 .active_low = 1,
61 }, {
62 .desc = "WPS button",
63 .type = EV_KEY,
64 .code = KEY_WPS_BUTTON,
65 .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL,
66 .gpio = DIR_505A1_GPIO_BTN_WPS,
67 .active_low = 1,
68 }
69 };
70
71 static void __init dir_505_a1_read_ascii_mac(u8 *dest, unsigned int src_addr)
72 {
73 int ret;
74 u8 *src = (u8 *)KSEG1ADDR(src_addr);
75
76 ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
77 &dest[0], &dest[1], &dest[2],
78 &dest[3], &dest[4], &dest[5]);
79
80 if (ret != ETH_ALEN)
81 memset(dest, 0, ETH_ALEN);
82 }
83
84 static void __init dir_505_a1_setup(void)
85 {
86 u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS);
87 u8 lan_mac[ETH_ALEN];
88 u8 wan_mac[ETH_ALEN];
89
90 ath79_setup_ar933x_phy4_switch(false, false);
91
92 ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
93 AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
94 AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
95 AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
96 AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
97
98 gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE,
99 GPIOF_OUT_INIT_LOW, "WAN LED enable");
100
101 ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio),
102 dir_505_a1_leds_gpio);
103
104 ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL,
105 ARRAY_SIZE(dir_505_a1_gpio_keys),
106 dir_505_a1_gpio_keys);
107
108 ath79_register_m25p80(NULL);
109
110 ath79_register_usb();
111
112 dir_505_a1_read_ascii_mac(lan_mac, DIR_505A1_LAN_MAC_ADDRESS);
113 dir_505_a1_read_ascii_mac(wan_mac, DIR_505A1_WAN_MAC_ADDRESS);
114
115 ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
116 ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
117
118 ath79_register_mdio(0, 0x0);
119 ath79_register_eth(1);
120 ath79_register_eth(0);
121
122 ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac);
123 }
124
125 MIPS_MACHINE(ATH79_MACH_DIR_505_A1, "DIR-505-A1",
126 "D-Link DIR-505 rev. A1", dir_505_a1_setup);