2 * OpenMesh OM5P-ACv2 support
4 * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
5 * Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>
6 * Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
13 #include <linux/gpio.h>
14 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
15 #include <linux/mdio-gpio.h>
17 #include <linux/platform_data/mdio-gpio.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/platform_device.h>
22 #include <linux/i2c.h>
23 #include <linux/i2c-algo-bit.h>
24 #include <linux/i2c-gpio.h>
25 #include <linux/platform_data/phy-at803x.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
28 #include <asm/mach-ath79/ath79.h>
31 #include "dev-ap9x-pci.h"
33 #include "dev-gpio-buttons.h"
34 #include "dev-leds-gpio.h"
35 #include "dev-m25p80.h"
37 #include "machtypes.h"
40 #define OM5PACV2_GPIO_LED_POWER 14
41 #define OM5PACV2_GPIO_LED_GREEN 13
42 #define OM5PACV2_GPIO_LED_RED 23
43 #define OM5PACV2_GPIO_LED_YELLOW 15
44 #define OM5PACV2_GPIO_BTN_RESET 1
45 #define OM5PACV2_GPIO_I2C_SCL 18
46 #define OM5PACV2_GPIO_I2C_SDA 19
47 #define OM5PACV2_GPIO_PA_DCDC 2
48 #define OM5PACV2_GPIO_PA_HIGH 16
50 #define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */
51 #define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL)
53 #define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000
55 static struct gpio_led om5pacv2_leds_gpio
[] __initdata
= {
57 .name
= "om5pac:blue:power",
58 .gpio
= OM5PACV2_GPIO_LED_POWER
,
61 .name
= "om5pac:red:wifi",
62 .gpio
= OM5PACV2_GPIO_LED_RED
,
65 .name
= "om5pac:yellow:wifi",
66 .gpio
= OM5PACV2_GPIO_LED_YELLOW
,
69 .name
= "om5pac:green:wifi",
70 .gpio
= OM5PACV2_GPIO_LED_GREEN
,
75 static struct gpio_keys_button om5pacv2_gpio_keys
[] __initdata
= {
80 .debounce_interval
= OM5PACV2_KEYS_DEBOUNCE_INTERVAL
,
81 .gpio
= OM5PACV2_GPIO_BTN_RESET
,
86 static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata
= {
87 .sda_pin
= OM5PACV2_GPIO_I2C_SDA
,
88 .scl_pin
= OM5PACV2_GPIO_I2C_SCL
,
90 .sda_is_open_drain
= 1,
91 .scl_is_open_drain
= 1,
94 static struct platform_device om5pacv2_i2c_device
= {
98 .platform_data
= &om5pacv2_i2c_device_platdata
,
102 static struct i2c_board_info om5pacv2_i2c_devs
[] __initdata
= {
104 I2C_BOARD_INFO("tmp423", 0x4e),
108 static struct flash_platform_data om5pacv2_flash_data
= {
109 .type
= "mx25l12805d",
112 static struct at803x_platform_data om5pacv2_an_at803x_data
= {
113 .disable_smarteee
= 1,
114 .enable_rgmii_rx_delay
= 1,
115 .enable_rgmii_tx_delay
= 1,
118 static struct at803x_platform_data om5pacv2_an_at8031_data
= {
119 .disable_smarteee
= 1,
120 .enable_rgmii_rx_delay
= 1,
121 .enable_rgmii_tx_delay
= 1,
124 static struct mdio_board_info om5pacv2_an_mdio0_info
[] = {
126 .bus_id
= "ag71xx-mdio.0",
128 .platform_data
= &om5pacv2_an_at803x_data
,
131 .bus_id
= "ag71xx-mdio.1",
133 .platform_data
= &om5pacv2_an_at8031_data
,
137 static void __init
om5p_acv2_setup_qca955x_eth_cfg(u32 mask
,
146 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
149 t
|= rxd
<< QCA955X_ETH_CFG_RXD_DELAY_SHIFT
;
150 t
|= rxdv
<< QCA955X_ETH_CFG_RDV_DELAY_SHIFT
;
151 t
|= txd
<< QCA955X_ETH_CFG_TXD_DELAY_SHIFT
;
152 t
|= txe
<< QCA955X_ETH_CFG_TXE_DELAY_SHIFT
;
154 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
159 static void __init
om5p_acv2_setup(void)
161 u8
*art
= (u8
*)KSEG1ADDR(0x1fff0000);
164 /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
165 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE
);
166 ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC
, QCA955X_GPIO_OUT_GPIO
);
167 ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH
, QCA955X_GPIO_OUT_GPIO
);
168 gpio_request_one(OM5PACV2_GPIO_PA_DCDC
, GPIOF_OUT_INIT_HIGH
,
170 gpio_request_one(OM5PACV2_GPIO_PA_HIGH
, GPIOF_OUT_INIT_HIGH
, "PA HIGH");
172 /* temperature sensor */
173 platform_device_register(&om5pacv2_i2c_device
);
174 i2c_register_board_info(0, om5pacv2_i2c_devs
,
175 ARRAY_SIZE(om5pacv2_i2c_devs
));
177 ath79_register_m25p80(&om5pacv2_flash_data
);
178 ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio
),
180 ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL
,
181 ARRAY_SIZE(om5pacv2_gpio_keys
),
184 ath79_init_mac(mac
, art
, 0x02);
185 ath79_register_wmac(art
+ OM5PACV2_WMAC_CALDATA_OFFSET
, mac
);
187 om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN
, 2, 2, 0, 0);
188 ath79_register_mdio(0, 0x0);
189 ath79_register_mdio(1, 0x0);
191 mdiobus_register_board_info(om5pacv2_an_mdio0_info
,
192 ARRAY_SIZE(om5pacv2_an_mdio0_info
));
194 ath79_init_mac(ath79_eth0_data
.mac_addr
, art
, 0x00);
195 ath79_init_mac(ath79_eth1_data
.mac_addr
, art
, 0x01);
197 /* GMAC0 is connected to the PHY4 */
198 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
199 ath79_eth0_data
.mii_bus_dev
= &ath79_mdio0_device
.dev
;
200 ath79_eth0_data
.phy_mask
= BIT(4);
201 ath79_eth0_pll_data
.pll_1000
= 0x82000101;
202 ath79_eth0_pll_data
.pll_100
= 0x80000101;
203 ath79_eth0_pll_data
.pll_10
= 0x80001313;
204 ath79_register_eth(0);
206 /* GMAC1 is connected to MDIO1 in SGMII mode */
207 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_SGMII
;
208 ath79_eth1_data
.mii_bus_dev
= &ath79_mdio1_device
.dev
;
209 ath79_eth1_data
.phy_mask
= BIT(1);
210 ath79_eth1_pll_data
.pll_1000
= 0x03000101;
211 ath79_eth1_pll_data
.pll_100
= 0x80000101;
212 ath79_eth1_pll_data
.pll_10
= 0x80001313;
213 ath79_eth1_data
.speed
= SPEED_1000
;
214 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
215 ath79_register_eth(1);
217 ath79_register_pci();
220 MIPS_MACHINE(ATH79_MACH_OM5P_ACv2
, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup
);