2 * MikroTik SPI-NOR RouterBOARDs support
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 750UP r2
8 * - MikroTik RouterBOARD 750 r2
10 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published
14 * by the Free Software Foundation.
17 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/routerboot.h>
20 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/74x164.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/partitions.h>
29 #include <asm/mach-ath79/ar71xx_regs.h>
30 #include <asm/mach-ath79/ath79.h>
35 #include "dev-gpio-buttons.h"
36 #include "dev-leds-gpio.h"
37 #include "dev-m25p80.h"
40 #include "machtypes.h"
41 #include "routerboot.h"
43 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
44 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
46 #define RBSPI_HAS_USB BIT(0)
47 #define RBSPI_HAS_WLAN BIT(1)
48 #define RBSPI_HAS_WAN4 BIT(2) /* has WAN port on PHY4 */
49 #define RBSPI_HAS_SSR BIT(3) /* has an SSR on SPI bus 0 */
50 #define RBSPI_HAS_POE BIT(4)
52 #define RB_ROUTERBOOT_OFFSET 0x0000
53 #define RB_BIOS_SIZE 0x1000
54 #define RB_SOFT_CFG_SIZE 0x1000
55 #define RB_KERNEL_SIZE (2 * 1024 * 1024) /* 2MB kernel */
57 /* Flash partitions indexes */
69 static struct mtd_partition rbspi_spi_partitions
[RBSPI_PARTS
];
72 * Setup the SPI flash partition table based on initial parsing.
73 * The kernel can be at any aligned position and have any size.
74 * The size of the kernel partition is the desired RB_KERNEL_SIZE
75 * minus the size of the preceding partitions (128KB).
77 static void __init
rbspi_init_partitions(const struct rb_info
*info
)
79 struct mtd_partition
*parts
= rbspi_spi_partitions
;
80 memset(parts
, 0x0, sizeof(*parts
));
82 parts
[RBSPI_PART_RBOOT
].name
= "routerboot";
83 parts
[RBSPI_PART_RBOOT
].offset
= RB_ROUTERBOOT_OFFSET
;
84 parts
[RBSPI_PART_RBOOT
].size
= info
->hard_cfg_offs
;
85 parts
[RBSPI_PART_RBOOT
].mask_flags
= MTD_WRITEABLE
;
87 parts
[RBSPI_PART_HCONF
].name
= "hard_config";
88 parts
[RBSPI_PART_HCONF
].offset
= info
->hard_cfg_offs
;
89 parts
[RBSPI_PART_HCONF
].size
= info
->hard_cfg_size
;
90 parts
[RBSPI_PART_HCONF
].mask_flags
= MTD_WRITEABLE
;
92 parts
[RBSPI_PART_BIOS
].name
= "bios";
93 parts
[RBSPI_PART_BIOS
].offset
= info
->hard_cfg_offs
94 + info
->hard_cfg_size
;
95 parts
[RBSPI_PART_BIOS
].size
= RB_BIOS_SIZE
;
96 parts
[RBSPI_PART_BIOS
].mask_flags
= MTD_WRITEABLE
;
98 parts
[RBSPI_PART_RBOOT2
].name
= "routerboot2";
99 parts
[RBSPI_PART_RBOOT2
].offset
= parts
[RBSPI_PART_BIOS
].offset
101 parts
[RBSPI_PART_RBOOT2
].size
= info
->soft_cfg_offs
102 - parts
[RBSPI_PART_RBOOT2
].offset
;
103 parts
[RBSPI_PART_RBOOT2
].mask_flags
= MTD_WRITEABLE
;
105 parts
[RBSPI_PART_SCONF
].name
= "soft_config";
106 parts
[RBSPI_PART_SCONF
].offset
= info
->soft_cfg_offs
;
107 parts
[RBSPI_PART_SCONF
].size
= RB_SOFT_CFG_SIZE
;
109 parts
[RBSPI_PART_KERN
].name
= "kernel";
110 parts
[RBSPI_PART_KERN
].offset
= parts
[RBSPI_PART_SCONF
].offset
111 + parts
[RBSPI_PART_SCONF
].size
;
112 parts
[RBSPI_PART_KERN
].size
= RB_KERNEL_SIZE
113 - parts
[RBSPI_PART_KERN
].offset
;
115 parts
[RBSPI_PART_ROOT
].name
= "rootfs";
116 parts
[RBSPI_PART_ROOT
].offset
= parts
[RBSPI_PART_KERN
].offset
117 + parts
[RBSPI_PART_KERN
].size
;
118 parts
[RBSPI_PART_ROOT
].size
= MTDPART_SIZ_FULL
;
121 static struct flash_platform_data rbspi_spi_flash_data
= {
122 .parts
= rbspi_spi_partitions
,
123 .nr_parts
= ARRAY_SIZE(rbspi_spi_partitions
),
126 /* Several boards only have a single reset button wired to GPIO 16 */
127 #define RBSPI_GPIO_BTN_RESET16 16
129 static struct gpio_keys_button rbspi_gpio_keys_reset16
[] __initdata
= {
131 .desc
= "Reset button",
134 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
135 .gpio
= RBSPI_GPIO_BTN_RESET16
,
140 /* RB mAP L-2nD gpios */
141 #define RBMAPL_GPIO_LED_POWER 17
142 #define RBMAPL_GPIO_LED_USER 14
143 #define RBMAPL_GPIO_LED_ETH 4
144 #define RBMAPL_GPIO_LED_WLAN 11
146 static struct gpio_led rbmapl_leds
[] __initdata
= {
148 .name
= "rb:green:power",
149 .gpio
= RBMAPL_GPIO_LED_POWER
,
151 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
153 .name
= "rb:green:user",
154 .gpio
= RBMAPL_GPIO_LED_USER
,
157 .name
= "rb:green:eth",
158 .gpio
= RBMAPL_GPIO_LED_ETH
,
161 .name
= "rb:green:wlan",
162 .gpio
= RBMAPL_GPIO_LED_WLAN
,
167 /* RB 941L-2nD gpios */
168 #define RBHAPL_GPIO_LED_USER 14
169 static struct gpio_led rbhapl_leds
[] __initdata
= {
171 .name
= "rb:green:user",
172 .gpio
= RBHAPL_GPIO_LED_USER
,
178 #define RBSPI_SSR_GPIO_BASE 40
179 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
181 /* RB 951Ui-2nD gpios */
182 #define RB952_SSR_BIT_LED_LAN1 0
183 #define RB952_SSR_BIT_LED_LAN2 1
184 #define RB952_SSR_BIT_LED_LAN3 2
185 #define RB952_SSR_BIT_LED_LAN4 3
186 #define RB952_SSR_BIT_LED_LAN5 4
187 #define RB952_SSR_BIT_USB_POWER 5
188 #define RB952_SSR_BIT_LED_WLAN 6
189 #define RB952_GPIO_SSR_CS 11
190 #define RB952_GPIO_LED_USER 4
191 #define RB952_GPIO_POE_POWER 14
192 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
193 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
194 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
195 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
196 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
197 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
198 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
200 static struct gpio_led rb952_leds
[] __initdata
= {
202 .name
= "rb:green:user",
203 .gpio
= RB952_GPIO_LED_USER
,
206 .name
= "rb:blue:wlan",
207 .gpio
= RB952_GPIO_LED_WLAN
,
210 .name
= "rb:green:port1",
211 .gpio
= RB952_GPIO_LED_LAN1
,
214 .name
= "rb:green:port2",
215 .gpio
= RB952_GPIO_LED_LAN2
,
218 .name
= "rb:green:port3",
219 .gpio
= RB952_GPIO_LED_LAN3
,
222 .name
= "rb:green:port4",
223 .gpio
= RB952_GPIO_LED_LAN4
,
226 .name
= "rb:green:port5",
227 .gpio
= RB952_GPIO_LED_LAN5
,
232 static struct gen_74x164_chip_platform_data rbspi_ssr_data
= {
233 .base
= RBSPI_SSR_GPIO_BASE
,
236 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
237 static int rbspi_spi_cs_gpios
[] = {
238 -ENOENT
, /* CS0 is always -ENOENT: natively handled */
239 -ENOENT
, /* CS1 can be updated by the code as necessary */
242 static struct ath79_spi_platform_data rbspi_ath79_spi_data
= {
244 .cs_gpios
= rbspi_spi_cs_gpios
,
248 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
249 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
251 static struct spi_board_info rbspi_spi_info
[] = {
255 .max_speed_hz
= 25000000,
256 .modalias
= "m25p80",
257 .platform_data
= &rbspi_spi_flash_data
,
261 .max_speed_hz
= 25000000,
262 .modalias
= "74x164",
263 .platform_data
= &rbspi_ssr_data
,
267 void __init
rbspi_wlan_init(int wmac_offset
)
270 u8 wlan_mac
[ETH_ALEN
];
272 art_buf
= rb_get_wlan_data();
276 ath79_init_mac(wlan_mac
, ath79_mac_base
, wmac_offset
);
277 ath79_register_wmac(art_buf
+ 0x1000, wlan_mac
);
283 * Common platform init routine for all SPI NOR devices.
285 static int __init
rbspi_platform_setup(void)
287 const struct rb_info
*info
;
290 info
= rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE
)), 0x20000);
294 scnprintf(buf
, sizeof(buf
), "MikroTik %s",
295 (info
->board_name
) ? info
->board_name
: "");
296 mips_set_machine_name(buf
);
298 /* fix partitions based on flash parsing */
299 rbspi_init_partitions(info
);
305 * Common peripherals init routine for all SPI NOR devices.
308 static void __init
rbspi_peripherals_setup(u32 flags
)
312 if (flags
& RBSPI_HAS_SSR
)
313 spi_n
= ARRAY_SIZE(rbspi_spi_info
);
315 spi_n
= 1; /* only one device on bus0 */
317 rbspi_ath79_spi_data
.num_chipselect
= spi_n
;
318 rbspi_ath79_spi_data
.cs_gpios
= rbspi_spi_cs_gpios
;
319 ath79_register_spi(&rbspi_ath79_spi_data
, rbspi_spi_info
, spi_n
);
321 if (flags
& RBSPI_HAS_USB
)
322 ath79_register_usb();
326 * Common network init routine for all SPI NOR devices.
329 static void __init
rbspi_network_setup(u32 flags
, int gmac1_offset
,
332 /* for QCA953x that will init mdio1_device/data */
333 ath79_register_mdio(0, 0x0);
335 if (flags
& RBSPI_HAS_WAN4
) {
336 ath79_setup_ar934x_eth_cfg(0);
338 /* set switch to oper mode 1, PHY4 connected to CPU */
339 ath79_switch_data
.phy4_mii_en
= 1;
340 ath79_switch_data
.phy_poll_mask
|= BIT(4);
342 /* init GMAC0 connected to PHY4 at 100M */
343 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
344 ath79_eth0_data
.phy_mask
= BIT(4);
345 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
346 ath79_register_eth(0);
348 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
349 * to the internal switch.
350 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
351 * the QCA953x, this works because this configuration bit is
352 * the same as the AR934x. There's no equivalent function for
353 * QCA953x for now. */
354 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE
);
358 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, gmac1_offset
);
359 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
360 ath79_register_eth(1);
362 if (flags
& RBSPI_HAS_WLAN
)
363 rbspi_wlan_init(wmac_offset
);
367 * Init the mAP lite hardware.
368 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
369 * Trying to use GMAC0 in direct mode was unsucessful, so we're
370 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
371 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
373 static void __init
rbmapl_setup(void)
375 u32 flags
= RBSPI_HAS_WLAN
;
377 if (rbspi_platform_setup())
380 rbspi_peripherals_setup(flags
);
382 /* GMAC1 is HW MAC, WLAN MAC is HW MAC + 1 */
383 rbspi_network_setup(flags
, 0, 1);
385 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds
), rbmapl_leds
);
387 /* mAP lite has a single reset button as gpio 16 */
388 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
389 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
390 rbspi_gpio_keys_reset16
);
392 /* clear internal multiplexing */
393 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
394 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER
, AR934X_GPIO_OUT_GPIO
);
398 * Init the hAP lite hardware.
399 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
400 * being assigned to LAN on the casing, and port 1 being assigned
401 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
402 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
404 static void __init
rbhapl_setup(void)
406 u32 flags
= RBSPI_HAS_WLAN
;
408 if (rbspi_platform_setup())
411 rbspi_peripherals_setup(flags
);
413 /* GMAC1 is HW MAC, WLAN MAC is HW MAC + 4 */
414 rbspi_network_setup(flags
, 0, 4);
416 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds
), rbhapl_leds
);
418 /* hAP lite has a single reset button as gpio 16 */
419 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
420 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
421 rbspi_gpio_keys_reset16
);
425 * The hAP, hEX lite and hEX PoE lite share the same platform
427 static void __init
rbspi_952_750r2_setup(u32 flags
)
429 if (flags
& RBSPI_HAS_SSR
)
430 rbspi_spi_cs_gpios
[1] = RB952_GPIO_SSR_CS
;
432 rbspi_peripherals_setup(flags
);
434 /* GMAC1 is HW MAC + 1, WLAN MAC IS HW MAC + 5 */
435 rbspi_network_setup(flags
, 1, 5);
437 if (flags
& RBSPI_HAS_USB
)
438 gpio_request_one(RB952_GPIO_USB_POWER
,
439 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
442 if (flags
& RBSPI_HAS_POE
)
443 gpio_request_one(RB952_GPIO_POE_POWER
,
444 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
447 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds
), rb952_leds
);
449 /* These devices have a single reset button as gpio 16 */
450 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
451 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
452 rbspi_gpio_keys_reset16
);
456 * Init the hAP hardware.
457 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
458 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
459 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
460 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
461 * internal switch for the LAN ports.
462 * The device also has USB, PoE output and an SSR used for LED multiplexing.
464 static void __init
rb952_setup(void)
466 u32 flags
= RBSPI_HAS_WLAN
| RBSPI_HAS_WAN4
| RBSPI_HAS_USB
|
467 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
469 if (rbspi_platform_setup())
472 rbspi_952_750r2_setup(flags
);
476 * Init the hEX (PoE) lite hardware.
477 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
478 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
479 * without USB and POE. It shares the same bootloader board identifier.
481 static void __init
rb750upr2_setup(void)
483 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_SSR
;
485 if (rbspi_platform_setup())
488 /* differentiate the hEX lite from the hEX PoE lite */
489 if (strstr(mips_get_machine_name(), "750UP r2"))
490 flags
|= RBSPI_HAS_USB
| RBSPI_HAS_POE
;
492 rbspi_952_750r2_setup(flags
);
495 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL
, "map-hb", rbmapl_setup
);
496 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941
, "H951L", rbhapl_setup
);
497 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952
, "952-hb", rb952_setup
);
498 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2
, "750-hb", rb750upr2_setup
);