2 * MikroTik SPI-NOR RouterBOARDs support
4 * - MikroTik RouterBOARD mAP 2nD
5 * - MikroTik RouterBOARD mAP L-2nD
6 * - MikroTik RouterBOARD 911-2Hn (911 Lite2)
7 * - MikroTik RouterBOARD 911-5Hn (911 Lite5)
8 * - MikroTik RouterBOARD 941L-2nD
9 * - MikroTik RouterBOARD 951Ui-2nD
10 * - MikroTik RouterBOARD 952Ui-5ac2nD
11 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
12 * - MikroTik RouterBOARD 750UP r2
13 * - MikroTik RouterBOARD 750P-PBr2
14 * - MikroTik RouterBOARD 750 r2
15 * - MikroTik RouterBOARD LHG 5nD
16 * - MikroTik RouterBOARD wAP2nD
17 * - MikroTik RouterBOARD wAP G-5HacT2HnDwAP (wAP AC)
18 * - MikroTik RouterBOARD wAP R-2nD
20 * Preliminary support for the following hardware
21 * - MikroTik RouterBOARD cAP2nD
22 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
23 * hardware as the mAP L-2nD. It is unknown if they share the same board
26 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
27 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
28 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License version 2 as published
32 * by the Free Software Foundation.
35 #include <linux/pci.h>
36 #include <linux/platform_device.h>
37 #include <linux/phy.h>
38 #include <linux/routerboot.h>
39 #include <linux/gpio.h>
41 #include <linux/spi/spi.h>
42 #include <linux/spi/74x164.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/partitions.h>
47 #include <linux/ar8216_platform.h>
48 #include <linux/platform_data/phy-at803x.h>
49 #include <linux/platform_data/mdio-gpio.h>
52 #include <asm/mach-ath79/ar71xx_regs.h>
53 #include <asm/mach-ath79/ath79.h>
58 #include "dev-gpio-buttons.h"
59 #include "dev-leds-gpio.h"
60 #include "dev-m25p80.h"
63 #include "machtypes.h"
65 #include "routerboot.h"
67 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
68 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
70 #define RBSPI_HAS_USB BIT(0)
71 #define RBSPI_HAS_WLAN0 BIT(1)
72 #define RBSPI_HAS_WLAN1 BIT(2)
73 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
74 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
75 #define RBSPI_HAS_POE BIT(5)
76 #define RBSPI_HAS_MDIO1 BIT(6)
77 #define RBSPI_HAS_PCI BIT(7)
79 #define RB_ROUTERBOOT_OFFSET 0x0000
80 #define RB_BIOS_SIZE 0x1000
81 #define RB_SOFT_CFG_SIZE 0x1000
83 /* Flash partitions indexes */
94 static struct mtd_partition rbspi_spi_partitions
[RBSPI_PARTS
];
97 * Setup the SPI flash partition table based on initial parsing.
98 * The kernel can be at any aligned position and have any size.
100 static void __init
rbspi_init_partitions(const struct rb_info
*info
)
102 struct mtd_partition
*parts
= rbspi_spi_partitions
;
103 memset(parts
, 0x0, sizeof(*parts
));
105 parts
[RBSPI_PART_RBOOT
].name
= "routerboot";
106 parts
[RBSPI_PART_RBOOT
].offset
= RB_ROUTERBOOT_OFFSET
;
107 parts
[RBSPI_PART_RBOOT
].size
= info
->hard_cfg_offs
;
108 parts
[RBSPI_PART_RBOOT
].mask_flags
= MTD_WRITEABLE
;
110 parts
[RBSPI_PART_HCONF
].name
= "hard_config";
111 parts
[RBSPI_PART_HCONF
].offset
= info
->hard_cfg_offs
;
112 parts
[RBSPI_PART_HCONF
].size
= info
->hard_cfg_size
;
113 parts
[RBSPI_PART_HCONF
].mask_flags
= MTD_WRITEABLE
;
115 parts
[RBSPI_PART_BIOS
].name
= "bios";
116 parts
[RBSPI_PART_BIOS
].offset
= info
->hard_cfg_offs
117 + info
->hard_cfg_size
;
118 parts
[RBSPI_PART_BIOS
].size
= RB_BIOS_SIZE
;
119 parts
[RBSPI_PART_BIOS
].mask_flags
= MTD_WRITEABLE
;
121 parts
[RBSPI_PART_RBOOT2
].name
= "routerboot2";
122 parts
[RBSPI_PART_RBOOT2
].offset
= parts
[RBSPI_PART_BIOS
].offset
124 parts
[RBSPI_PART_RBOOT2
].size
= info
->soft_cfg_offs
125 - parts
[RBSPI_PART_RBOOT2
].offset
;
126 parts
[RBSPI_PART_RBOOT2
].mask_flags
= MTD_WRITEABLE
;
128 parts
[RBSPI_PART_SCONF
].name
= "soft_config";
129 parts
[RBSPI_PART_SCONF
].offset
= info
->soft_cfg_offs
;
130 parts
[RBSPI_PART_SCONF
].size
= RB_SOFT_CFG_SIZE
;
132 parts
[RBSPI_PART_FIRMW
].name
= "firmware";
133 parts
[RBSPI_PART_FIRMW
].offset
= parts
[RBSPI_PART_SCONF
].offset
134 + parts
[RBSPI_PART_SCONF
].size
;
135 parts
[RBSPI_PART_FIRMW
].size
= MTDPART_SIZ_FULL
;
138 static struct flash_platform_data rbspi_spi_flash_data
= {
139 .parts
= rbspi_spi_partitions
,
140 .nr_parts
= ARRAY_SIZE(rbspi_spi_partitions
),
144 * Several boards only have a single reset button, use a common
145 * structure for that.
147 static struct gpio_keys_button rbspi_gpio_keys_reset
[] __initdata
= {
149 .desc
= "Reset button",
152 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
153 .gpio
= -ENOENT
, /* filled dynamically */
158 /* RB mAP L-2nD gpios */
159 #define RBMAPL_GPIO_LED_POWER 17
160 #define RBMAPL_GPIO_LED_USER 14
161 #define RBMAPL_GPIO_LED_ETH 4
162 #define RBMAPL_GPIO_LED_WLAN 11
163 #define RBMAPL_GPIO_BTN_RESET 16
165 static struct gpio_led rbmapl_leds
[] __initdata
= {
167 .name
= "rb:green:power",
168 .gpio
= RBMAPL_GPIO_LED_POWER
,
170 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
172 .name
= "rb:green:user",
173 .gpio
= RBMAPL_GPIO_LED_USER
,
176 .name
= "rb:green:eth",
177 .gpio
= RBMAPL_GPIO_LED_ETH
,
180 .name
= "rb:green:wlan",
181 .gpio
= RBMAPL_GPIO_LED_WLAN
,
186 /* RB 941L-2nD gpios */
187 #define RBHAPL_GPIO_LED_USER 14
188 #define RBHAPL_GPIO_BTN_RESET 16
190 static struct gpio_led rbhapl_leds
[] __initdata
= {
192 .name
= "rb:green:user",
193 .gpio
= RBHAPL_GPIO_LED_USER
,
199 #define RBSPI_SSR_GPIO_BASE 40
200 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
202 /* RB 951Ui-2nD gpios */
203 #define RB952_SSR_BIT_LED_LAN1 0
204 #define RB952_SSR_BIT_LED_LAN2 1
205 #define RB952_SSR_BIT_LED_LAN3 2
206 #define RB952_SSR_BIT_LED_LAN4 3
207 #define RB952_SSR_BIT_LED_LAN5 4
208 #define RB952_SSR_BIT_USB_POWER 5
209 #define RB952_SSR_BIT_LED_WLAN 6
210 #define RB952_GPIO_SSR_CS 11
211 #define RB952_GPIO_LED_USER 4
212 #define RB952_GPIO_POE_POWER 14
213 #define RB952_GPIO_POE_STATUS 12
214 #define RB952_GPIO_BTN_RESET 16
215 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
216 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
217 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
218 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
219 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
220 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
221 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
223 static struct gpio_led rb952_leds
[] __initdata
= {
225 .name
= "rb:green:user",
226 .gpio
= RB952_GPIO_LED_USER
,
229 .name
= "rb:blue:wlan",
230 .gpio
= RB952_GPIO_LED_WLAN
,
233 .name
= "rb:green:port1",
234 .gpio
= RB952_GPIO_LED_LAN1
,
237 .name
= "rb:green:port2",
238 .gpio
= RB952_GPIO_LED_LAN2
,
241 .name
= "rb:green:port3",
242 .gpio
= RB952_GPIO_LED_LAN3
,
245 .name
= "rb:green:port4",
246 .gpio
= RB952_GPIO_LED_LAN4
,
249 .name
= "rb:green:port5",
250 .gpio
= RB952_GPIO_LED_LAN5
,
256 /* RB 962UiGS-5HacT2HnT gpios */
257 #define RB962_GPIO_POE_STATUS 2
258 #define RB962_GPIO_POE_POWER 3
259 #define RB962_GPIO_LED_USER 12
260 #define RB962_GPIO_USB_POWER 13
261 #define RB962_GPIO_BTN_RESET 20
263 static struct gpio_led rb962_leds_gpio
[] __initdata
= {
265 .name
= "rb:green:user",
266 .gpio
= RB962_GPIO_LED_USER
,
271 static const struct ar8327_led_info rb962_leds_ar8327
[] = {
272 AR8327_LED_INFO(PHY0_0
, HW
, "rb:green:port1"),
273 AR8327_LED_INFO(PHY1_0
, HW
, "rb:green:port2"),
274 AR8327_LED_INFO(PHY2_0
, HW
, "rb:green:port3"),
275 AR8327_LED_INFO(PHY3_0
, HW
, "rb:green:port4"),
276 AR8327_LED_INFO(PHY4_0
, HW
, "rb:green:port5"),
279 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg
= {
280 .mode
= AR8327_PAD_MAC_RGMII
,
281 .txclk_delay_en
= true,
282 .rxclk_delay_en
= true,
283 .txclk_delay_sel
= AR8327_CLK_DELAY_SEL1
,
284 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL2
,
285 .mac06_exchange_dis
= true,
288 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg
= {
289 /* Use SGMII interface for GMAC6 of the AR8337 switch */
290 .mode
= AR8327_PAD_MAC_SGMII
,
291 .rxclk_delay_en
= true,
292 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL0
,
295 static struct ar8327_led_cfg rb962_ar8327_led_cfg
= {
296 .led_ctrl0
= 0xc737c737,
297 .led_ctrl1
= 0x00000000,
298 .led_ctrl2
= 0x00000000,
299 .led_ctrl3
= 0x0030c300,
303 static struct ar8327_platform_data rb962_ar8327_data
= {
304 .pad0_cfg
= &rb962_ar8327_pad0_cfg
,
305 .pad6_cfg
= &rb962_ar8327_pad6_cfg
,
308 .speed
= AR8327_PORT_SPEED_1000
,
315 .speed
= AR8327_PORT_SPEED_1000
,
320 .led_cfg
= &rb962_ar8327_led_cfg
,
321 .num_leds
= ARRAY_SIZE(rb962_leds_ar8327
),
322 .leds
= rb962_leds_ar8327
,
325 static struct mdio_board_info rb962_mdio0_info
[] = {
327 .bus_id
= "ag71xx-mdio.0",
329 .platform_data
= &rb962_ar8327_data
,
333 /* RB wAP-2nD gpios */
334 #define RBWAP_GPIO_LED_USER 14
335 #define RBWAP_GPIO_LED_WLAN 11
336 #define RBWAP_GPIO_BTN_RESET 16
338 static struct gpio_led rbwap_leds
[] __initdata
= {
340 .name
= "rb:green:user",
341 .gpio
= RBWAP_GPIO_LED_USER
,
344 .name
= "rb:green:wlan",
345 .gpio
= RBWAP_GPIO_LED_WLAN
,
350 /* RB cAP-2nD gpios */
351 #define RBCAP_GPIO_LED_1 14
352 #define RBCAP_GPIO_LED_2 12
353 #define RBCAP_GPIO_LED_3 11
354 #define RBCAP_GPIO_LED_4 4
355 #define RBCAP_GPIO_LED_ALL 13
357 static struct gpio_led rbcap_leds
[] __initdata
= {
359 .name
= "rb:green:rssi1",
360 .gpio
= RBCAP_GPIO_LED_1
,
363 .name
= "rb:green:rssi2",
364 .gpio
= RBCAP_GPIO_LED_2
,
367 .name
= "rb:green:rssi3",
368 .gpio
= RBCAP_GPIO_LED_3
,
371 .name
= "rb:green:rssi4",
372 .gpio
= RBCAP_GPIO_LED_4
,
377 /* RB mAP-2nD gpios */
378 #define RBMAP_SSR_BIT_LED_LAN1 0
379 #define RBMAP_SSR_BIT_LED_LAN2 1
380 #define RBMAP_SSR_BIT_LED_POEO 2
381 #define RBMAP_SSR_BIT_LED_USER 3
382 #define RBMAP_SSR_BIT_LED_WLAN 4
383 #define RBMAP_SSR_BIT_USB_POWER 5
384 #define RBMAP_SSR_BIT_LED_APCAP 6
385 #define RBMAP_GPIO_BTN_RESET 16
386 #define RBMAP_GPIO_SSR_CS 11
387 #define RBMAP_GPIO_LED_POWER 4
388 #define RBMAP_GPIO_POE_POWER 14
389 #define RBMAP_GPIO_POE_STATUS 12
390 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
391 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
392 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
393 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
394 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
395 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
396 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
398 static struct gpio_led rbmap_leds
[] __initdata
= {
400 .name
= "rb:green:power",
401 .gpio
= RBMAP_GPIO_LED_POWER
,
403 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
405 .name
= "rb:green:eth1",
406 .gpio
= RBMAP_GPIO_LED_LAN1
,
409 .name
= "rb:green:eth2",
410 .gpio
= RBMAP_GPIO_LED_LAN2
,
413 .name
= "rb:red:poe_out",
414 .gpio
= RBMAP_GPIO_LED_POEO
,
417 .name
= "rb:green:user",
418 .gpio
= RBMAP_GPIO_LED_USER
,
421 .name
= "rb:green:wlan",
422 .gpio
= RBMAP_GPIO_LED_WLAN
,
425 .name
= "rb:green:ap_cap",
426 .gpio
= RBMAP_GPIO_LED_APCAP
,
431 /* RB LHG 5nD gpios */
432 #define RBLHG_GPIO_LED_0 13
433 #define RBLHG_GPIO_LED_1 12
434 #define RBLHG_GPIO_LED_2 4
435 #define RBLHG_GPIO_LED_3 21
436 #define RBLHG_GPIO_LED_4 18
437 #define RBLHG_GPIO_LED_ETH 14
438 #define RBLHG_GPIO_LED_POWER 11
439 #define RBLHG_GPIO_LED_USER 20
440 #define RBLHG_GPIO_BTN_RESET 15
442 static struct gpio_led rblhg_leds
[] __initdata
= {
444 .name
= "rb:green:rssi0",
445 .gpio
= RBLHG_GPIO_LED_0
,
448 .name
= "rb:green:rssi1",
449 .gpio
= RBLHG_GPIO_LED_1
,
452 .name
= "rb:green:rssi2",
453 .gpio
= RBLHG_GPIO_LED_2
,
456 .name
= "rb:green:rssi3",
457 .gpio
= RBLHG_GPIO_LED_3
,
460 .name
= "rb:green:rssi4",
461 .gpio
= RBLHG_GPIO_LED_4
,
464 .name
= "rb:green:eth",
465 .gpio
= RBLHG_GPIO_LED_ETH
,
468 .name
= "rb:green:user",
469 .gpio
= RBLHG_GPIO_LED_USER
,
472 .name
= "rb:blue:power",
473 .gpio
= RBLHG_GPIO_LED_POWER
,
475 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
479 /* RB w APG-5HacT2HnD (wAP AC) gpios*/
480 #define RBWAPGSC_LED1 1
481 #define RBWAPGSC_LED2 8
482 #define RBWAPGSC_LED3 9
483 #define RBWAPGSC_POWERLED 16
484 #define RBWAPGSC_GPIO_BTN_RESET 1
485 #define RBWAPGSC_GPIO_MDIO_MDC 12
486 #define RBWAPGSC_GPIO_MDIO_DATA 11
487 #define RBWAPGSC_MDIO_PHYADDR 0
489 static struct gpio_led rbwapgsc_leds
[] __initdata
= {
491 .name
= "rb:green:led1",
492 .gpio
= RBWAPGSC_LED1
,
495 .name
= "rb:blue:power",
496 .gpio
= RBWAPGSC_POWERLED
,
501 static struct mdio_gpio_platform_data rbwapgsc_mdio_data
= {
502 .mdc
= RBWAPGSC_GPIO_MDIO_MDC
,
503 .mdio
= RBWAPGSC_GPIO_MDIO_DATA
,
504 .phy_mask
= ~BIT(RBWAPGSC_MDIO_PHYADDR
),
507 static struct platform_device rbwapgsc_phy_device
= {
511 .platform_data
= &rbwapgsc_mdio_data
516 #define RB911L_GPIO_BTN_RESET 15
517 #define RB911L_GPIO_LED_1 13
518 #define RB911L_GPIO_LED_2 12
519 #define RB911L_GPIO_LED_3 4
520 #define RB911L_GPIO_LED_4 21
521 #define RB911L_GPIO_LED_5 18
522 #define RB911L_GPIO_LED_ETH 20
523 #define RB911L_GPIO_LED_POWER 11
524 #define RB911L_GPIO_LED_USER 3
525 #define RB911L_GPIO_PIN_HOLE 14 /* for reference */
527 static struct gpio_led rb911l_leds
[] __initdata
= {
529 .name
= "rb:green:eth",
530 .gpio
= RB911L_GPIO_LED_ETH
,
533 .name
= "rb:green:led1",
534 .gpio
= RB911L_GPIO_LED_1
,
537 .name
= "rb:green:led2",
538 .gpio
= RB911L_GPIO_LED_2
,
541 .name
= "rb:green:led3",
542 .gpio
= RB911L_GPIO_LED_3
,
545 .name
= "rb:green:led4",
546 .gpio
= RB911L_GPIO_LED_4
,
549 .name
= "rb:green:led5",
550 .gpio
= RB911L_GPIO_LED_5
,
553 .name
= "rb:green:power",
554 .gpio
= RB911L_GPIO_LED_POWER
,
555 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
558 .name
= "rb:green:user",
559 .gpio
= RB911L_GPIO_LED_USER
,
565 static struct gen_74x164_chip_platform_data rbspi_ssr_data
= {
566 .base
= RBSPI_SSR_GPIO_BASE
,
570 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
571 static int rbspi_spi_cs_gpios
[] = {
572 -ENOENT
, /* CS0 is always -ENOENT: natively handled */
573 -ENOENT
, /* CS1 can be updated by the code as necessary */
576 static struct ath79_spi_platform_data rbspi_ath79_spi_data
= {
578 .cs_gpios
= rbspi_spi_cs_gpios
,
582 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
583 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
585 static struct spi_board_info rbspi_spi_info
[] = {
589 .max_speed_hz
= 25000000,
590 .modalias
= "m25p80",
591 .platform_data
= &rbspi_spi_flash_data
,
595 .max_speed_hz
= 25000000,
596 .modalias
= "74x164",
597 .platform_data
= &rbspi_ssr_data
,
601 void __init
rbspi_wlan_init(u16 id
, int wmac_offset
)
604 u8 wlan_mac
[ETH_ALEN
];
606 art_buf
= rb_get_ext_wlan_data(id
);
610 ath79_init_mac(wlan_mac
, ath79_mac_base
, wmac_offset
);
611 ath79_register_wmac(art_buf
+ 0x1000, wlan_mac
);
616 #define RBSPI_MACH_BUFLEN 64
618 * Common platform init routine for all SPI NOR devices.
620 static __init
const struct rb_info
*rbspi_platform_setup(void)
622 const struct rb_info
*info
;
623 char buf
[RBSPI_MACH_BUFLEN
] = "MikroTik ";
625 int len
= RBSPI_MACH_BUFLEN
- strlen(buf
) - 1;
627 info
= rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE
)), 0x20000);
631 if (info
->board_name
) {
632 str
= "RouterBOARD ";
633 if (strncmp(info
->board_name
, str
, strlen(str
))) {
634 strncat(buf
, str
, len
);
637 strncat(buf
, info
->board_name
, len
);
640 strncat(buf
, "UNKNOWN", len
);
642 mips_set_machine_name(buf
);
644 /* fix partitions based on flash parsing */
645 rbspi_init_partitions(info
);
651 * Common peripherals init routine for all SPI NOR devices.
654 static void __init
rbspi_peripherals_setup(u32 flags
)
658 if (flags
& RBSPI_HAS_SSR
)
659 spi_n
= ARRAY_SIZE(rbspi_spi_info
);
661 spi_n
= 1; /* only one device on bus0 */
663 rbspi_ath79_spi_data
.num_chipselect
= spi_n
;
664 rbspi_ath79_spi_data
.cs_gpios
= rbspi_spi_cs_gpios
;
665 ath79_register_spi(&rbspi_ath79_spi_data
, rbspi_spi_info
, spi_n
);
667 if (flags
& RBSPI_HAS_USB
)
668 ath79_register_usb();
670 if (flags
& RBSPI_HAS_PCI
)
671 ath79_register_pci();
675 * Common network init routine for all SPI NOR devices.
678 static void __init
rbspi_network_setup(u32 flags
, int gmac1_offset
,
679 int wmac0_offset
, int wmac1_offset
)
681 /* for QCA953x that will init mdio1_device/data */
682 ath79_register_mdio(0, 0x0);
683 if (flags
& RBSPI_HAS_MDIO1
)
684 ath79_register_mdio(1, 0x0);
686 if (flags
& RBSPI_HAS_WAN4
) {
687 ath79_setup_ar934x_eth_cfg(0);
689 /* set switch to oper mode 1, PHY4 connected to CPU */
690 ath79_switch_data
.phy4_mii_en
= 1;
691 ath79_switch_data
.phy_poll_mask
|= BIT(4);
693 /* init GMAC0 connected to PHY4 at 100M */
694 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
695 ath79_eth0_data
.phy_mask
= BIT(4);
696 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
697 ath79_register_eth(0);
699 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
700 * to the internal switch.
701 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
702 * the QCA953x, this works because this configuration bit is
703 * the same as the AR934x. There's no equivalent function for
704 * QCA953x for now. */
705 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE
);
709 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, gmac1_offset
);
710 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
711 ath79_register_eth(1);
713 if (flags
& RBSPI_HAS_WLAN0
)
714 rbspi_wlan_init(0, wmac0_offset
);
716 if (flags
& RBSPI_HAS_WLAN1
)
717 rbspi_wlan_init(1, wmac1_offset
);
720 static __init
void rbspi_register_reset_button(int gpio
)
722 rbspi_gpio_keys_reset
[0].gpio
= gpio
;
723 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
724 ARRAY_SIZE(rbspi_gpio_keys_reset
),
725 rbspi_gpio_keys_reset
);
729 * Init the mAP lite hardware (QCA953x).
730 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
731 * Trying to use GMAC0 in direct mode was unsucessful, so we're
732 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
733 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
735 static void __init
rbmapl_setup(void)
737 u32 flags
= RBSPI_HAS_WLAN0
;
739 if (!rbspi_platform_setup())
742 rbspi_peripherals_setup(flags
);
744 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
745 rbspi_network_setup(flags
, 0, 1, 0);
747 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds
), rbmapl_leds
);
749 /* mAP lite has a single reset button as gpio 16 */
750 rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET
);
752 /* clear internal multiplexing */
753 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
754 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER
, AR934X_GPIO_OUT_GPIO
);
758 * Init the hAP lite hardware (QCA953x).
759 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
760 * being assigned to LAN on the casing, and port 1 being assigned
761 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
762 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
764 static void __init
rbhapl_setup(void)
766 u32 flags
= RBSPI_HAS_WLAN0
;
768 if (!rbspi_platform_setup())
771 rbspi_peripherals_setup(flags
);
773 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
774 rbspi_network_setup(flags
, 0, 4, 0);
776 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds
), rbhapl_leds
);
778 /* hAP lite has a single reset button as gpio 16 */
779 rbspi_register_reset_button(RBHAPL_GPIO_BTN_RESET
);
783 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
785 static void __init
rbspi_952_750r2_setup(u32 flags
)
787 if (flags
& RBSPI_HAS_SSR
)
788 rbspi_spi_cs_gpios
[1] = RB952_GPIO_SSR_CS
;
790 rbspi_peripherals_setup(flags
);
793 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
794 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
796 rbspi_network_setup(flags
, 1, 5, 6);
798 if (flags
& RBSPI_HAS_USB
)
799 gpio_request_one(RB952_GPIO_USB_POWER
,
800 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
803 if (flags
& RBSPI_HAS_POE
)
804 gpio_request_one(RB952_GPIO_POE_POWER
,
805 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
808 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds
), rb952_leds
);
810 /* These devices have a single reset button as gpio 16 */
811 rbspi_register_reset_button(RB952_GPIO_BTN_RESET
);
815 * Init the hAP (ac lite) hardware (QCA953x).
816 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
817 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
818 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
819 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
820 * internal switch for the LAN ports.
821 * The device also has USB, PoE output and an SSR used for LED multiplexing.
822 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
823 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
825 static void __init
rb952_setup(void)
827 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_USB
|
828 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
830 if (!rbspi_platform_setup())
833 /* differentiate the hAP from the hAP ac lite */
834 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
835 flags
|= RBSPI_HAS_WLAN1
| RBSPI_HAS_PCI
;
837 flags
|= RBSPI_HAS_WLAN0
;
839 rbspi_952_750r2_setup(flags
);
843 * Init the hEX (PoE) lite hardware (QCA953x).
844 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
845 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
846 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
847 * lite, only without USB. It shares the same bootloader board identifier.
849 static void __init
rb750upr2_setup(void)
851 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_SSR
;
853 if (!rbspi_platform_setup())
856 /* differentiate the hEX lite from the hEX PoE lite */
857 if (strstr(mips_get_machine_name(), "750UP r2"))
858 flags
|= RBSPI_HAS_USB
| RBSPI_HAS_POE
;
860 /* differentiate the Powerbox from the hEX lite */
861 else if (strstr(mips_get_machine_name(), "750P r2"))
862 flags
|= RBSPI_HAS_POE
;
864 rbspi_952_750r2_setup(flags
);
868 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
869 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
870 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
871 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
872 * The SFP cage is not assigned by default on RouterOS. Extra work is required
873 * to support this interface as it is directly connected to the SoC (eth1).
874 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
875 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
876 * they are not attached to GPIOs, extra work is required to support these.
877 * PoE and USB output power control is supported.
879 static void __init
rb962_setup(void)
881 u32 flags
= RBSPI_HAS_USB
| RBSPI_HAS_POE
| RBSPI_HAS_PCI
;
883 if (!rbspi_platform_setup())
886 rbspi_peripherals_setup(flags
);
888 /* Do not call rbspi_network_setup as we have a discrete switch chip */
889 ath79_eth0_pll_data
.pll_1000
= 0xae000000;
890 ath79_eth0_pll_data
.pll_100
= 0xa0000101;
891 ath79_eth0_pll_data
.pll_10
= 0xa0001313;
893 ath79_register_mdio(0, 0x0);
894 mdiobus_register_board_info(rb962_mdio0_info
,
895 ARRAY_SIZE(rb962_mdio0_info
));
897 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN
);
899 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
900 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
901 ath79_eth0_data
.phy_mask
= BIT(0);
902 ath79_eth0_data
.mii_bus_dev
= &ath79_mdio0_device
.dev
;
903 ath79_register_eth(0);
905 /* WLAN1 MAC is HW MAC + 7 */
906 rbspi_wlan_init(1, 7);
908 if (flags
& RBSPI_HAS_USB
)
909 gpio_request_one(RB962_GPIO_USB_POWER
,
910 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
913 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
914 if (flags
& RBSPI_HAS_POE
)
915 gpio_request_one(RB962_GPIO_POE_POWER
,
916 GPIOF_OUT_INIT_HIGH
| GPIOF_ACTIVE_LOW
|
917 GPIOF_EXPORT_DIR_FIXED
,
920 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio
),
923 /* This device has a single reset button as gpio 20 */
924 rbspi_register_reset_button(RB962_GPIO_BTN_RESET
);
928 * Init the LHG hardware (AR9344).
929 * The LHG 5nD has a single ethernet port connected to PHY0.
930 * Wireless is provided via 5GHz WLAN1.
932 static void __init
rblhg_setup(void)
934 u32 flags
= RBSPI_HAS_WLAN1
| RBSPI_HAS_MDIO1
;
936 if (!rbspi_platform_setup())
939 rbspi_peripherals_setup(flags
);
941 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
942 rbspi_network_setup(flags
, 0, 0, 1);
944 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds
), rblhg_leds
);
946 rbspi_register_reset_button(RBLHG_GPIO_BTN_RESET
);
950 * Init the wAP hardware.
951 * The wAP 2nD has a single ethernet port.
953 static void __init
rbwap_setup(void)
955 u32 flags
= RBSPI_HAS_WLAN0
;
957 if (!rbspi_platform_setup())
960 rbspi_peripherals_setup(flags
);
962 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
963 rbspi_network_setup(flags
, 0, 1, 0);
965 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds
), rbwap_leds
);
967 /* wAP has a single reset button as GPIO 16 */
968 rbspi_register_reset_button(RBWAP_GPIO_BTN_RESET
);
972 * Init the cAP hardware (EXPERIMENTAL).
973 * The cAP 2nD has a single ethernet port, and a global LED switch.
975 static void __init
rbcap_setup(void)
977 u32 flags
= RBSPI_HAS_WLAN0
;
979 if (!rbspi_platform_setup())
982 rbspi_peripherals_setup(flags
);
984 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
985 rbspi_network_setup(flags
, 0, 1, 0);
987 gpio_request_one(RBCAP_GPIO_LED_ALL
,
988 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
991 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds
), rbcap_leds
);
995 * Init the mAP hardware.
996 * The mAP 2nD has two ethernet ports, PoE output, SSR for LED
997 * multiplexing and USB port.
999 static void __init
rbmap_setup(void)
1001 u32 flags
= RBSPI_HAS_USB
| RBSPI_HAS_WLAN0
|
1002 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
1004 if (!rbspi_platform_setup())
1007 rbspi_spi_cs_gpios
[1] = RBMAP_GPIO_SSR_CS
;
1008 rbspi_peripherals_setup(flags
);
1010 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
1011 rbspi_network_setup(flags
, 0, 2, 0);
1013 if (flags
& RBSPI_HAS_POE
)
1014 gpio_request_one(RBMAP_GPIO_POE_POWER
,
1015 GPIOF_OUT_INIT_LOW
| GPIOF_EXPORT_DIR_FIXED
,
1018 /* USB power GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
1019 if (flags
& RBSPI_HAS_USB
)
1020 gpio_request_one(RBMAP_GPIO_USB_POWER
,
1021 GPIOF_OUT_INIT_HIGH
| GPIOF_ACTIVE_LOW
|
1022 GPIOF_EXPORT_DIR_FIXED
,
1025 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds
), rbmap_leds
);
1027 /* mAP 2nD has a single reset button as gpio 16 */
1028 rbspi_register_reset_button(RBMAP_GPIO_BTN_RESET
);
1032 * Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware.
1033 * The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC
1034 * 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor
1035 * (currently not supported).
1037 static void __init
rbwapgsc_setup(void)
1039 u32 flags
= RBSPI_HAS_PCI
;
1041 if (!rbspi_platform_setup())
1044 rbspi_peripherals_setup(flags
);
1046 platform_device_register(&rbwapgsc_phy_device
);
1048 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
1049 ath79_eth1_data
.mii_bus_dev
= &rbwapgsc_phy_device
.dev
;
1050 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_SGMII
;
1051 ath79_eth1_data
.phy_mask
= BIT(RBWAPGSC_MDIO_PHYADDR
);
1052 ath79_eth1_pll_data
.pll_1000
= 0x03000101;
1053 ath79_eth1_pll_data
.pll_100
= 0x80000101;
1054 ath79_eth1_pll_data
.pll_10
= 0x80001313;
1055 ath79_eth1_data
.speed
= SPEED_1000
;
1056 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
1057 ath79_register_eth(1);
1059 rbspi_wlan_init(1, 2);
1061 rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET
);
1063 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE
|
1064 QCA955X_GPIO_REG_OUT_FUNC4
|
1065 QCA955X_GPIO_REG_OUT_FUNC3
);
1067 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds
),
1072 * Setup the 911L hardware (AR9344).
1074 static void __init
rb911l_setup(void)
1076 const struct rb_info
*info
;
1078 info
= rbspi_platform_setup();
1082 if (!rb_has_hw_option(info
, RB_HW_OPT_NO_NAND
)) {
1084 * Old hardware revisions might be equipped with a NAND flash
1085 * chip instead of the 16MiB SPI NOR device. Those boards are
1086 * not supported at the moment, so throw a warning and skip
1087 * the peripheral setup to avoid messing up the data in the
1090 WARN(1, "The NAND flash on this board is not supported.\n");
1092 rbspi_peripherals_setup(0);
1095 ath79_register_mdio(1, 0x0);
1097 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
1099 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
1100 ath79_eth1_data
.speed
= SPEED_1000
;
1101 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
1103 ath79_register_eth(1);
1105 rbspi_wlan_init(0, 1);
1107 rbspi_register_reset_button(RB911L_GPIO_BTN_RESET
);
1109 /* Make the eth LED controllable by software. */
1110 ath79_gpio_output_select(RB911L_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
1112 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb911l_leds
), rb911l_leds
);
1115 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL
, "map-hb", rbmapl_setup
);
1116 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941
, "H951L", rbhapl_setup
);
1117 MIPS_MACHINE_NONAME(ATH79_MACH_RB_911L
, "911L", rb911l_setup
);
1118 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952
, "952-hb", rb952_setup
);
1119 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962
, "962", rb962_setup
);
1120 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2
, "750-hb", rb750upr2_setup
);
1121 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5
, "lhg", rblhg_setup
);
1122 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP
, "wap-hb", rbwap_setup
);
1123 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPR
, "wap-lte", rbwap_setup
);
1124 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP
, "cap-hb", rbcap_setup
);
1125 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP
, "map2-hb", rbmap_setup
);
1126 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPAC
, "wapg-sc", rbwapgsc_setup
);