2 * MikroTik SPI-NOR RouterBOARDs support
4 * - MikroTik RouterBOARD mAP 2nD
5 * - MikroTik RouterBOARD mAP L-2nD
6 * - MikroTik RouterBOARD 911-2Hn (911 Lite2)
7 * - MikroTik RouterBOARD 911-5Hn (911 Lite5)
8 * - MikroTik RouterBOARD 941L-2nD
9 * - MikroTik RouterBOARD 951Ui-2nD
10 * - MikroTik RouterBOARD 952Ui-5ac2nD
11 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
12 * - MikroTik RouterBOARD 750UP r2
13 * - MikroTik RouterBOARD 750P-PBr2
14 * - MikroTik RouterBOARD 750 r2
15 * - MikroTik RouterBOARD LHG 5nD
16 * - MikroTik RouterBOARD wAP2nD
17 * - MikroTik RouterBOARD wAP G-5HacT2HnDwAP (wAP AC)
19 * Preliminary support for the following hardware
20 * - MikroTik RouterBOARD cAP2nD
21 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
22 * hardware as the mAP L-2nD. It is unknown if they share the same board
25 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
26 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
27 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License version 2 as published
31 * by the Free Software Foundation.
34 #include <linux/pci.h>
35 #include <linux/platform_device.h>
36 #include <linux/phy.h>
37 #include <linux/routerboot.h>
38 #include <linux/gpio.h>
40 #include <linux/spi/spi.h>
41 #include <linux/spi/74x164.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/partitions.h>
46 #include <linux/ar8216_platform.h>
47 #include <linux/platform_data/phy-at803x.h>
48 #include <linux/platform_data/mdio-gpio.h>
51 #include <asm/mach-ath79/ar71xx_regs.h>
52 #include <asm/mach-ath79/ath79.h>
57 #include "dev-gpio-buttons.h"
58 #include "dev-leds-gpio.h"
59 #include "dev-m25p80.h"
62 #include "machtypes.h"
64 #include "routerboot.h"
66 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
67 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
69 #define RBSPI_HAS_USB BIT(0)
70 #define RBSPI_HAS_WLAN0 BIT(1)
71 #define RBSPI_HAS_WLAN1 BIT(2)
72 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
73 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
74 #define RBSPI_HAS_POE BIT(5)
75 #define RBSPI_HAS_MDIO1 BIT(6)
76 #define RBSPI_HAS_PCI BIT(7)
78 #define RB_ROUTERBOOT_OFFSET 0x0000
79 #define RB_BIOS_SIZE 0x1000
80 #define RB_SOFT_CFG_SIZE 0x1000
82 /* Flash partitions indexes */
93 static struct mtd_partition rbspi_spi_partitions
[RBSPI_PARTS
];
96 * Setup the SPI flash partition table based on initial parsing.
97 * The kernel can be at any aligned position and have any size.
99 static void __init
rbspi_init_partitions(const struct rb_info
*info
)
101 struct mtd_partition
*parts
= rbspi_spi_partitions
;
102 memset(parts
, 0x0, sizeof(*parts
));
104 parts
[RBSPI_PART_RBOOT
].name
= "routerboot";
105 parts
[RBSPI_PART_RBOOT
].offset
= RB_ROUTERBOOT_OFFSET
;
106 parts
[RBSPI_PART_RBOOT
].size
= info
->hard_cfg_offs
;
107 parts
[RBSPI_PART_RBOOT
].mask_flags
= MTD_WRITEABLE
;
109 parts
[RBSPI_PART_HCONF
].name
= "hard_config";
110 parts
[RBSPI_PART_HCONF
].offset
= info
->hard_cfg_offs
;
111 parts
[RBSPI_PART_HCONF
].size
= info
->hard_cfg_size
;
112 parts
[RBSPI_PART_HCONF
].mask_flags
= MTD_WRITEABLE
;
114 parts
[RBSPI_PART_BIOS
].name
= "bios";
115 parts
[RBSPI_PART_BIOS
].offset
= info
->hard_cfg_offs
116 + info
->hard_cfg_size
;
117 parts
[RBSPI_PART_BIOS
].size
= RB_BIOS_SIZE
;
118 parts
[RBSPI_PART_BIOS
].mask_flags
= MTD_WRITEABLE
;
120 parts
[RBSPI_PART_RBOOT2
].name
= "routerboot2";
121 parts
[RBSPI_PART_RBOOT2
].offset
= parts
[RBSPI_PART_BIOS
].offset
123 parts
[RBSPI_PART_RBOOT2
].size
= info
->soft_cfg_offs
124 - parts
[RBSPI_PART_RBOOT2
].offset
;
125 parts
[RBSPI_PART_RBOOT2
].mask_flags
= MTD_WRITEABLE
;
127 parts
[RBSPI_PART_SCONF
].name
= "soft_config";
128 parts
[RBSPI_PART_SCONF
].offset
= info
->soft_cfg_offs
;
129 parts
[RBSPI_PART_SCONF
].size
= RB_SOFT_CFG_SIZE
;
131 parts
[RBSPI_PART_FIRMW
].name
= "firmware";
132 parts
[RBSPI_PART_FIRMW
].offset
= parts
[RBSPI_PART_SCONF
].offset
133 + parts
[RBSPI_PART_SCONF
].size
;
134 parts
[RBSPI_PART_FIRMW
].size
= MTDPART_SIZ_FULL
;
137 static struct flash_platform_data rbspi_spi_flash_data
= {
138 .parts
= rbspi_spi_partitions
,
139 .nr_parts
= ARRAY_SIZE(rbspi_spi_partitions
),
143 * Several boards only have a single reset button, use a common
144 * structure for that.
146 static struct gpio_keys_button rbspi_gpio_keys_reset
[] __initdata
= {
148 .desc
= "Reset button",
151 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
152 .gpio
= -ENOENT
, /* filled dynamically */
157 /* RB mAP L-2nD gpios */
158 #define RBMAPL_GPIO_LED_POWER 17
159 #define RBMAPL_GPIO_LED_USER 14
160 #define RBMAPL_GPIO_LED_ETH 4
161 #define RBMAPL_GPIO_LED_WLAN 11
162 #define RBMAPL_GPIO_BTN_RESET 16
164 static struct gpio_led rbmapl_leds
[] __initdata
= {
166 .name
= "rb:green:power",
167 .gpio
= RBMAPL_GPIO_LED_POWER
,
169 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
171 .name
= "rb:green:user",
172 .gpio
= RBMAPL_GPIO_LED_USER
,
175 .name
= "rb:green:eth",
176 .gpio
= RBMAPL_GPIO_LED_ETH
,
179 .name
= "rb:green:wlan",
180 .gpio
= RBMAPL_GPIO_LED_WLAN
,
185 /* RB 941L-2nD gpios */
186 #define RBHAPL_GPIO_LED_USER 14
187 #define RBHAPL_GPIO_BTN_RESET 16
189 static struct gpio_led rbhapl_leds
[] __initdata
= {
191 .name
= "rb:green:user",
192 .gpio
= RBHAPL_GPIO_LED_USER
,
198 #define RBSPI_SSR_GPIO_BASE 40
199 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
201 /* RB 951Ui-2nD gpios */
202 #define RB952_SSR_BIT_LED_LAN1 0
203 #define RB952_SSR_BIT_LED_LAN2 1
204 #define RB952_SSR_BIT_LED_LAN3 2
205 #define RB952_SSR_BIT_LED_LAN4 3
206 #define RB952_SSR_BIT_LED_LAN5 4
207 #define RB952_SSR_BIT_USB_POWER 5
208 #define RB952_SSR_BIT_LED_WLAN 6
209 #define RB952_GPIO_SSR_CS 11
210 #define RB952_GPIO_LED_USER 4
211 #define RB952_GPIO_POE_POWER 14
212 #define RB952_GPIO_POE_STATUS 12
213 #define RB952_GPIO_BTN_RESET 16
214 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
215 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
216 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
217 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
218 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
219 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
220 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
222 static struct gpio_led rb952_leds
[] __initdata
= {
224 .name
= "rb:green:user",
225 .gpio
= RB952_GPIO_LED_USER
,
228 .name
= "rb:blue:wlan",
229 .gpio
= RB952_GPIO_LED_WLAN
,
232 .name
= "rb:green:port1",
233 .gpio
= RB952_GPIO_LED_LAN1
,
236 .name
= "rb:green:port2",
237 .gpio
= RB952_GPIO_LED_LAN2
,
240 .name
= "rb:green:port3",
241 .gpio
= RB952_GPIO_LED_LAN3
,
244 .name
= "rb:green:port4",
245 .gpio
= RB952_GPIO_LED_LAN4
,
248 .name
= "rb:green:port5",
249 .gpio
= RB952_GPIO_LED_LAN5
,
255 /* RB 962UiGS-5HacT2HnT gpios */
256 #define RB962_GPIO_POE_STATUS 2
257 #define RB962_GPIO_POE_POWER 3
258 #define RB962_GPIO_LED_USER 12
259 #define RB962_GPIO_USB_POWER 13
260 #define RB962_GPIO_BTN_RESET 20
262 static struct gpio_led rb962_leds_gpio
[] __initdata
= {
264 .name
= "rb:green:user",
265 .gpio
= RB962_GPIO_LED_USER
,
270 static const struct ar8327_led_info rb962_leds_ar8327
[] = {
271 AR8327_LED_INFO(PHY0_0
, HW
, "rb:green:port1"),
272 AR8327_LED_INFO(PHY1_0
, HW
, "rb:green:port2"),
273 AR8327_LED_INFO(PHY2_0
, HW
, "rb:green:port3"),
274 AR8327_LED_INFO(PHY3_0
, HW
, "rb:green:port4"),
275 AR8327_LED_INFO(PHY4_0
, HW
, "rb:green:port5"),
278 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg
= {
279 .mode
= AR8327_PAD_MAC_RGMII
,
280 .txclk_delay_en
= true,
281 .rxclk_delay_en
= true,
282 .txclk_delay_sel
= AR8327_CLK_DELAY_SEL1
,
283 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL2
,
284 .mac06_exchange_dis
= true,
287 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg
= {
288 /* Use SGMII interface for GMAC6 of the AR8337 switch */
289 .mode
= AR8327_PAD_MAC_SGMII
,
290 .rxclk_delay_en
= true,
291 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL0
,
294 static struct ar8327_led_cfg rb962_ar8327_led_cfg
= {
295 .led_ctrl0
= 0xc737c737,
296 .led_ctrl1
= 0x00000000,
297 .led_ctrl2
= 0x00000000,
298 .led_ctrl3
= 0x0030c300,
302 static struct ar8327_platform_data rb962_ar8327_data
= {
303 .pad0_cfg
= &rb962_ar8327_pad0_cfg
,
304 .pad6_cfg
= &rb962_ar8327_pad6_cfg
,
307 .speed
= AR8327_PORT_SPEED_1000
,
314 .speed
= AR8327_PORT_SPEED_1000
,
319 .led_cfg
= &rb962_ar8327_led_cfg
,
320 .num_leds
= ARRAY_SIZE(rb962_leds_ar8327
),
321 .leds
= rb962_leds_ar8327
,
324 static struct mdio_board_info rb962_mdio0_info
[] = {
326 .bus_id
= "ag71xx-mdio.0",
328 .platform_data
= &rb962_ar8327_data
,
332 /* RB wAP-2nD gpios */
333 #define RBWAP_GPIO_LED_USER 14
334 #define RBWAP_GPIO_LED_WLAN 11
335 #define RBWAP_GPIO_BTN_RESET 16
337 static struct gpio_led rbwap_leds
[] __initdata
= {
339 .name
= "rb:green:user",
340 .gpio
= RBWAP_GPIO_LED_USER
,
343 .name
= "rb:green:wlan",
344 .gpio
= RBWAP_GPIO_LED_WLAN
,
349 /* RB cAP-2nD gpios */
350 #define RBCAP_GPIO_LED_1 14
351 #define RBCAP_GPIO_LED_2 12
352 #define RBCAP_GPIO_LED_3 11
353 #define RBCAP_GPIO_LED_4 4
354 #define RBCAP_GPIO_LED_ALL 13
356 static struct gpio_led rbcap_leds
[] __initdata
= {
358 .name
= "rb:green:rssi1",
359 .gpio
= RBCAP_GPIO_LED_1
,
362 .name
= "rb:green:rssi2",
363 .gpio
= RBCAP_GPIO_LED_2
,
366 .name
= "rb:green:rssi3",
367 .gpio
= RBCAP_GPIO_LED_3
,
370 .name
= "rb:green:rssi4",
371 .gpio
= RBCAP_GPIO_LED_4
,
376 /* RB mAP-2nD gpios */
377 #define RBMAP_SSR_BIT_LED_LAN1 0
378 #define RBMAP_SSR_BIT_LED_LAN2 1
379 #define RBMAP_SSR_BIT_LED_POEO 2
380 #define RBMAP_SSR_BIT_LED_USER 3
381 #define RBMAP_SSR_BIT_LED_WLAN 4
382 #define RBMAP_SSR_BIT_USB_POWER 5
383 #define RBMAP_SSR_BIT_LED_APCAP 6
384 #define RBMAP_GPIO_BTN_RESET 16
385 #define RBMAP_GPIO_SSR_CS 11
386 #define RBMAP_GPIO_LED_POWER 4
387 #define RBMAP_GPIO_POE_POWER 14
388 #define RBMAP_GPIO_POE_STATUS 12
389 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
390 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
391 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
392 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
393 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
394 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
395 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
397 static struct gpio_led rbmap_leds
[] __initdata
= {
399 .name
= "rb:green:power",
400 .gpio
= RBMAP_GPIO_LED_POWER
,
402 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
404 .name
= "rb:green:eth1",
405 .gpio
= RBMAP_GPIO_LED_LAN1
,
408 .name
= "rb:green:eth2",
409 .gpio
= RBMAP_GPIO_LED_LAN2
,
412 .name
= "rb:red:poe_out",
413 .gpio
= RBMAP_GPIO_LED_POEO
,
416 .name
= "rb:green:user",
417 .gpio
= RBMAP_GPIO_LED_USER
,
420 .name
= "rb:green:wlan",
421 .gpio
= RBMAP_GPIO_LED_WLAN
,
424 .name
= "rb:green:ap_cap",
425 .gpio
= RBMAP_GPIO_LED_APCAP
,
430 /* RB LHG 5nD gpios */
431 #define RBLHG_GPIO_LED_0 13
432 #define RBLHG_GPIO_LED_1 12
433 #define RBLHG_GPIO_LED_2 4
434 #define RBLHG_GPIO_LED_3 21
435 #define RBLHG_GPIO_LED_4 18
436 #define RBLHG_GPIO_LED_ETH 14
437 #define RBLHG_GPIO_LED_POWER 11
438 #define RBLHG_GPIO_LED_USER 20
439 #define RBLHG_GPIO_BTN_RESET 15
441 static struct gpio_led rblhg_leds
[] __initdata
= {
443 .name
= "rb:green:rssi0",
444 .gpio
= RBLHG_GPIO_LED_0
,
447 .name
= "rb:green:rssi1",
448 .gpio
= RBLHG_GPIO_LED_1
,
451 .name
= "rb:green:rssi2",
452 .gpio
= RBLHG_GPIO_LED_2
,
455 .name
= "rb:green:rssi3",
456 .gpio
= RBLHG_GPIO_LED_3
,
459 .name
= "rb:green:rssi4",
460 .gpio
= RBLHG_GPIO_LED_4
,
463 .name
= "rb:green:eth",
464 .gpio
= RBLHG_GPIO_LED_ETH
,
467 .name
= "rb:green:user",
468 .gpio
= RBLHG_GPIO_LED_USER
,
471 .name
= "rb:blue:power",
472 .gpio
= RBLHG_GPIO_LED_POWER
,
474 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
478 /* RB w APG-5HacT2HnD (wAP AC) gpios*/
479 #define RBWAPGSC_LED1 1
480 #define RBWAPGSC_LED2 8
481 #define RBWAPGSC_LED3 9
482 #define RBWAPGSC_POWERLED 16
483 #define RBWAPGSC_GPIO_BTN_RESET 1
484 #define RBWAPGSC_GPIO_MDIO_MDC 12
485 #define RBWAPGSC_GPIO_MDIO_DATA 11
486 #define RBWAPGSC_MDIO_PHYADDR 0
488 static struct gpio_led rbwapgsc_leds
[] __initdata
= {
490 .name
= "rb:green:led1",
491 .gpio
= RBWAPGSC_LED1
,
494 .name
= "rb:blue:power",
495 .gpio
= RBWAPGSC_POWERLED
,
500 static struct mdio_gpio_platform_data rbwapgsc_mdio_data
= {
501 .mdc
= RBWAPGSC_GPIO_MDIO_MDC
,
502 .mdio
= RBWAPGSC_GPIO_MDIO_DATA
,
503 .phy_mask
= ~BIT(RBWAPGSC_MDIO_PHYADDR
),
506 static struct platform_device rbwapgsc_phy_device
= {
510 .platform_data
= &rbwapgsc_mdio_data
515 #define RB911L_GPIO_BTN_RESET 15
516 #define RB911L_GPIO_LED_1 13
517 #define RB911L_GPIO_LED_2 12
518 #define RB911L_GPIO_LED_3 4
519 #define RB911L_GPIO_LED_4 21
520 #define RB911L_GPIO_LED_5 18
521 #define RB911L_GPIO_LED_ETH 20
522 #define RB911L_GPIO_LED_POWER 11
523 #define RB911L_GPIO_LED_USER 3
524 #define RB911L_GPIO_PIN_HOLE 14 /* for reference */
526 static struct gpio_led rb911l_leds
[] __initdata
= {
528 .name
= "rb:green:eth",
529 .gpio
= RB911L_GPIO_LED_ETH
,
532 .name
= "rb:green:led1",
533 .gpio
= RB911L_GPIO_LED_1
,
536 .name
= "rb:green:led2",
537 .gpio
= RB911L_GPIO_LED_2
,
540 .name
= "rb:green:led3",
541 .gpio
= RB911L_GPIO_LED_3
,
544 .name
= "rb:green:led4",
545 .gpio
= RB911L_GPIO_LED_4
,
548 .name
= "rb:green:led5",
549 .gpio
= RB911L_GPIO_LED_5
,
552 .name
= "rb:green:power",
553 .gpio
= RB911L_GPIO_LED_POWER
,
554 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
557 .name
= "rb:green:user",
558 .gpio
= RB911L_GPIO_LED_USER
,
564 static struct gen_74x164_chip_platform_data rbspi_ssr_data
= {
565 .base
= RBSPI_SSR_GPIO_BASE
,
569 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
570 static int rbspi_spi_cs_gpios
[] = {
571 -ENOENT
, /* CS0 is always -ENOENT: natively handled */
572 -ENOENT
, /* CS1 can be updated by the code as necessary */
575 static struct ath79_spi_platform_data rbspi_ath79_spi_data
= {
577 .cs_gpios
= rbspi_spi_cs_gpios
,
581 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
582 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
584 static struct spi_board_info rbspi_spi_info
[] = {
588 .max_speed_hz
= 25000000,
589 .modalias
= "m25p80",
590 .platform_data
= &rbspi_spi_flash_data
,
594 .max_speed_hz
= 25000000,
595 .modalias
= "74x164",
596 .platform_data
= &rbspi_ssr_data
,
600 void __init
rbspi_wlan_init(u16 id
, int wmac_offset
)
603 u8 wlan_mac
[ETH_ALEN
];
605 art_buf
= rb_get_ext_wlan_data(id
);
609 ath79_init_mac(wlan_mac
, ath79_mac_base
, wmac_offset
);
610 ath79_register_wmac(art_buf
+ 0x1000, wlan_mac
);
615 #define RBSPI_MACH_BUFLEN 64
617 * Common platform init routine for all SPI NOR devices.
619 static __init
const struct rb_info
*rbspi_platform_setup(void)
621 const struct rb_info
*info
;
622 char buf
[RBSPI_MACH_BUFLEN
] = "MikroTik ";
624 int len
= RBSPI_MACH_BUFLEN
- strlen(buf
) - 1;
626 info
= rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE
)), 0x20000);
630 if (info
->board_name
) {
631 str
= "RouterBOARD ";
632 if (strncmp(info
->board_name
, str
, strlen(str
))) {
633 strncat(buf
, str
, len
);
636 strncat(buf
, info
->board_name
, len
);
639 strncat(buf
, "UNKNOWN", len
);
641 mips_set_machine_name(buf
);
643 /* fix partitions based on flash parsing */
644 rbspi_init_partitions(info
);
650 * Common peripherals init routine for all SPI NOR devices.
653 static void __init
rbspi_peripherals_setup(u32 flags
)
657 if (flags
& RBSPI_HAS_SSR
)
658 spi_n
= ARRAY_SIZE(rbspi_spi_info
);
660 spi_n
= 1; /* only one device on bus0 */
662 rbspi_ath79_spi_data
.num_chipselect
= spi_n
;
663 rbspi_ath79_spi_data
.cs_gpios
= rbspi_spi_cs_gpios
;
664 ath79_register_spi(&rbspi_ath79_spi_data
, rbspi_spi_info
, spi_n
);
666 if (flags
& RBSPI_HAS_USB
)
667 ath79_register_usb();
669 if (flags
& RBSPI_HAS_PCI
)
670 ath79_register_pci();
674 * Common network init routine for all SPI NOR devices.
677 static void __init
rbspi_network_setup(u32 flags
, int gmac1_offset
,
678 int wmac0_offset
, int wmac1_offset
)
680 /* for QCA953x that will init mdio1_device/data */
681 ath79_register_mdio(0, 0x0);
682 if (flags
& RBSPI_HAS_MDIO1
)
683 ath79_register_mdio(1, 0x0);
685 if (flags
& RBSPI_HAS_WAN4
) {
686 ath79_setup_ar934x_eth_cfg(0);
688 /* set switch to oper mode 1, PHY4 connected to CPU */
689 ath79_switch_data
.phy4_mii_en
= 1;
690 ath79_switch_data
.phy_poll_mask
|= BIT(4);
692 /* init GMAC0 connected to PHY4 at 100M */
693 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
694 ath79_eth0_data
.phy_mask
= BIT(4);
695 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
696 ath79_register_eth(0);
698 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
699 * to the internal switch.
700 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
701 * the QCA953x, this works because this configuration bit is
702 * the same as the AR934x. There's no equivalent function for
703 * QCA953x for now. */
704 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE
);
708 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, gmac1_offset
);
709 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
710 ath79_register_eth(1);
712 if (flags
& RBSPI_HAS_WLAN0
)
713 rbspi_wlan_init(0, wmac0_offset
);
715 if (flags
& RBSPI_HAS_WLAN1
)
716 rbspi_wlan_init(1, wmac1_offset
);
719 static __init
void rbspi_register_reset_button(int gpio
)
721 rbspi_gpio_keys_reset
[0].gpio
= gpio
;
722 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
723 ARRAY_SIZE(rbspi_gpio_keys_reset
),
724 rbspi_gpio_keys_reset
);
728 * Init the mAP lite hardware (QCA953x).
729 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
730 * Trying to use GMAC0 in direct mode was unsucessful, so we're
731 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
732 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
734 static void __init
rbmapl_setup(void)
736 u32 flags
= RBSPI_HAS_WLAN0
;
738 if (!rbspi_platform_setup())
741 rbspi_peripherals_setup(flags
);
743 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
744 rbspi_network_setup(flags
, 0, 1, 0);
746 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds
), rbmapl_leds
);
748 /* mAP lite has a single reset button as gpio 16 */
749 rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET
);
751 /* clear internal multiplexing */
752 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
753 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER
, AR934X_GPIO_OUT_GPIO
);
757 * Init the hAP lite hardware (QCA953x).
758 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
759 * being assigned to LAN on the casing, and port 1 being assigned
760 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
761 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
763 static void __init
rbhapl_setup(void)
765 u32 flags
= RBSPI_HAS_WLAN0
;
767 if (!rbspi_platform_setup())
770 rbspi_peripherals_setup(flags
);
772 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
773 rbspi_network_setup(flags
, 0, 4, 0);
775 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds
), rbhapl_leds
);
777 /* hAP lite has a single reset button as gpio 16 */
778 rbspi_register_reset_button(RBHAPL_GPIO_BTN_RESET
);
782 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
784 static void __init
rbspi_952_750r2_setup(u32 flags
)
786 if (flags
& RBSPI_HAS_SSR
)
787 rbspi_spi_cs_gpios
[1] = RB952_GPIO_SSR_CS
;
789 rbspi_peripherals_setup(flags
);
792 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
793 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
795 rbspi_network_setup(flags
, 1, 5, 6);
797 if (flags
& RBSPI_HAS_USB
)
798 gpio_request_one(RB952_GPIO_USB_POWER
,
799 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
802 if (flags
& RBSPI_HAS_POE
)
803 gpio_request_one(RB952_GPIO_POE_POWER
,
804 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
807 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds
), rb952_leds
);
809 /* These devices have a single reset button as gpio 16 */
810 rbspi_register_reset_button(RB952_GPIO_BTN_RESET
);
814 * Init the hAP (ac lite) hardware (QCA953x).
815 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
816 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
817 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
818 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
819 * internal switch for the LAN ports.
820 * The device also has USB, PoE output and an SSR used for LED multiplexing.
821 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
822 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
824 static void __init
rb952_setup(void)
826 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_USB
|
827 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
829 if (!rbspi_platform_setup())
832 /* differentiate the hAP from the hAP ac lite */
833 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
834 flags
|= RBSPI_HAS_WLAN1
| RBSPI_HAS_PCI
;
836 flags
|= RBSPI_HAS_WLAN0
;
838 rbspi_952_750r2_setup(flags
);
842 * Init the hEX (PoE) lite hardware (QCA953x).
843 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
844 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
845 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
846 * lite, only without USB. It shares the same bootloader board identifier.
848 static void __init
rb750upr2_setup(void)
850 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_SSR
;
852 if (!rbspi_platform_setup())
855 /* differentiate the hEX lite from the hEX PoE lite */
856 if (strstr(mips_get_machine_name(), "750UP r2"))
857 flags
|= RBSPI_HAS_USB
| RBSPI_HAS_POE
;
859 /* differentiate the Powerbox from the hEX lite */
860 else if (strstr(mips_get_machine_name(), "750P r2"))
861 flags
|= RBSPI_HAS_POE
;
863 rbspi_952_750r2_setup(flags
);
867 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
868 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
869 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
870 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
871 * The SFP cage is not assigned by default on RouterOS. Extra work is required
872 * to support this interface as it is directly connected to the SoC (eth1).
873 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
874 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
875 * they are not attached to GPIOs, extra work is required to support these.
876 * PoE and USB output power control is supported.
878 static void __init
rb962_setup(void)
880 u32 flags
= RBSPI_HAS_USB
| RBSPI_HAS_POE
| RBSPI_HAS_PCI
;
882 if (!rbspi_platform_setup())
885 rbspi_peripherals_setup(flags
);
887 /* Do not call rbspi_network_setup as we have a discrete switch chip */
888 ath79_eth0_pll_data
.pll_1000
= 0xae000000;
889 ath79_eth0_pll_data
.pll_100
= 0xa0000101;
890 ath79_eth0_pll_data
.pll_10
= 0xa0001313;
892 ath79_register_mdio(0, 0x0);
893 mdiobus_register_board_info(rb962_mdio0_info
,
894 ARRAY_SIZE(rb962_mdio0_info
));
896 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN
);
898 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
899 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
900 ath79_eth0_data
.phy_mask
= BIT(0);
901 ath79_eth0_data
.mii_bus_dev
= &ath79_mdio0_device
.dev
;
902 ath79_register_eth(0);
904 /* WLAN1 MAC is HW MAC + 7 */
905 rbspi_wlan_init(1, 7);
907 if (flags
& RBSPI_HAS_USB
)
908 gpio_request_one(RB962_GPIO_USB_POWER
,
909 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
912 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
913 if (flags
& RBSPI_HAS_POE
)
914 gpio_request_one(RB962_GPIO_POE_POWER
,
915 GPIOF_OUT_INIT_HIGH
| GPIOF_ACTIVE_LOW
|
916 GPIOF_EXPORT_DIR_FIXED
,
919 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio
),
922 /* This device has a single reset button as gpio 20 */
923 rbspi_register_reset_button(RB962_GPIO_BTN_RESET
);
927 * Init the LHG hardware (AR9344).
928 * The LHG 5nD has a single ethernet port connected to PHY0.
929 * Wireless is provided via 5GHz WLAN1.
931 static void __init
rblhg_setup(void)
933 u32 flags
= RBSPI_HAS_WLAN1
| RBSPI_HAS_MDIO1
;
935 if (!rbspi_platform_setup())
938 rbspi_peripherals_setup(flags
);
940 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
941 rbspi_network_setup(flags
, 0, 0, 1);
943 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds
), rblhg_leds
);
945 rbspi_register_reset_button(RBLHG_GPIO_BTN_RESET
);
949 * Init the wAP hardware.
950 * The wAP 2nD has a single ethernet port.
952 static void __init
rbwap_setup(void)
954 u32 flags
= RBSPI_HAS_WLAN0
;
956 if (!rbspi_platform_setup())
959 rbspi_peripherals_setup(flags
);
961 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
962 rbspi_network_setup(flags
, 0, 1, 0);
964 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds
), rbwap_leds
);
966 /* wAP has a single reset button as GPIO 16 */
967 rbspi_register_reset_button(RBWAP_GPIO_BTN_RESET
);
971 * Init the cAP hardware (EXPERIMENTAL).
972 * The cAP 2nD has a single ethernet port, and a global LED switch.
974 static void __init
rbcap_setup(void)
976 u32 flags
= RBSPI_HAS_WLAN0
;
978 if (!rbspi_platform_setup())
981 rbspi_peripherals_setup(flags
);
983 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
984 rbspi_network_setup(flags
, 0, 1, 0);
986 gpio_request_one(RBCAP_GPIO_LED_ALL
,
987 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
990 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds
), rbcap_leds
);
994 * Init the mAP hardware.
995 * The mAP 2nD has two ethernet ports, PoE output, SSR for LED
996 * multiplexing and USB port.
998 static void __init
rbmap_setup(void)
1000 u32 flags
= RBSPI_HAS_USB
| RBSPI_HAS_WLAN0
|
1001 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
1003 if (!rbspi_platform_setup())
1006 rbspi_spi_cs_gpios
[1] = RBMAP_GPIO_SSR_CS
;
1007 rbspi_peripherals_setup(flags
);
1009 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
1010 rbspi_network_setup(flags
, 0, 2, 0);
1012 if (flags
& RBSPI_HAS_POE
)
1013 gpio_request_one(RBMAP_GPIO_POE_POWER
,
1014 GPIOF_OUT_INIT_LOW
| GPIOF_EXPORT_DIR_FIXED
,
1017 /* USB power GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
1018 if (flags
& RBSPI_HAS_USB
)
1019 gpio_request_one(RBMAP_GPIO_USB_POWER
,
1020 GPIOF_OUT_INIT_HIGH
| GPIOF_ACTIVE_LOW
|
1021 GPIOF_EXPORT_DIR_FIXED
,
1024 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds
), rbmap_leds
);
1026 /* mAP 2nD has a single reset button as gpio 16 */
1027 rbspi_register_reset_button(RBMAP_GPIO_BTN_RESET
);
1031 * Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware.
1032 * The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC
1033 * 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor
1034 * (currently not supported).
1036 static void __init
rbwapgsc_setup(void)
1038 u32 flags
= RBSPI_HAS_PCI
;
1040 if (!rbspi_platform_setup())
1043 rbspi_peripherals_setup(flags
);
1045 platform_device_register(&rbwapgsc_phy_device
);
1047 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
1048 ath79_eth1_data
.mii_bus_dev
= &rbwapgsc_phy_device
.dev
;
1049 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_SGMII
;
1050 ath79_eth1_data
.phy_mask
= BIT(RBWAPGSC_MDIO_PHYADDR
);
1051 ath79_eth1_pll_data
.pll_1000
= 0x03000101;
1052 ath79_eth1_pll_data
.pll_100
= 0x80000101;
1053 ath79_eth1_pll_data
.pll_10
= 0x80001313;
1054 ath79_eth1_data
.speed
= SPEED_1000
;
1055 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
1056 ath79_register_eth(1);
1058 rbspi_wlan_init(1, 2);
1060 rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET
);
1062 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE
|
1063 QCA955X_GPIO_REG_OUT_FUNC4
|
1064 QCA955X_GPIO_REG_OUT_FUNC3
);
1066 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds
),
1071 * Setup the 911L hardware (AR9344).
1073 static void __init
rb911l_setup(void)
1075 const struct rb_info
*info
;
1077 info
= rbspi_platform_setup();
1081 if (!rb_has_hw_option(info
, RB_HW_OPT_NO_NAND
)) {
1083 * Old hardware revisions might be equipped with a NAND flash
1084 * chip instead of the 16MiB SPI NOR device. Those boards are
1085 * not supported at the moment, so throw a warning and skip
1086 * the peripheral setup to avoid messing up the data in the
1089 WARN(1, "The NAND flash on this board is not supported.\n");
1091 rbspi_peripherals_setup(0);
1094 ath79_register_mdio(1, 0x0);
1096 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
1098 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
1099 ath79_eth1_data
.speed
= SPEED_1000
;
1100 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
1102 ath79_register_eth(1);
1104 rbspi_wlan_init(0, 1);
1106 rbspi_register_reset_button(RB911L_GPIO_BTN_RESET
);
1108 /* Make the eth LED controllable by software. */
1109 ath79_gpio_output_select(RB911L_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
1111 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb911l_leds
), rb911l_leds
);
1114 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL
, "map-hb", rbmapl_setup
);
1115 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941
, "H951L", rbhapl_setup
);
1116 MIPS_MACHINE_NONAME(ATH79_MACH_RB_911L
, "911L", rb911l_setup
);
1117 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952
, "952-hb", rb952_setup
);
1118 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962
, "962", rb962_setup
);
1119 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2
, "750-hb", rb750upr2_setup
);
1120 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5
, "lhg", rblhg_setup
);
1121 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP
, "wap-hb", rbwap_setup
);
1122 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP
, "cap-hb", rbcap_setup
);
1123 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP
, "map2-hb", rbmap_setup
);
1124 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPAC
, "wapg-sc", rbwapgsc_setup
);