2 * MikroTik SPI-NOR RouterBOARDs support
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 952Ui-5ac2nD
8 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
9 * - MikroTik RouterBOARD 750UP r2
10 * - MikroTik RouterBOARD 750P-PBr2
11 * - MikroTik RouterBOARD 750 r2
12 * - MikroTik RouterBOARD LHG 5nD
14 * Preliminary support for the following hardware
15 * - MikroTik RouterBOARD wAP2nD
16 * - MikroTik RouterBOARD cAP2nD
17 * - MikroTik RouterBOARD mAP2nD
18 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
19 * hardware as the mAP L-2nD. It is unknown if they share the same board
22 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
23 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
24 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License version 2 as published
28 * by the Free Software Foundation.
31 #include <linux/pci.h>
32 #include <linux/platform_device.h>
33 #include <linux/phy.h>
34 #include <linux/routerboot.h>
35 #include <linux/gpio.h>
37 #include <linux/spi/spi.h>
38 #include <linux/spi/74x164.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/partitions.h>
43 #include <linux/ar8216_platform.h>
46 #include <asm/mach-ath79/ar71xx_regs.h>
47 #include <asm/mach-ath79/ath79.h>
52 #include "dev-gpio-buttons.h"
53 #include "dev-leds-gpio.h"
54 #include "dev-m25p80.h"
57 #include "machtypes.h"
59 #include "routerboot.h"
61 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
62 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
64 #define RBSPI_HAS_USB BIT(0)
65 #define RBSPI_HAS_WLAN0 BIT(1)
66 #define RBSPI_HAS_WLAN1 BIT(2)
67 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
68 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
69 #define RBSPI_HAS_POE BIT(5)
70 #define RBSPI_HAS_MDIO1 BIT(6)
71 #define RBSPI_HAS_PCI BIT(7)
73 #define RB_ROUTERBOOT_OFFSET 0x0000
74 #define RB_BIOS_SIZE 0x1000
75 #define RB_SOFT_CFG_SIZE 0x1000
77 /* Flash partitions indexes */
88 static struct mtd_partition rbspi_spi_partitions
[RBSPI_PARTS
];
91 * Setup the SPI flash partition table based on initial parsing.
92 * The kernel can be at any aligned position and have any size.
94 static void __init
rbspi_init_partitions(const struct rb_info
*info
)
96 struct mtd_partition
*parts
= rbspi_spi_partitions
;
97 memset(parts
, 0x0, sizeof(*parts
));
99 parts
[RBSPI_PART_RBOOT
].name
= "routerboot";
100 parts
[RBSPI_PART_RBOOT
].offset
= RB_ROUTERBOOT_OFFSET
;
101 parts
[RBSPI_PART_RBOOT
].size
= info
->hard_cfg_offs
;
102 parts
[RBSPI_PART_RBOOT
].mask_flags
= MTD_WRITEABLE
;
104 parts
[RBSPI_PART_HCONF
].name
= "hard_config";
105 parts
[RBSPI_PART_HCONF
].offset
= info
->hard_cfg_offs
;
106 parts
[RBSPI_PART_HCONF
].size
= info
->hard_cfg_size
;
107 parts
[RBSPI_PART_HCONF
].mask_flags
= MTD_WRITEABLE
;
109 parts
[RBSPI_PART_BIOS
].name
= "bios";
110 parts
[RBSPI_PART_BIOS
].offset
= info
->hard_cfg_offs
111 + info
->hard_cfg_size
;
112 parts
[RBSPI_PART_BIOS
].size
= RB_BIOS_SIZE
;
113 parts
[RBSPI_PART_BIOS
].mask_flags
= MTD_WRITEABLE
;
115 parts
[RBSPI_PART_RBOOT2
].name
= "routerboot2";
116 parts
[RBSPI_PART_RBOOT2
].offset
= parts
[RBSPI_PART_BIOS
].offset
118 parts
[RBSPI_PART_RBOOT2
].size
= info
->soft_cfg_offs
119 - parts
[RBSPI_PART_RBOOT2
].offset
;
120 parts
[RBSPI_PART_RBOOT2
].mask_flags
= MTD_WRITEABLE
;
122 parts
[RBSPI_PART_SCONF
].name
= "soft_config";
123 parts
[RBSPI_PART_SCONF
].offset
= info
->soft_cfg_offs
;
124 parts
[RBSPI_PART_SCONF
].size
= RB_SOFT_CFG_SIZE
;
126 parts
[RBSPI_PART_FIRMW
].name
= "firmware";
127 parts
[RBSPI_PART_FIRMW
].offset
= parts
[RBSPI_PART_SCONF
].offset
128 + parts
[RBSPI_PART_SCONF
].size
;
129 parts
[RBSPI_PART_FIRMW
].size
= MTDPART_SIZ_FULL
;
132 static struct flash_platform_data rbspi_spi_flash_data
= {
133 .parts
= rbspi_spi_partitions
,
134 .nr_parts
= ARRAY_SIZE(rbspi_spi_partitions
),
137 /* Several boards only have a single reset button wired to GPIO 16 */
138 #define RBSPI_GPIO_BTN_RESET16 16
139 #define RBSPI_GPIO_BTN_RESET20 20
141 static struct gpio_keys_button rbspi_gpio_keys_reset16
[] __initdata
= {
143 .desc
= "Reset button",
146 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
147 .gpio
= RBSPI_GPIO_BTN_RESET16
,
152 static struct gpio_keys_button rbspi_gpio_keys_reset20
[] __initdata
= {
154 .desc
= "Reset button",
157 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
158 .gpio
= RBSPI_GPIO_BTN_RESET20
,
163 /* RB mAP L-2nD gpios */
164 #define RBMAPL_GPIO_LED_POWER 17
165 #define RBMAPL_GPIO_LED_USER 14
166 #define RBMAPL_GPIO_LED_ETH 4
167 #define RBMAPL_GPIO_LED_WLAN 11
169 static struct gpio_led rbmapl_leds
[] __initdata
= {
171 .name
= "rb:green:power",
172 .gpio
= RBMAPL_GPIO_LED_POWER
,
174 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
176 .name
= "rb:green:user",
177 .gpio
= RBMAPL_GPIO_LED_USER
,
180 .name
= "rb:green:eth",
181 .gpio
= RBMAPL_GPIO_LED_ETH
,
184 .name
= "rb:green:wlan",
185 .gpio
= RBMAPL_GPIO_LED_WLAN
,
190 /* RB 941L-2nD gpios */
191 #define RBHAPL_GPIO_LED_USER 14
192 static struct gpio_led rbhapl_leds
[] __initdata
= {
194 .name
= "rb:green:user",
195 .gpio
= RBHAPL_GPIO_LED_USER
,
201 #define RBSPI_SSR_GPIO_BASE 40
202 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
204 /* RB 951Ui-2nD gpios */
205 #define RB952_SSR_BIT_LED_LAN1 0
206 #define RB952_SSR_BIT_LED_LAN2 1
207 #define RB952_SSR_BIT_LED_LAN3 2
208 #define RB952_SSR_BIT_LED_LAN4 3
209 #define RB952_SSR_BIT_LED_LAN5 4
210 #define RB952_SSR_BIT_USB_POWER 5
211 #define RB952_SSR_BIT_LED_WLAN 6
212 #define RB952_GPIO_SSR_CS 11
213 #define RB952_GPIO_LED_USER 4
214 #define RB952_GPIO_POE_POWER 14
215 #define RB952_GPIO_POE_STATUS 12
216 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
217 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
218 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
219 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
220 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
221 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
222 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
224 static struct gpio_led rb952_leds
[] __initdata
= {
226 .name
= "rb:green:user",
227 .gpio
= RB952_GPIO_LED_USER
,
230 .name
= "rb:blue:wlan",
231 .gpio
= RB952_GPIO_LED_WLAN
,
234 .name
= "rb:green:port1",
235 .gpio
= RB952_GPIO_LED_LAN1
,
238 .name
= "rb:green:port2",
239 .gpio
= RB952_GPIO_LED_LAN2
,
242 .name
= "rb:green:port3",
243 .gpio
= RB952_GPIO_LED_LAN3
,
246 .name
= "rb:green:port4",
247 .gpio
= RB952_GPIO_LED_LAN4
,
250 .name
= "rb:green:port5",
251 .gpio
= RB952_GPIO_LED_LAN5
,
257 /* RB 962UiGS-5HacT2HnT gpios */
258 #define RB962_GPIO_POE_STATUS 2
259 #define RB962_GPIO_POE_POWER 3
260 #define RB962_GPIO_LED_USER 12
261 #define RB962_GPIO_USB_POWER 13
263 static struct gpio_led rb962_leds_gpio
[] __initdata
= {
265 .name
= "rb:green:user",
266 .gpio
= RB962_GPIO_LED_USER
,
271 static const struct ar8327_led_info rb962_leds_ar8327
[] = {
272 AR8327_LED_INFO(PHY0_0
, HW
, "rb:green:port1"),
273 AR8327_LED_INFO(PHY1_0
, HW
, "rb:green:port2"),
274 AR8327_LED_INFO(PHY2_0
, HW
, "rb:green:port3"),
275 AR8327_LED_INFO(PHY3_0
, HW
, "rb:green:port4"),
276 AR8327_LED_INFO(PHY4_0
, HW
, "rb:green:port5"),
279 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg
= {
280 .mode
= AR8327_PAD_MAC_RGMII
,
281 .txclk_delay_en
= true,
282 .rxclk_delay_en
= true,
283 .txclk_delay_sel
= AR8327_CLK_DELAY_SEL1
,
284 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL2
,
285 .mac06_exchange_dis
= true,
288 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg
= {
289 /* Use SGMII interface for GMAC6 of the AR8337 switch */
290 .mode
= AR8327_PAD_MAC_SGMII
,
291 .rxclk_delay_en
= true,
292 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL0
,
295 static struct ar8327_led_cfg rb962_ar8327_led_cfg
= {
296 .led_ctrl0
= 0xc737c737,
297 .led_ctrl1
= 0x00000000,
298 .led_ctrl2
= 0x00000000,
299 .led_ctrl3
= 0x0030c300,
303 static struct ar8327_platform_data rb962_ar8327_data
= {
304 .pad0_cfg
= &rb962_ar8327_pad0_cfg
,
305 .pad6_cfg
= &rb962_ar8327_pad6_cfg
,
308 .speed
= AR8327_PORT_SPEED_1000
,
315 .speed
= AR8327_PORT_SPEED_1000
,
320 .led_cfg
= &rb962_ar8327_led_cfg
,
321 .num_leds
= ARRAY_SIZE(rb962_leds_ar8327
),
322 .leds
= rb962_leds_ar8327
,
325 static struct mdio_board_info rb962_mdio0_info
[] = {
327 .bus_id
= "ag71xx-mdio.0",
329 .platform_data
= &rb962_ar8327_data
,
333 /* RB wAP-2nD gpios */
334 #define RBWAP_GPIO_LED_USER 14
335 #define RBWAP_GPIO_LED_WLAN 11
337 static struct gpio_led rbwap_leds
[] __initdata
= {
339 .name
= "rb:green:user",
340 .gpio
= RBWAP_GPIO_LED_USER
,
343 .name
= "rb:green:wlan",
344 .gpio
= RBWAP_GPIO_LED_WLAN
,
349 /* RB cAP-2nD gpios */
350 #define RBCAP_GPIO_LED_1 14
351 #define RBCAP_GPIO_LED_2 12
352 #define RBCAP_GPIO_LED_3 11
353 #define RBCAP_GPIO_LED_4 4
354 #define RBCAP_GPIO_LED_ALL 13
356 static struct gpio_led rbcap_leds
[] __initdata
= {
358 .name
= "rb:green:rssi1",
359 .gpio
= RBCAP_GPIO_LED_1
,
362 .name
= "rb:green:rssi2",
363 .gpio
= RBCAP_GPIO_LED_2
,
366 .name
= "rb:green:rssi3",
367 .gpio
= RBCAP_GPIO_LED_3
,
370 .name
= "rb:green:rssi4",
371 .gpio
= RBCAP_GPIO_LED_4
,
376 /* RB mAP-2nD gpios */
377 #define RBMAP_SSR_BIT_LED_LAN1 0
378 #define RBMAP_SSR_BIT_LED_LAN2 1
379 #define RBMAP_SSR_BIT_LED_POEO 2
380 #define RBMAP_SSR_BIT_LED_USER 3
381 #define RBMAP_SSR_BIT_LED_WLAN 4
382 #define RBMAP_SSR_BIT_USB_POWER 5
383 #define RBMAP_SSR_BIT_LED_APCAP 6
384 #define RBMAP_GPIO_SSR_CS 11
385 #define RBMAP_GPIO_LED_POWER 4
386 #define RBMAP_GPIO_POE_POWER 14
387 #define RBMAP_GPIO_POE_STATUS 12
388 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
389 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
390 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
391 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
392 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
393 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
394 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
396 static struct gpio_led rbmap_leds
[] __initdata
= {
398 .name
= "rb:green:power",
399 .gpio
= RBMAP_GPIO_LED_POWER
,
401 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
403 .name
= "rb:green:eth1",
404 .gpio
= RBMAP_GPIO_LED_LAN1
,
407 .name
= "rb:green:eth2",
408 .gpio
= RBMAP_GPIO_LED_WLAN
,
411 .name
= "rb:red:poe_out",
412 .gpio
= RBMAP_GPIO_LED_POEO
,
415 .name
= "rb:green:user",
416 .gpio
= RBMAP_GPIO_LED_USER
,
419 .name
= "rb:green:wlan",
420 .gpio
= RBMAP_GPIO_LED_WLAN
,
423 .name
= "rb:green:ap_cap",
424 .gpio
= RBMAP_GPIO_LED_APCAP
,
429 /* RB LHG 5nD gpios */
430 #define RBLHG_GPIO_LED_0 13
431 #define RBLHG_GPIO_LED_1 12
432 #define RBLHG_GPIO_LED_2 4
433 #define RBLHG_GPIO_LED_3 21
434 #define RBLHG_GPIO_LED_4 18
435 #define RBLHG_GPIO_LED_ETH 14
436 #define RBLHG_GPIO_LED_POWER 11
437 #define RBLHG_GPIO_LED_USER 20
438 #define RBLHG_GPIO_BTN_RESET 15
440 static struct gpio_led rblhg_leds
[] __initdata
= {
442 .name
= "rb:green:rssi0",
443 .gpio
= RBLHG_GPIO_LED_0
,
446 .name
= "rb:green:rssi1",
447 .gpio
= RBLHG_GPIO_LED_1
,
450 .name
= "rb:green:rssi2",
451 .gpio
= RBLHG_GPIO_LED_2
,
454 .name
= "rb:green:rssi3",
455 .gpio
= RBLHG_GPIO_LED_3
,
458 .name
= "rb:green:rssi4",
459 .gpio
= RBLHG_GPIO_LED_4
,
462 .name
= "rb:green:eth",
463 .gpio
= RBLHG_GPIO_LED_ETH
,
466 .name
= "rb:green:user",
467 .gpio
= RBLHG_GPIO_LED_USER
,
470 .name
= "rb:blue:power",
471 .gpio
= RBLHG_GPIO_LED_POWER
,
473 .default_state
= LEDS_GPIO_DEFSTATE_ON
,
477 static struct gpio_keys_button rblhg_gpio_keys
[] __initdata
= {
479 .desc
= "Reset button",
482 .debounce_interval
= RBSPI_KEYS_DEBOUNCE_INTERVAL
,
483 .gpio
= RBLHG_GPIO_BTN_RESET
,
489 static struct gen_74x164_chip_platform_data rbspi_ssr_data
= {
490 .base
= RBSPI_SSR_GPIO_BASE
,
493 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
494 static int rbspi_spi_cs_gpios
[] = {
495 -ENOENT
, /* CS0 is always -ENOENT: natively handled */
496 -ENOENT
, /* CS1 can be updated by the code as necessary */
499 static struct ath79_spi_platform_data rbspi_ath79_spi_data
= {
501 .cs_gpios
= rbspi_spi_cs_gpios
,
505 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
506 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
508 static struct spi_board_info rbspi_spi_info
[] = {
512 .max_speed_hz
= 25000000,
513 .modalias
= "m25p80",
514 .platform_data
= &rbspi_spi_flash_data
,
518 .max_speed_hz
= 25000000,
519 .modalias
= "74x164",
520 .platform_data
= &rbspi_ssr_data
,
524 void __init
rbspi_wlan_init(u16 id
, int wmac_offset
)
527 u8 wlan_mac
[ETH_ALEN
];
529 art_buf
= rb_get_ext_wlan_data(id
);
533 ath79_init_mac(wlan_mac
, ath79_mac_base
, wmac_offset
);
534 ath79_register_wmac(art_buf
+ 0x1000, wlan_mac
);
539 #define RBSPI_MACH_BUFLEN 64
541 * Common platform init routine for all SPI NOR devices.
543 static int __init
rbspi_platform_setup(void)
545 const struct rb_info
*info
;
546 char buf
[RBSPI_MACH_BUFLEN
] = "MikroTik ";
548 int len
= RBSPI_MACH_BUFLEN
- strlen(buf
) - 1;
550 info
= rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE
)), 0x20000);
554 if (info
->board_name
) {
555 str
= "RouterBOARD ";
556 if (strncmp(info
->board_name
, str
, strlen(str
))) {
557 strncat(buf
, str
, len
);
560 strncat(buf
, info
->board_name
, len
);
563 strncat(buf
, "UNKNOWN", len
);
565 mips_set_machine_name(buf
);
567 /* fix partitions based on flash parsing */
568 rbspi_init_partitions(info
);
574 * Common peripherals init routine for all SPI NOR devices.
577 static void __init
rbspi_peripherals_setup(u32 flags
)
581 if (flags
& RBSPI_HAS_SSR
)
582 spi_n
= ARRAY_SIZE(rbspi_spi_info
);
584 spi_n
= 1; /* only one device on bus0 */
586 rbspi_ath79_spi_data
.num_chipselect
= spi_n
;
587 rbspi_ath79_spi_data
.cs_gpios
= rbspi_spi_cs_gpios
;
588 ath79_register_spi(&rbspi_ath79_spi_data
, rbspi_spi_info
, spi_n
);
590 if (flags
& RBSPI_HAS_USB
)
591 ath79_register_usb();
593 if (flags
& RBSPI_HAS_PCI
)
594 ath79_register_pci();
598 * Common network init routine for all SPI NOR devices.
601 static void __init
rbspi_network_setup(u32 flags
, int gmac1_offset
,
602 int wmac0_offset
, int wmac1_offset
)
604 /* for QCA953x that will init mdio1_device/data */
605 ath79_register_mdio(0, 0x0);
606 if (flags
& RBSPI_HAS_MDIO1
)
607 ath79_register_mdio(1, 0x0);
609 if (flags
& RBSPI_HAS_WAN4
) {
610 ath79_setup_ar934x_eth_cfg(0);
612 /* set switch to oper mode 1, PHY4 connected to CPU */
613 ath79_switch_data
.phy4_mii_en
= 1;
614 ath79_switch_data
.phy_poll_mask
|= BIT(4);
616 /* init GMAC0 connected to PHY4 at 100M */
617 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
618 ath79_eth0_data
.phy_mask
= BIT(4);
619 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
620 ath79_register_eth(0);
622 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
623 * to the internal switch.
624 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
625 * the QCA953x, this works because this configuration bit is
626 * the same as the AR934x. There's no equivalent function for
627 * QCA953x for now. */
628 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE
);
632 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, gmac1_offset
);
633 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
634 ath79_register_eth(1);
636 if (flags
& RBSPI_HAS_WLAN0
)
637 rbspi_wlan_init(0, wmac0_offset
);
639 if (flags
& RBSPI_HAS_WLAN1
)
640 rbspi_wlan_init(1, wmac1_offset
);
644 * Init the mAP lite hardware (QCA953x).
645 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
646 * Trying to use GMAC0 in direct mode was unsucessful, so we're
647 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
648 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
650 static void __init
rbmapl_setup(void)
652 u32 flags
= RBSPI_HAS_WLAN0
;
654 if (rbspi_platform_setup())
657 rbspi_peripherals_setup(flags
);
659 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
660 rbspi_network_setup(flags
, 0, 1, 0);
662 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds
), rbmapl_leds
);
664 /* mAP lite has a single reset button as gpio 16 */
665 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
666 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
667 rbspi_gpio_keys_reset16
);
669 /* clear internal multiplexing */
670 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH
, AR934X_GPIO_OUT_GPIO
);
671 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER
, AR934X_GPIO_OUT_GPIO
);
675 * Init the hAP lite hardware (QCA953x).
676 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
677 * being assigned to LAN on the casing, and port 1 being assigned
678 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
679 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
681 static void __init
rbhapl_setup(void)
683 u32 flags
= RBSPI_HAS_WLAN0
;
685 if (rbspi_platform_setup())
688 rbspi_peripherals_setup(flags
);
690 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
691 rbspi_network_setup(flags
, 0, 4, 0);
693 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds
), rbhapl_leds
);
695 /* hAP lite has a single reset button as gpio 16 */
696 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
697 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
698 rbspi_gpio_keys_reset16
);
702 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
704 static void __init
rbspi_952_750r2_setup(u32 flags
)
706 if (flags
& RBSPI_HAS_SSR
)
707 rbspi_spi_cs_gpios
[1] = RB952_GPIO_SSR_CS
;
709 rbspi_peripherals_setup(flags
);
712 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
713 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
715 rbspi_network_setup(flags
, 1, 5, 6);
717 if (flags
& RBSPI_HAS_USB
)
718 gpio_request_one(RB952_GPIO_USB_POWER
,
719 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
722 if (flags
& RBSPI_HAS_POE
)
723 gpio_request_one(RB952_GPIO_POE_POWER
,
724 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
727 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds
), rb952_leds
);
729 /* These devices have a single reset button as gpio 16 */
730 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
731 ARRAY_SIZE(rbspi_gpio_keys_reset16
),
732 rbspi_gpio_keys_reset16
);
736 * Init the hAP (ac lite) hardware (QCA953x).
737 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
738 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
739 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
740 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
741 * internal switch for the LAN ports.
742 * The device also has USB, PoE output and an SSR used for LED multiplexing.
743 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
744 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
746 static void __init
rb952_setup(void)
748 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_USB
|
749 RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
751 if (rbspi_platform_setup())
754 /* differentiate the hAP from the hAP ac lite */
755 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
756 flags
|= RBSPI_HAS_WLAN1
| RBSPI_HAS_PCI
;
758 flags
|= RBSPI_HAS_WLAN0
;
760 rbspi_952_750r2_setup(flags
);
764 * Init the hEX (PoE) lite hardware (QCA953x).
765 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
766 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
767 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
768 * lite, only without USB. It shares the same bootloader board identifier.
770 static void __init
rb750upr2_setup(void)
772 u32 flags
= RBSPI_HAS_WAN4
| RBSPI_HAS_SSR
;
774 if (rbspi_platform_setup())
777 /* differentiate the hEX lite from the hEX PoE lite */
778 if (strstr(mips_get_machine_name(), "750UP r2"))
779 flags
|= RBSPI_HAS_USB
| RBSPI_HAS_POE
;
781 /* differentiate the Powerbox from the hEX lite */
782 else if (strstr(mips_get_machine_name(), "750P r2"))
783 flags
|= RBSPI_HAS_POE
;
785 rbspi_952_750r2_setup(flags
);
789 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
790 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
791 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
792 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
793 * The SFP cage is not assigned by default on RouterOS. Extra work is required
794 * to support this interface as it is directly connected to the SoC (eth1).
795 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
796 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
797 * they are not attached to GPIOs, extra work is required to support these.
798 * PoE and USB output power control is supported.
800 static void __init
rb962_setup(void)
802 u32 flags
= RBSPI_HAS_USB
| RBSPI_HAS_POE
| RBSPI_HAS_PCI
;
804 if (rbspi_platform_setup())
807 rbspi_peripherals_setup(flags
);
809 /* Do not call rbspi_network_setup as we have a discrete switch chip */
810 ath79_eth0_pll_data
.pll_1000
= 0xae000000;
811 ath79_eth0_pll_data
.pll_100
= 0xa0000101;
812 ath79_eth0_pll_data
.pll_10
= 0xa0001313;
814 ath79_register_mdio(0, 0x0);
815 mdiobus_register_board_info(rb962_mdio0_info
,
816 ARRAY_SIZE(rb962_mdio0_info
));
818 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN
);
820 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
821 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
822 ath79_eth0_data
.phy_mask
= BIT(0);
823 ath79_eth0_data
.mii_bus_dev
= &ath79_mdio0_device
.dev
;
824 ath79_register_eth(0);
826 /* WLAN1 MAC is HW MAC + 7 */
827 rbspi_wlan_init(1, 7);
829 if (flags
& RBSPI_HAS_USB
)
830 gpio_request_one(RB962_GPIO_USB_POWER
,
831 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
834 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
835 if (flags
& RBSPI_HAS_POE
)
836 gpio_request_one(RB962_GPIO_POE_POWER
,
837 GPIOF_OUT_INIT_HIGH
| GPIOF_ACTIVE_LOW
|
838 GPIOF_EXPORT_DIR_FIXED
,
841 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio
),
844 /* This device has a single reset button as gpio 20 */
845 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
846 ARRAY_SIZE(rbspi_gpio_keys_reset20
),
847 rbspi_gpio_keys_reset20
);
851 * Init the LHG hardware (AR9344).
852 * The LHG 5nD has a single ethernet port connected to PHY0.
853 * Wireless is provided via 5GHz WLAN1.
855 static void __init
rblhg_setup(void)
857 u32 flags
= RBSPI_HAS_WLAN1
| RBSPI_HAS_MDIO1
;
859 if (rbspi_platform_setup())
862 rbspi_peripherals_setup(flags
);
864 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
865 rbspi_network_setup(flags
, 0, 0, 1);
867 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds
), rblhg_leds
);
869 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL
,
870 ARRAY_SIZE(rblhg_gpio_keys
),
875 * Init the wAP hardware (EXPERIMENTAL).
876 * The wAP 2nD has a single ethernet port.
878 static void __init
rbwap_setup(void)
880 u32 flags
= RBSPI_HAS_WLAN0
;
882 if (rbspi_platform_setup())
885 rbspi_peripherals_setup(flags
);
887 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
888 rbspi_network_setup(flags
, 0, 1, 0);
890 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds
), rbwap_leds
);
894 * Init the cAP hardware (EXPERIMENTAL).
895 * The cAP 2nD has a single ethernet port, and a global LED switch.
897 static void __init
rbcap_setup(void)
899 u32 flags
= RBSPI_HAS_WLAN0
;
901 if (rbspi_platform_setup())
904 rbspi_peripherals_setup(flags
);
906 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
907 rbspi_network_setup(flags
, 0, 1, 0);
909 gpio_request_one(RBCAP_GPIO_LED_ALL
,
910 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
913 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds
), rbcap_leds
);
917 * Init the mAP hardware (EXPERIMENTAL).
918 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
921 static void __init
rbmap_setup(void)
923 u32 flags
= RBSPI_HAS_WLAN0
| RBSPI_HAS_SSR
| RBSPI_HAS_POE
;
925 if (rbspi_platform_setup())
928 rbspi_spi_cs_gpios
[1] = RBMAP_GPIO_SSR_CS
;
929 rbspi_peripherals_setup(flags
);
931 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
932 rbspi_network_setup(flags
, 0, 2, 0);
934 if (flags
& RBSPI_HAS_POE
)
935 gpio_request_one(RBMAP_GPIO_POE_POWER
,
936 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
939 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds
), rbmap_leds
);
943 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL
, "map-hb", rbmapl_setup
);
944 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941
, "H951L", rbhapl_setup
);
945 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952
, "952-hb", rb952_setup
);
946 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962
, "962", rb962_setup
);
947 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2
, "750-hb", rb750upr2_setup
);
948 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5
, "lhg", rblhg_setup
);
949 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP
, "wap-hb", rbwap_setup
);
950 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP
, "cap-hb", rbcap_setup
);
951 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP
, "map2-hb", rbmap_setup
);