2 * Atheros AR71xx PCI host controller driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/resource.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/pci.h>
19 #include <linux/pci_regs.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
26 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
28 #define DBG(fmt, args...)
31 #define AR71XX_PCI_DELAY 100 /* msecs */
34 #define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
36 #define PCI_IDSEL_BASE 0
39 static unsigned ar71xx_pci_nr_irqs
;
40 static struct ar71xx_pci_irq
*ar71xx_pci_irq_map __initdata
;
41 static void __iomem
*ar71xx_pcicfg_base
;
43 static DEFINE_SPINLOCK(ar71xx_pci_lock
);
45 static inline void ar71xx_pci_delay(void)
47 mdelay(AR71XX_PCI_DELAY
);
50 static inline u32
ar71xx_pcicfg_rr(unsigned int reg
)
52 return __raw_readl(ar71xx_pcicfg_base
+ reg
);
55 static inline void ar71xx_pcicfg_wr(unsigned int reg
, u32 val
)
57 __raw_writel(val
, ar71xx_pcicfg_base
+ reg
);
60 /* Byte lane enable bits */
61 static u8 ble_table
[4][4] = {
68 static inline u32
ar71xx_pci_get_ble(int where
, int size
, int local
)
72 t
= ble_table
[size
][where
& 3];
73 t
<<= (local
) ? 20 : 4;
77 static inline u32
ar71xx_pci_bus_addr(struct pci_bus
*bus
, unsigned int devfn
,
84 ret
= (1 << (PCI_IDSEL_BASE
+ PCI_SLOT(devfn
)))
85 | (PCI_FUNC(devfn
) << 8) | (where
& ~3);
88 ret
= (bus
->number
<< 16) | (PCI_SLOT(devfn
) << 11)
89 | (PCI_FUNC(devfn
) << 8) | (where
& ~3) | 1;
95 static int __ar71xx_pci_be_handler(int is_fixup
)
100 pci_err
= ar71xx_pcicfg_rr(PCI_REG_PCI_ERR
) & 3;
103 printk(KERN_ALERT
"PCI error %d at PCI addr 0x%x\n",
105 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR
));
107 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR
, pci_err
);
110 ahb_err
= ar71xx_pcicfg_rr(PCI_REG_AHB_ERR
) & 1;
113 printk(KERN_ALERT
"AHB error at AHB address 0x%x\n",
114 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR
));
116 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR
, ahb_err
);
119 return ((ahb_err
| pci_err
) ? 1 : 0);
122 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus
*bus
,
123 unsigned int devfn
, int where
, int size
, u32 cmd
)
127 addr
= ar71xx_pci_bus_addr(bus
, devfn
, where
);
129 DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
130 bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
),
133 ar71xx_pcicfg_wr(PCI_REG_CFG_AD
, addr
);
134 ar71xx_pcicfg_wr(PCI_REG_CFG_CBE
,
135 cmd
| ar71xx_pci_get_ble(where
, size
, 0));
137 return __ar71xx_pci_be_handler(1);
140 static int ar71xx_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
141 int where
, int size
, u32
*value
)
143 static u32 mask
[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
148 ret
= PCIBIOS_SUCCESSFUL
;
150 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus
->number
,
151 PCI_SLOT(devfn
), PCI_FUNC(devfn
), where
, size
);
153 spin_lock_irqsave(&ar71xx_pci_lock
, flags
);
155 if (bus
->number
== 0 && devfn
== 0) {
158 t
= PCI_CRP_CMD_READ
| (where
& ~3);
160 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE
, t
);
161 data
= ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA
);
163 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t
, data
);
168 err
= ar71xx_pci_set_cfgaddr(bus
, devfn
, where
, size
,
172 data
= ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA
);
174 ret
= PCIBIOS_DEVICE_NOT_FOUND
;
179 spin_unlock_irqrestore(&ar71xx_pci_lock
, flags
);
181 DBG("PCI: read config: data=%08x raw=%08x\n",
182 (data
>> (8 * (where
& 3))) & mask
[size
& 7], data
);
184 *value
= (data
>> (8 * (where
& 3))) & mask
[size
& 7];
189 static int ar71xx_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
190 int where
, int size
, u32 value
)
195 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
196 bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
),
199 value
= value
<< (8 * (where
& 3));
200 ret
= PCIBIOS_SUCCESSFUL
;
202 spin_lock_irqsave(&ar71xx_pci_lock
, flags
);
203 if (bus
->number
== 0 && devfn
== 0) {
206 t
= PCI_CRP_CMD_WRITE
| (where
& ~3);
207 t
|= ar71xx_pci_get_ble(where
, size
, 1);
209 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t
, value
);
211 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE
, t
);
212 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA
, value
);
216 err
= ar71xx_pci_set_cfgaddr(bus
, devfn
, where
, size
,
220 ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA
, value
);
222 ret
= PCIBIOS_DEVICE_NOT_FOUND
;
224 spin_unlock_irqrestore(&ar71xx_pci_lock
, flags
);
229 static void ar71xx_pci_fixup(struct pci_dev
*dev
)
233 if (dev
->bus
->number
!= 0 || dev
->devfn
!= 0)
236 DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev
),
237 dev
->vendor
, dev
->device
);
239 /* setup COMMAND register */
240 t
= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
| PCI_COMMAND_INVALIDATE
241 | PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| PCI_COMMAND_FAST_BACK
;
243 pci_write_config_word(dev
, PCI_COMMAND
, t
);
246 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, ar71xx_pci_fixup
);
248 int __init
pcibios_map_irq(const struct pci_dev
*dev
, uint8_t slot
, uint8_t pin
)
253 slot
-= PCI_IDSEL_ADL_START
- PCI_IDSEL_BASE
;
255 for (i
= 0; i
< ar71xx_pci_nr_irqs
; i
++) {
256 struct ar71xx_pci_irq
*entry
;
258 entry
= &ar71xx_pci_irq_map
[i
];
259 if (entry
->slot
== slot
&& entry
->pin
== pin
) {
266 printk(KERN_ALERT
"PCI: no irq found for pin%u@%s\n",
267 pin
, pci_name((struct pci_dev
*)dev
));
269 printk(KERN_INFO
"PCI: mapping irq %d to pin%u@%s\n",
270 irq
, pin
, pci_name((struct pci_dev
*)dev
));
276 int pcibios_plat_dev_init(struct pci_dev
*dev
)
281 static struct pci_ops ar71xx_pci_ops
= {
282 .read
= ar71xx_pci_read_config
,
283 .write
= ar71xx_pci_write_config
,
286 static struct resource ar71xx_pci_io_resource
= {
287 .name
= "PCI IO space",
290 .flags
= IORESOURCE_IO
,
293 static struct resource ar71xx_pci_mem_resource
= {
294 .name
= "PCI memory space",
295 .start
= AR71XX_PCI_MEM_BASE
,
296 .end
= AR71XX_PCI_MEM_BASE
+ AR71XX_PCI_MEM_SIZE
- 1,
297 .flags
= IORESOURCE_MEM
300 static struct pci_controller ar71xx_pci_controller
= {
301 .pci_ops
= &ar71xx_pci_ops
,
302 .mem_resource
= &ar71xx_pci_mem_resource
,
303 .io_resource
= &ar71xx_pci_io_resource
,
306 static int __init
__ar71xx_pci_bios_init(unsigned nr_irqs
,
307 struct ar71xx_pci_irq
*map
)
309 ar71xx_device_stop(RESET_MODULE_PCI_BUS
| RESET_MODULE_PCI_CORE
);
312 ar71xx_device_start(RESET_MODULE_PCI_BUS
| RESET_MODULE_PCI_CORE
);
315 ar71xx_pcicfg_base
= ioremap_nocache(AR71XX_PCI_CFG_BASE
,
316 AR71XX_PCI_CFG_SIZE
);
318 ar71xx_ddr_wr(DDR_REG_PCI_WIN0
, PCI_WIN0_OFFS
);
319 ar71xx_ddr_wr(DDR_REG_PCI_WIN1
, PCI_WIN1_OFFS
);
320 ar71xx_ddr_wr(DDR_REG_PCI_WIN2
, PCI_WIN2_OFFS
);
321 ar71xx_ddr_wr(DDR_REG_PCI_WIN3
, PCI_WIN3_OFFS
);
322 ar71xx_ddr_wr(DDR_REG_PCI_WIN4
, PCI_WIN4_OFFS
);
323 ar71xx_ddr_wr(DDR_REG_PCI_WIN5
, PCI_WIN5_OFFS
);
324 ar71xx_ddr_wr(DDR_REG_PCI_WIN6
, PCI_WIN6_OFFS
);
325 ar71xx_ddr_wr(DDR_REG_PCI_WIN7
, PCI_WIN7_OFFS
);
329 /* clear bus errors */
330 (void)__ar71xx_pci_be_handler(1);
332 ar71xx_pci_nr_irqs
= nr_irqs
;
333 ar71xx_pci_irq_map
= map
;
334 ar71xx_pci_be_handler
= __ar71xx_pci_be_handler
;
336 register_pci_controller(&ar71xx_pci_controller
);
341 static int __init
__ar71xx_pci_init(void)
343 ar71xx_pci_bios_init
= __ar71xx_pci_bios_init
;
346 pure_initcall(__ar71xx_pci_init
);