2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
22 #include <linux/platform/ar934x_nfc.h>
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
125 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
126 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
127 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
128 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
129 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
130 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
137 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
138 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
139 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
141 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
143 /* default timing values */
144 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
145 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
146 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
148 #define AR934X_NFC_ID_BUF_SIZE 8
149 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
150 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
151 #define AR934X_NFC_DONE_TIMEOUT 1000
152 #define AR934X_NFC_DMA_RETRIES 20
154 #define AR934X_NFC_USE_IRQ true
155 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
157 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
159 #undef AR934X_NFC_DEBUG_DATA
160 #undef AR934X_NFC_DEBUG
164 static inline __attribute__ ((format (printf
, 2, 3)))
165 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
169 #ifdef AR934X_NFC_DEBUG
170 #define nfc_dbg(_nfc, fmt, ...) \
171 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
173 #define nfc_dbg(_nfc, fmt, ...) \
174 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
175 #endif /* AR934X_NFC_DEBUG */
177 #ifdef AR934X_NFC_DEBUG_DATA
179 nfc_debug_data(const char *label
, void *data
, int len
)
181 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
186 nfc_debug_data(const char *label
, void *data
, int len
) {}
187 #endif /* AR934X_NFC_DEBUG_DATA */
191 struct nand_chip nand_chip
;
192 struct device
*parent
;
194 void (*select_chip
)(int chip_no
);
197 wait_queue_head_t irq_waitq
;
199 bool spurious_irq_expected
;
209 unsigned int addr_count0
;
210 unsigned int addr_count1
;
214 unsigned int buf_size
;
219 int erase1_page_addr
;
221 int rndout_page_addr
;
229 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
232 is_all_ff(u8
*buf
, int len
)
235 if (buf
[len
] != 0xff)
242 ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
244 __raw_writel(val
, nfc
->base
+ reg
);
248 ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
250 return __raw_readl(nfc
->base
+ reg
);
253 static inline struct ar934x_nfc_platform_data
*
254 ar934x_nfc_get_platform_data(struct ar934x_nfc
*nfc
)
256 return nfc
->parent
->platform_data
;
260 ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
262 return container_of(mtd
, struct ar934x_nfc
, mtd
);
265 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
267 return AR934X_NFC_USE_IRQ
;
270 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
274 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
276 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
280 __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
284 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
285 return (status
& 0xff) == 0xff;
289 __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
293 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
294 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
298 ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
300 unsigned long timeout
;
302 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
304 if (__ar934x_nfc_dev_ready(nfc
))
306 } while time_before(jiffies
, timeout
);
308 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
309 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
310 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
315 ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
317 unsigned long timeout
;
319 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
321 if (__ar934x_nfc_is_dma_ready(nfc
))
323 } while time_before(jiffies
, timeout
);
325 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
326 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
331 ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
336 timeout
= wait_event_timeout(nfc
->irq_waitq
,
337 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
338 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
342 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
343 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
345 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
348 "timeout waiting for interrupt, status:%08x\n",
358 ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
362 if (ar934x_nfc_use_irq(nfc
))
363 ret
= ar934x_nfc_wait_irq(nfc
);
365 ret
= ar934x_nfc_wait_dev_ready(nfc
);
370 return ar934x_nfc_wait_dma_ready(nfc
);
374 ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
376 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
377 &nfc
->buf_dma
, GFP_KERNEL
);
378 if (nfc
->buf
== NULL
) {
379 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
383 nfc
->buf_size
= size
;
384 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
390 ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
392 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
396 ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
397 u32
*addr0
, u32
*addr1
)
406 a0
= (page_addr
& 0xffff) << 16;
407 a1
= (page_addr
>> 16) & 0xf;
408 } else if (page_addr
!= -1) {
409 /* SEQIN, READ0, etc.. */
411 /* TODO: handle 16bit bus width */
412 if (nfc
->small_page
) {
414 a0
|= (page_addr
& 0xff) << 8;
415 a0
|= ((page_addr
>> 8) & 0xff) << 16;
416 a0
|= ((page_addr
>> 16) & 0xff) << 24;
418 a0
= column
& 0x0FFF;
419 a0
|= (page_addr
& 0xffff) << 16;
421 if (nfc
->addr_count0
> 4)
422 a1
= (page_addr
>> 16) & 0xf;
431 ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
435 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
436 AR934X_NFC_CMD_SEQ_1C
;
437 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
439 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
440 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
442 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
443 ar934x_nfc_wait_dev_ready(nfc
);
447 ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
448 int len
, u32 cmd_reg
, u32 ctrl_reg
, bool write
)
458 if (WARN_ON(len
> nfc
->buf_size
))
459 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
, nfc
->buf_size
);
462 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
465 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
466 dir
= DMA_FROM_DEVICE
;
469 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
471 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
472 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
473 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
475 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
476 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
478 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
479 (write
) ? "write" : "read",
480 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
483 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
484 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
485 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
486 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
487 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
488 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
489 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
490 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
491 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_CTRL
, nfc
->ecc_ctrl_reg
);
492 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_OFFSET
, nfc
->ecc_offset_reg
);
494 if (ar934x_nfc_use_irq(nfc
)) {
495 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, AR934X_NFC_IRQ_MASK
);
497 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
500 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
501 err
= ar934x_nfc_wait_done(nfc
);
503 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
504 (write
) ? "write" : "read", page_addr
);
506 ar934x_nfc_restart(nfc
);
507 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
510 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
511 (write
) ? "write" : "read", page_addr
);
518 ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
523 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
525 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
526 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
528 err
= ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
,
529 cmd_reg
, nfc
->ctrl_reg
, false);
531 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
537 ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
538 int page_addr
, int len
)
543 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
544 column
, page_addr
, len
);
546 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
548 if (nfc
->small_page
) {
549 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
551 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
552 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
555 err
= ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
556 cmd_reg
, nfc
->ctrl_reg
, false);
558 nfc_debug_data("[data] ", nfc
->buf
, len
);
564 ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
571 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
573 ctrl_reg
= nfc
->ctrl_reg
;
574 if (nfc
->small_page
) {
575 /* override number of address cycles for the erase command */
576 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
577 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
578 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
579 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
580 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
581 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
582 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
585 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
586 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
587 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
589 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
590 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
592 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
593 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
594 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
595 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
597 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
598 ar934x_nfc_wait_dev_ready(nfc
);
602 ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
603 int page_addr
, int len
)
607 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
608 column
, page_addr
, len
);
610 nfc_debug_data("[data] ", nfc
->buf
, len
);
612 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
613 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
614 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
616 return ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
617 cmd_reg
, nfc
->ctrl_reg
, true);
621 ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
626 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
627 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
629 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
630 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
632 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
633 ar934x_nfc_wait_dev_ready(nfc
);
635 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
637 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
638 cmd_reg
, (status
& 0xff));
641 nfc
->buf
[0 ^ 3] = status
;
643 nfc
->buf
[0] = status
;
647 ar934x_nfc_cmdfunc(struct mtd_info
*mtd
, unsigned int command
, int column
,
650 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
651 struct nand_chip
*nand
= mtd
->priv
;
653 nfc
->read_id
= false;
654 if (command
!= NAND_CMD_PAGEPROG
)
659 ar934x_nfc_send_cmd(nfc
, command
);
662 case NAND_CMD_READID
:
664 ar934x_nfc_send_readid(nfc
, command
);
669 if (nfc
->small_page
) {
670 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
671 mtd
->writesize
+ mtd
->oobsize
);
673 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
674 mtd
->writesize
+ mtd
->oobsize
);
675 nfc
->buf_index
= column
;
676 nfc
->rndout_page_addr
= page_addr
;
677 nfc
->rndout_read_cmd
= command
;
681 case NAND_CMD_READOOB
:
683 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
687 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
688 mtd
->writesize
, page_addr
,
692 case NAND_CMD_RNDOUT
:
693 if (WARN_ON(nfc
->small_page
))
696 /* emulate subpage read */
697 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
698 nfc
->rndout_page_addr
,
699 mtd
->writesize
+ mtd
->oobsize
);
700 nfc
->buf_index
= column
;
703 case NAND_CMD_ERASE1
:
704 nfc
->erase1_page_addr
= page_addr
;
707 case NAND_CMD_ERASE2
:
708 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
711 case NAND_CMD_STATUS
:
712 ar934x_nfc_read_status(nfc
);
716 if (nfc
->small_page
) {
717 /* output read command */
718 if (column
>= mtd
->writesize
) {
719 column
-= mtd
->writesize
;
720 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
721 } else if (column
< 256) {
722 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
725 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
728 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
730 nfc
->seqin_column
= column
;
731 nfc
->seqin_page_addr
= page_addr
;
734 case NAND_CMD_PAGEPROG
:
735 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
736 /* the data is already written */
741 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
743 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
744 nfc
->seqin_page_addr
,
750 "unsupported command: %x, column:%d page_addr=%d\n",
751 command
, column
, page_addr
);
757 ar934x_nfc_dev_ready(struct mtd_info
*mtd
)
759 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
761 return __ar934x_nfc_dev_ready(nfc
);
765 ar934x_nfc_select_chip(struct mtd_info
*mtd
, int chip_no
)
767 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
769 if (nfc
->select_chip
)
770 nfc
->select_chip(chip_no
);
774 ar934x_nfc_read_byte(struct mtd_info
*mtd
)
776 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
779 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
781 if (nfc
->swap_dma
|| nfc
->read_id
)
782 data
= nfc
->buf
[nfc
->buf_index
^ 3];
784 data
= nfc
->buf
[nfc
->buf_index
];
792 ar934x_nfc_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
794 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
797 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
800 for (i
= 0; i
< len
; i
++) {
801 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
805 for (i
= 0; i
< len
; i
++) {
806 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
813 ar934x_nfc_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
815 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
819 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
821 buf_index
= nfc
->buf_index
;
823 if (nfc
->swap_dma
|| nfc
->read_id
) {
824 for (i
= 0; i
< len
; i
++) {
825 buf
[i
] = nfc
->buf
[buf_index
^ 3];
829 for (i
= 0; i
< len
; i
++) {
830 buf
[i
] = nfc
->buf
[buf_index
];
835 nfc
->buf_index
= buf_index
;
839 ar934x_nfc_enable_hwecc(struct ar934x_nfc
*nfc
)
841 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_ECC_EN
;
842 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
846 ar934x_nfc_disable_hwecc(struct ar934x_nfc
*nfc
)
848 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_ECC_EN
;
849 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
853 ar934x_nfc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
856 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
859 nfc_dbg(nfc
, "read_oob: page:%d\n", page
);
861 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
, page
,
866 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
872 ar934x_nfc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
875 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
877 nfc_dbg(nfc
, "write_oob: page:%d\n", page
);
879 memcpy(nfc
->buf
, chip
->oob_poi
, mtd
->oobsize
);
881 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, mtd
->writesize
,
886 ar934x_nfc_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
887 u8
*buf
, int oob_required
, int page
)
889 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
893 nfc_dbg(nfc
, "read_page_raw: page:%d oob:%d\n", page
, oob_required
);
895 len
= mtd
->writesize
;
899 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
, len
);
903 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
906 memcpy(chip
->oob_poi
, &nfc
->buf
[mtd
->writesize
], mtd
->oobsize
);
912 ar934x_nfc_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
913 u8
*buf
, int oob_required
, int page
)
915 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
917 int max_bitflips
= 0;
922 nfc_dbg(nfc
, "read_page: page:%d oob:%d\n", page
, oob_required
);
924 ar934x_nfc_enable_hwecc(nfc
);
925 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
,
927 ar934x_nfc_disable_hwecc(nfc
);
932 /* TODO: optimize to avoid memcpy */
933 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
935 /* read the ECC status */
936 ecc_ctrl
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_ECC_CTRL
);
937 ecc_failed
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_UNCORRECT
;
938 ecc_corrected
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_CORRECT
;
940 if (oob_required
|| ecc_failed
) {
941 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
,
947 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
952 * The hardware ECC engine reports uncorrectable errors
953 * on empty pages. Check the ECC bytes and the data. If
954 * both contains 0xff bytes only, dont report a failure.
956 * TODO: prebuild a buffer with 0xff bytes and use memcmp
957 * for better performance?
959 if (!is_all_ff(&nfc
->buf
[nfc
->ecc_oob_pos
], chip
->ecc
.total
) ||
960 !is_all_ff(buf
, mtd
->writesize
))
961 mtd
->ecc_stats
.failed
++;
962 } else if (ecc_corrected
) {
964 * The hardware does not report the exact count of the
965 * corrected bitflips, use assumptions based on the
968 if (ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_OVER
) {
970 * The number of corrected bitflips exceeds the
971 * threshold. Assume the maximum.
973 max_bitflips
= chip
->ecc
.strength
* chip
->ecc
.steps
;
975 max_bitflips
= nfc
->ecc_thres
* chip
->ecc
.steps
;
978 mtd
->ecc_stats
.corrected
+= max_bitflips
;
985 ar934x_nfc_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
986 const u8
*buf
, int oob_required
)
988 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
992 page
= nfc
->seqin_page_addr
;
994 nfc_dbg(nfc
, "write_page_raw: page:%d oob:%d\n", page
, oob_required
);
996 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
997 len
= mtd
->writesize
;
1000 memcpy(&nfc
->buf
[mtd
->writesize
], chip
->oob_poi
, mtd
->oobsize
);
1001 len
+= mtd
->oobsize
;
1004 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
, len
);
1008 ar934x_nfc_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1009 const u8
*buf
, int oob_required
)
1011 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1015 page
= nfc
->seqin_page_addr
;
1017 nfc_dbg(nfc
, "write_page: page:%d oob:%d\n", page
, oob_required
);
1019 /* write OOB first */
1021 !is_all_ff(chip
->oob_poi
, mtd
->oobsize
)) {
1022 err
= ar934x_nfc_write_oob(mtd
, chip
, page
);
1027 /* TODO: optimize to avoid memcopy */
1028 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
1030 ar934x_nfc_enable_hwecc(nfc
);
1031 err
= ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
,
1033 ar934x_nfc_disable_hwecc(nfc
);
1039 ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
1041 struct ar934x_nfc_platform_data
*pdata
;
1043 pdata
= ar934x_nfc_get_platform_data(nfc
);
1044 if (pdata
->hw_reset
) {
1045 pdata
->hw_reset(true);
1046 pdata
->hw_reset(false);
1051 * TODO: make it configurable via platform data
1053 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
1054 AR934X_NFC_TIME_SEQ_DEFAULT
);
1055 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
1056 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
1057 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
1058 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
1060 /* disable WP on all chips, and select chip 0 */
1061 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
1063 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
1065 /* initialize Control register */
1066 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1067 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1069 if (nfc
->small_page
) {
1070 /* Setup generic sequence register for small page reads. */
1071 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
1072 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
1077 ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
1081 if (nfc
->select_chip
)
1082 nfc
->select_chip(-1);
1084 ctrl_reg
= nfc
->ctrl_reg
;
1085 ar934x_nfc_hw_init(nfc
);
1086 nfc
->ctrl_reg
= ctrl_reg
;
1088 if (nfc
->select_chip
)
1089 nfc
->select_chip(0);
1091 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
1095 ar934x_nfc_irq_handler(int irq
, void *data
)
1097 struct ar934x_nfc
*nfc
= data
;
1100 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1102 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
1104 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1106 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
1108 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
1110 nfc
->irq_status
= status
;
1111 nfc
->spurious_irq_expected
= true;
1112 wake_up(&nfc
->irq_waitq
);
1114 if (nfc
->spurious_irq_expected
) {
1115 nfc
->spurious_irq_expected
= false;
1117 dev_warn(nfc
->parent
, "spurious interrupt\n");
1125 ar934x_nfc_init_tail(struct mtd_info
*mtd
)
1127 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1128 struct nand_chip
*chip
= &nfc
->nand_chip
;
1133 switch (mtd
->oobsize
) {
1137 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
1141 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
1146 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1148 switch (mtd
->erasesize
/ mtd
->writesize
) {
1150 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
1154 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
1158 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
1162 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
1166 dev_err(nfc
->parent
, "unsupported block size: %u\n",
1167 mtd
->erasesize
/ mtd
->writesize
);
1171 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
1173 switch (mtd
->writesize
) {
1175 nfc
->small_page
= 1;
1176 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
1180 nfc
->small_page
= 1;
1181 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
1185 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
1189 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
1193 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
1197 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
1201 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
1205 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
1210 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
1212 if (nfc
->small_page
) {
1213 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
1215 if (chip
->chipsize
> (32 << 20)) {
1216 nfc
->addr_count0
= 4;
1217 nfc
->addr_count1
= 3;
1218 } else if (chip
->chipsize
> (2 << 16)) {
1219 nfc
->addr_count0
= 3;
1220 nfc
->addr_count1
= 2;
1222 nfc
->addr_count0
= 2;
1223 nfc
->addr_count1
= 1;
1226 if (chip
->chipsize
> (128 << 20)) {
1227 nfc
->addr_count0
= 5;
1228 nfc
->addr_count1
= 3;
1229 } else if (chip
->chipsize
> (8 << 16)) {
1230 nfc
->addr_count0
= 4;
1231 nfc
->addr_count1
= 2;
1233 nfc
->addr_count0
= 3;
1234 nfc
->addr_count1
= 1;
1238 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
1239 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
1241 nfc
->ctrl_reg
= ctrl
;
1242 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1244 ar934x_nfc_free_buf(nfc
);
1245 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1250 static struct nand_ecclayout ar934x_nfc_oob_64_hwecc
= {
1253 20, 21, 22, 23, 24, 25, 26,
1254 27, 28, 29, 30, 31, 32, 33,
1255 34, 35, 36, 37, 38, 39, 40,
1256 41, 42, 43, 44, 45, 46, 47,
1271 ar934x_nfc_setup_hwecc(struct ar934x_nfc
*nfc
)
1273 struct nand_chip
*nand
= &nfc
->nand_chip
;
1277 if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC
)) {
1278 dev_err(nfc
->parent
, "hardware ECC support is disabled\n");
1282 switch (nfc
->mtd
.writesize
) {
1285 * Writing a subpage separately is not supported, because
1286 * the controller only does ECC on full-page accesses.
1288 nand
->options
= NAND_NO_SUBPAGE_WRITE
;
1290 nand
->ecc
.size
= 512;
1291 nand
->ecc
.bytes
= 7;
1292 nand
->ecc
.strength
= 4;
1293 nand
->ecc
.layout
= &ar934x_nfc_oob_64_hwecc
;
1297 dev_err(nfc
->parent
,
1298 "hardware ECC is not available for %d byte pages\n",
1299 nfc
->mtd
.writesize
);
1303 BUG_ON(!nand
->ecc
.layout
);
1305 switch (nand
->ecc
.strength
) {
1307 ecc_cap
= AR934X_NFC_ECC_CTRL_ECC_CAP_4
;
1312 dev_err(nfc
->parent
, "unsupported ECC strength %u\n",
1313 nand
->ecc
.strength
);
1317 nfc
->ecc_thres
= ecc_thres
;
1318 nfc
->ecc_oob_pos
= nand
->ecc
.layout
->eccpos
[0];
1320 nfc
->ecc_ctrl_reg
= ecc_cap
<< AR934X_NFC_ECC_CTRL_ECC_CAP_S
;
1321 nfc
->ecc_ctrl_reg
|= ecc_thres
<< AR934X_NFC_ECC_CTRL_ERR_THRES_S
;
1323 nfc
->ecc_offset_reg
= nfc
->mtd
.writesize
+ nfc
->ecc_oob_pos
;
1325 nand
->ecc
.mode
= NAND_ECC_HW
;
1326 nand
->ecc
.read_page
= ar934x_nfc_read_page
;
1327 nand
->ecc
.read_page_raw
= ar934x_nfc_read_page_raw
;
1328 nand
->ecc
.write_page
= ar934x_nfc_write_page
;
1329 nand
->ecc
.write_page_raw
= ar934x_nfc_write_page_raw
;
1330 nand
->ecc
.read_oob
= ar934x_nfc_read_oob
;
1331 nand
->ecc
.write_oob
= ar934x_nfc_write_oob
;
1337 ar934x_nfc_probe(struct platform_device
*pdev
)
1339 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
1340 struct ar934x_nfc_platform_data
*pdata
;
1341 struct ar934x_nfc
*nfc
;
1342 struct resource
*res
;
1343 struct mtd_info
*mtd
;
1344 struct nand_chip
*nand
;
1345 struct mtd_part_parser_data ppdata
;
1348 pdata
= pdev
->dev
.platform_data
;
1349 if (pdata
== NULL
) {
1350 dev_err(&pdev
->dev
, "no platform data defined\n");
1354 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1356 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1360 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1362 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1366 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1367 if (IS_ERR(nfc
->base
)) {
1368 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1369 return PTR_ERR(nfc
->base
);
1372 nfc
->irq
= platform_get_irq(pdev
, 0);
1374 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1378 init_waitqueue_head(&nfc
->irq_waitq
);
1379 ret
= request_irq(nfc
->irq
, ar934x_nfc_irq_handler
, 0,
1380 dev_name(&pdev
->dev
), nfc
);
1382 dev_err(&pdev
->dev
, "requast_irq failed, err:%d\n", ret
);
1386 nfc
->parent
= &pdev
->dev
;
1387 nfc
->select_chip
= pdata
->select_chip
;
1388 nfc
->swap_dma
= pdata
->swap_dma
;
1390 nand
= &nfc
->nand_chip
;
1394 mtd
->owner
= THIS_MODULE
;
1396 mtd
->name
= pdata
->name
;
1398 mtd
->name
= dev_name(&pdev
->dev
);
1400 nand
->chip_delay
= 25;
1402 nand
->dev_ready
= ar934x_nfc_dev_ready
;
1403 nand
->cmdfunc
= ar934x_nfc_cmdfunc
;
1404 nand
->read_byte
= ar934x_nfc_read_byte
;
1405 nand
->write_buf
= ar934x_nfc_write_buf
;
1406 nand
->read_buf
= ar934x_nfc_read_buf
;
1407 nand
->select_chip
= ar934x_nfc_select_chip
;
1409 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1413 platform_set_drvdata(pdev
, nfc
);
1415 ar934x_nfc_hw_init(nfc
);
1417 ret
= nand_scan_ident(mtd
, 1, NULL
);
1419 dev_err(&pdev
->dev
, "nand_scan_ident failed, err:%d\n", ret
);
1423 ret
= ar934x_nfc_init_tail(mtd
);
1425 dev_err(&pdev
->dev
, "init tail failed, err:%d\n", ret
);
1429 if (pdata
->scan_fixup
) {
1430 ret
= pdata
->scan_fixup(mtd
);
1435 switch (pdata
->ecc_mode
) {
1436 case AR934X_NFC_ECC_SOFT
:
1437 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1440 case AR934X_NFC_ECC_SOFT_BCH
:
1441 nand
->ecc
.mode
= NAND_ECC_SOFT_BCH
;
1444 case AR934X_NFC_ECC_HW
:
1445 ret
= ar934x_nfc_setup_hwecc(nfc
);
1452 dev_err(nfc
->parent
, "unknown ECC mode %d\n", pdata
->ecc_mode
);
1456 ret
= nand_scan_tail(mtd
);
1458 dev_err(&pdev
->dev
, "scan tail failed, err:%d\n", ret
);
1462 memset(&ppdata
, '\0', sizeof(ppdata
));
1463 ret
= mtd_device_parse_register(mtd
, part_probes
, &ppdata
,
1464 pdata
->parts
, pdata
->nr_parts
);
1466 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1473 ar934x_nfc_free_buf(nfc
);
1475 free_irq(nfc
->irq
, nfc
);
1480 ar934x_nfc_remove(struct platform_device
*pdev
)
1482 struct ar934x_nfc
*nfc
;
1484 nfc
= platform_get_drvdata(pdev
);
1486 nand_release(&nfc
->mtd
);
1487 ar934x_nfc_free_buf(nfc
);
1488 free_irq(nfc
->irq
, nfc
);
1494 static struct platform_driver ar934x_nfc_driver
= {
1495 .probe
= ar934x_nfc_probe
,
1496 .remove
= ar934x_nfc_remove
,
1498 .name
= AR934X_NFC_DRIVER_NAME
,
1499 .owner
= THIS_MODULE
,
1503 module_platform_driver(ar934x_nfc_driver
);
1505 MODULE_LICENSE("GPL v2");
1506 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1507 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1508 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);