2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
23 #include <linux/platform/ar934x_nfc.h>
25 #define AR934X_NFC_REG_CMD 0x00
26 #define AR934X_NFC_REG_CTRL 0x04
27 #define AR934X_NFC_REG_STATUS 0x08
28 #define AR934X_NFC_REG_INT_MASK 0x0c
29 #define AR934X_NFC_REG_INT_STATUS 0x10
30 #define AR934X_NFC_REG_ECC_CTRL 0x14
31 #define AR934X_NFC_REG_ECC_OFFSET 0x18
32 #define AR934X_NFC_REG_ADDR0_0 0x1c
33 #define AR934X_NFC_REG_ADDR0_1 0x24
34 #define AR934X_NFC_REG_ADDR1_0 0x20
35 #define AR934X_NFC_REG_ADDR1_1 0x28
36 #define AR934X_NFC_REG_SPARE_SIZE 0x30
37 #define AR934X_NFC_REG_PROTECT 0x38
38 #define AR934X_NFC_REG_LOOKUP_EN 0x40
39 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
40 #define AR934X_NFC_REG_DMA_ADDR 0x64
41 #define AR934X_NFC_REG_DMA_COUNT 0x68
42 #define AR934X_NFC_REG_DMA_CTRL 0x6c
43 #define AR934X_NFC_REG_MEM_CTRL 0x80
44 #define AR934X_NFC_REG_DATA_SIZE 0x84
45 #define AR934X_NFC_REG_READ_STATUS 0x88
46 #define AR934X_NFC_REG_TIME_SEQ 0x8c
47 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
48 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
49 #define AR934X_NFC_REG_FIFO_DATA 0x98
50 #define AR934X_NFC_REG_TIME_MODE 0x9c
51 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
52 #define AR934X_NFC_REG_FIFO_INIT 0xb0
53 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
55 #define AR934X_NFC_CMD_CMD_SEQ_S 0
56 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
57 #define AR934X_NFC_CMD_SEQ_1C 0x00
58 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
59 #define AR934X_NFC_CMD_SEQ_12 0x0c
60 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
61 #define AR934X_NFC_CMD_SEQ_S 0x24
62 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
63 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
64 #define AR934X_NFC_CMD_SEQ_18 0x32
65 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
66 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
67 #define AR934X_NFC_CMD_ADDR_SEL_0 0
68 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
69 #define AR934X_NFC_CMD_CMD0_S 8
70 #define AR934X_NFC_CMD_CMD0_M 0xff
71 #define AR934X_NFC_CMD_CMD1_S 16
72 #define AR934X_NFC_CMD_CMD1_M 0xff
73 #define AR934X_NFC_CMD_CMD2_S 24
74 #define AR934X_NFC_CMD_CMD2_M 0xff
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
77 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
78 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
79 #define AR934X_NFC_CTRL_INT_EN BIT(4)
80 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
86 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
87 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
88 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
89 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
90 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
91 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
92 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
93 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
94 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
95 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
96 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
97 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
98 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
99 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
100 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
101 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
102 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
103 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
104 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
106 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
107 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
109 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
111 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
112 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
120 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
121 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
123 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
124 #define AR934X_NFC_INT_CMD_END BIT(1)
126 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
127 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
128 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
129 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
130 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
138 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
139 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
140 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
142 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
144 /* default timing values */
145 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
146 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
147 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
149 #define AR934X_NFC_ID_BUF_SIZE 8
150 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
151 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
152 #define AR934X_NFC_DONE_TIMEOUT 1000
153 #define AR934X_NFC_DMA_RETRIES 20
155 #define AR934X_NFC_USE_IRQ true
156 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
158 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
160 #undef AR934X_NFC_DEBUG_DATA
161 #undef AR934X_NFC_DEBUG
165 static inline __attribute__ ((format (printf
, 2, 3)))
166 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
170 #ifdef AR934X_NFC_DEBUG
171 #define nfc_dbg(_nfc, fmt, ...) \
172 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
174 #define nfc_dbg(_nfc, fmt, ...) \
175 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
176 #endif /* AR934X_NFC_DEBUG */
178 #ifdef AR934X_NFC_DEBUG_DATA
180 nfc_debug_data(const char *label
, void *data
, int len
)
182 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
187 nfc_debug_data(const char *label
, void *data
, int len
) {}
188 #endif /* AR934X_NFC_DEBUG_DATA */
191 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
194 struct nand_chip nand_chip
;
195 struct device
*parent
;
197 void (*select_chip
)(int chip_no
);
200 wait_queue_head_t irq_waitq
;
202 bool spurious_irq_expected
;
212 unsigned int addr_count0
;
213 unsigned int addr_count1
;
217 unsigned int buf_size
;
222 int erase1_page_addr
;
224 int rndout_page_addr
;
232 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
235 is_all_ff(u8
*buf
, int len
)
238 if (buf
[len
] != 0xff)
245 ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
247 __raw_writel(val
, nfc
->base
+ reg
);
251 ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
253 return __raw_readl(nfc
->base
+ reg
);
256 static inline struct ar934x_nfc_platform_data
*
257 ar934x_nfc_get_platform_data(struct ar934x_nfc
*nfc
)
259 return nfc
->parent
->platform_data
;
263 ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
265 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
266 return container_of(mtd
, struct ar934x_nfc
, mtd
);
268 struct nand_chip
*chip
= mtd_to_nand(mtd
);
270 return container_of(chip
, struct ar934x_nfc
, nand_chip
);
274 static struct mtd_info
*ar934x_nfc_to_mtd(struct ar934x_nfc
*nfc
)
276 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
279 return nand_to_mtd(&nfc
->nand_chip
);
283 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
285 return AR934X_NFC_USE_IRQ
;
288 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
292 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
294 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
298 __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
302 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
303 return (status
& 0xff) == 0xff;
307 __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
311 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
312 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
316 ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
318 unsigned long timeout
;
320 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
322 if (__ar934x_nfc_dev_ready(nfc
))
324 } while time_before(jiffies
, timeout
);
326 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
327 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
328 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
333 ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
335 unsigned long timeout
;
337 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
339 if (__ar934x_nfc_is_dma_ready(nfc
))
341 } while time_before(jiffies
, timeout
);
343 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
344 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
349 ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
354 timeout
= wait_event_timeout(nfc
->irq_waitq
,
355 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
356 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
360 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
361 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
363 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
366 "timeout waiting for interrupt, status:%08x\n",
376 ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
380 if (ar934x_nfc_use_irq(nfc
))
381 ret
= ar934x_nfc_wait_irq(nfc
);
383 ret
= ar934x_nfc_wait_dev_ready(nfc
);
388 return ar934x_nfc_wait_dma_ready(nfc
);
392 ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
394 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
395 &nfc
->buf_dma
, GFP_KERNEL
);
396 if (nfc
->buf
== NULL
) {
397 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
401 nfc
->buf_size
= size
;
402 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
408 ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
410 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
414 ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
415 u32
*addr0
, u32
*addr1
)
424 a0
= (page_addr
& 0xffff) << 16;
425 a1
= (page_addr
>> 16) & 0xf;
426 } else if (page_addr
!= -1) {
427 /* SEQIN, READ0, etc.. */
429 /* TODO: handle 16bit bus width */
430 if (nfc
->small_page
) {
432 a0
|= (page_addr
& 0xff) << 8;
433 a0
|= ((page_addr
>> 8) & 0xff) << 16;
434 a0
|= ((page_addr
>> 16) & 0xff) << 24;
436 a0
= column
& 0x0FFF;
437 a0
|= (page_addr
& 0xffff) << 16;
439 if (nfc
->addr_count0
> 4)
440 a1
= (page_addr
>> 16) & 0xf;
449 ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
453 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
454 AR934X_NFC_CMD_SEQ_1C
;
455 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
457 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
458 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
460 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
461 ar934x_nfc_wait_dev_ready(nfc
);
465 ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
466 int len
, u32 cmd_reg
, u32 ctrl_reg
, bool write
)
476 if (WARN_ON(len
> nfc
->buf_size
))
477 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
, nfc
->buf_size
);
480 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
483 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
484 dir
= DMA_FROM_DEVICE
;
487 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
489 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
490 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
491 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
493 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
494 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
496 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
497 (write
) ? "write" : "read",
498 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
501 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
502 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
503 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
504 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
505 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
506 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
507 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
508 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
509 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_CTRL
, nfc
->ecc_ctrl_reg
);
510 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_OFFSET
, nfc
->ecc_offset_reg
);
512 if (ar934x_nfc_use_irq(nfc
)) {
513 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, AR934X_NFC_IRQ_MASK
);
515 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
518 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
519 err
= ar934x_nfc_wait_done(nfc
);
521 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
522 (write
) ? "write" : "read", page_addr
);
524 ar934x_nfc_restart(nfc
);
525 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
528 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
529 (write
) ? "write" : "read", page_addr
);
536 ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
541 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
543 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
544 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
546 err
= ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
,
547 cmd_reg
, nfc
->ctrl_reg
, false);
549 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
555 ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
556 int page_addr
, int len
)
561 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
562 column
, page_addr
, len
);
564 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
566 if (nfc
->small_page
) {
567 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
569 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
570 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
573 err
= ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
574 cmd_reg
, nfc
->ctrl_reg
, false);
576 nfc_debug_data("[data] ", nfc
->buf
, len
);
582 ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
589 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
591 ctrl_reg
= nfc
->ctrl_reg
;
592 if (nfc
->small_page
) {
593 /* override number of address cycles for the erase command */
594 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
595 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
596 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
597 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
598 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
599 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
600 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
603 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
604 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
605 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
607 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
608 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
610 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
611 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
612 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
613 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
615 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
616 ar934x_nfc_wait_dev_ready(nfc
);
620 ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
621 int page_addr
, int len
)
625 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
626 column
, page_addr
, len
);
628 nfc_debug_data("[data] ", nfc
->buf
, len
);
630 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
631 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
632 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
634 return ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
635 cmd_reg
, nfc
->ctrl_reg
, true);
639 ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
644 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
645 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
647 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
648 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
650 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
651 ar934x_nfc_wait_dev_ready(nfc
);
653 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
655 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
656 cmd_reg
, (status
& 0xff));
659 nfc
->buf
[0 ^ 3] = status
;
661 nfc
->buf
[0] = status
;
665 ar934x_nfc_cmdfunc(struct mtd_info
*mtd
, unsigned int command
, int column
,
668 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
669 struct nand_chip
*nand
= &nfc
->nand_chip
;
671 nfc
->read_id
= false;
672 if (command
!= NAND_CMD_PAGEPROG
)
677 ar934x_nfc_send_cmd(nfc
, command
);
680 case NAND_CMD_READID
:
682 ar934x_nfc_send_readid(nfc
, command
);
687 if (nfc
->small_page
) {
688 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
689 mtd
->writesize
+ mtd
->oobsize
);
691 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
692 mtd
->writesize
+ mtd
->oobsize
);
693 nfc
->buf_index
= column
;
694 nfc
->rndout_page_addr
= page_addr
;
695 nfc
->rndout_read_cmd
= command
;
699 case NAND_CMD_READOOB
:
701 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
705 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
706 mtd
->writesize
, page_addr
,
710 case NAND_CMD_RNDOUT
:
711 if (WARN_ON(nfc
->small_page
))
714 /* emulate subpage read */
715 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
716 nfc
->rndout_page_addr
,
717 mtd
->writesize
+ mtd
->oobsize
);
718 nfc
->buf_index
= column
;
721 case NAND_CMD_ERASE1
:
722 nfc
->erase1_page_addr
= page_addr
;
725 case NAND_CMD_ERASE2
:
726 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
729 case NAND_CMD_STATUS
:
730 ar934x_nfc_read_status(nfc
);
734 if (nfc
->small_page
) {
735 /* output read command */
736 if (column
>= mtd
->writesize
) {
737 column
-= mtd
->writesize
;
738 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
739 } else if (column
< 256) {
740 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
743 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
746 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
748 nfc
->seqin_column
= column
;
749 nfc
->seqin_page_addr
= page_addr
;
752 case NAND_CMD_PAGEPROG
:
753 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
754 /* the data is already written */
759 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
761 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
762 nfc
->seqin_page_addr
,
768 "unsupported command: %x, column:%d page_addr=%d\n",
769 command
, column
, page_addr
);
775 ar934x_nfc_dev_ready(struct mtd_info
*mtd
)
777 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
779 return __ar934x_nfc_dev_ready(nfc
);
783 ar934x_nfc_select_chip(struct mtd_info
*mtd
, int chip_no
)
785 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
787 if (nfc
->select_chip
)
788 nfc
->select_chip(chip_no
);
792 ar934x_nfc_read_byte(struct mtd_info
*mtd
)
794 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
797 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
799 if (nfc
->swap_dma
|| nfc
->read_id
)
800 data
= nfc
->buf
[nfc
->buf_index
^ 3];
802 data
= nfc
->buf
[nfc
->buf_index
];
810 ar934x_nfc_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
812 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
815 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
818 for (i
= 0; i
< len
; i
++) {
819 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
823 for (i
= 0; i
< len
; i
++) {
824 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
831 ar934x_nfc_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
833 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
837 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
839 buf_index
= nfc
->buf_index
;
841 if (nfc
->swap_dma
|| nfc
->read_id
) {
842 for (i
= 0; i
< len
; i
++) {
843 buf
[i
] = nfc
->buf
[buf_index
^ 3];
847 for (i
= 0; i
< len
; i
++) {
848 buf
[i
] = nfc
->buf
[buf_index
];
853 nfc
->buf_index
= buf_index
;
857 ar934x_nfc_enable_hwecc(struct ar934x_nfc
*nfc
)
859 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_ECC_EN
;
860 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
864 ar934x_nfc_disable_hwecc(struct ar934x_nfc
*nfc
)
866 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_ECC_EN
;
867 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
871 ar934x_nfc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
874 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
877 nfc_dbg(nfc
, "read_oob: page:%d\n", page
);
879 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
, page
,
884 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
890 ar934x_nfc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
893 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
895 nfc_dbg(nfc
, "write_oob: page:%d\n", page
);
897 memcpy(nfc
->buf
, chip
->oob_poi
, mtd
->oobsize
);
899 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, mtd
->writesize
,
904 ar934x_nfc_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
905 u8
*buf
, int oob_required
, int page
)
907 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
911 nfc_dbg(nfc
, "read_page_raw: page:%d oob:%d\n", page
, oob_required
);
913 len
= mtd
->writesize
;
917 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
, len
);
921 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
924 memcpy(chip
->oob_poi
, &nfc
->buf
[mtd
->writesize
], mtd
->oobsize
);
930 ar934x_nfc_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
931 u8
*buf
, int oob_required
, int page
)
933 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
935 int max_bitflips
= 0;
940 nfc_dbg(nfc
, "read_page: page:%d oob:%d\n", page
, oob_required
);
942 ar934x_nfc_enable_hwecc(nfc
);
943 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
,
945 ar934x_nfc_disable_hwecc(nfc
);
950 /* TODO: optimize to avoid memcpy */
951 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
953 /* read the ECC status */
954 ecc_ctrl
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_ECC_CTRL
);
955 ecc_failed
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_UNCORRECT
;
956 ecc_corrected
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_CORRECT
;
958 if (oob_required
|| ecc_failed
) {
959 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
,
965 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
970 * The hardware ECC engine reports uncorrectable errors
971 * on empty pages. Check the ECC bytes and the data. If
972 * both contains 0xff bytes only, dont report a failure.
974 * TODO: prebuild a buffer with 0xff bytes and use memcmp
975 * for better performance?
977 if (!is_all_ff(&nfc
->buf
[nfc
->ecc_oob_pos
], chip
->ecc
.total
) ||
978 !is_all_ff(buf
, mtd
->writesize
))
979 mtd
->ecc_stats
.failed
++;
980 } else if (ecc_corrected
) {
982 * The hardware does not report the exact count of the
983 * corrected bitflips, use assumptions based on the
986 if (ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_OVER
) {
988 * The number of corrected bitflips exceeds the
989 * threshold. Assume the maximum.
991 max_bitflips
= chip
->ecc
.strength
* chip
->ecc
.steps
;
993 max_bitflips
= nfc
->ecc_thres
* chip
->ecc
.steps
;
996 mtd
->ecc_stats
.corrected
+= max_bitflips
;
1003 ar934x_nfc_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1004 const u8
*buf
, int oob_required
, int page
)
1006 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1009 nfc_dbg(nfc
, "write_page_raw: page:%d oob:%d\n", page
, oob_required
);
1011 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
1012 len
= mtd
->writesize
;
1015 memcpy(&nfc
->buf
[mtd
->writesize
], chip
->oob_poi
, mtd
->oobsize
);
1016 len
+= mtd
->oobsize
;
1019 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
, len
);
1023 ar934x_nfc_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1024 const u8
*buf
, int oob_required
, int page
)
1026 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1029 nfc_dbg(nfc
, "write_page: page:%d oob:%d\n", page
, oob_required
);
1031 /* write OOB first */
1033 !is_all_ff(chip
->oob_poi
, mtd
->oobsize
)) {
1034 err
= ar934x_nfc_write_oob(mtd
, chip
, page
);
1039 /* TODO: optimize to avoid memcopy */
1040 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
1042 ar934x_nfc_enable_hwecc(nfc
);
1043 err
= ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
,
1045 ar934x_nfc_disable_hwecc(nfc
);
1051 ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
1053 struct ar934x_nfc_platform_data
*pdata
;
1055 pdata
= ar934x_nfc_get_platform_data(nfc
);
1056 if (pdata
->hw_reset
) {
1057 pdata
->hw_reset(true);
1058 pdata
->hw_reset(false);
1063 * TODO: make it configurable via platform data
1065 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
1066 AR934X_NFC_TIME_SEQ_DEFAULT
);
1067 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
1068 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
1069 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
1070 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
1072 /* disable WP on all chips, and select chip 0 */
1073 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
1075 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
1077 /* initialize Control register */
1078 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1079 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1081 if (nfc
->small_page
) {
1082 /* Setup generic sequence register for small page reads. */
1083 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
1084 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
1089 ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
1093 if (nfc
->select_chip
)
1094 nfc
->select_chip(-1);
1096 ctrl_reg
= nfc
->ctrl_reg
;
1097 ar934x_nfc_hw_init(nfc
);
1098 nfc
->ctrl_reg
= ctrl_reg
;
1100 if (nfc
->select_chip
)
1101 nfc
->select_chip(0);
1103 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
1107 ar934x_nfc_irq_handler(int irq
, void *data
)
1109 struct ar934x_nfc
*nfc
= data
;
1112 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1114 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
1116 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1118 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
1120 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
1122 nfc
->irq_status
= status
;
1123 nfc
->spurious_irq_expected
= true;
1124 wake_up(&nfc
->irq_waitq
);
1126 if (nfc
->spurious_irq_expected
) {
1127 nfc
->spurious_irq_expected
= false;
1129 dev_warn(nfc
->parent
, "spurious interrupt\n");
1137 ar934x_nfc_init_tail(struct mtd_info
*mtd
)
1139 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1140 struct nand_chip
*chip
= &nfc
->nand_chip
;
1145 switch (mtd
->oobsize
) {
1149 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
1153 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
1158 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1160 switch (mtd
->erasesize
/ mtd
->writesize
) {
1162 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
1166 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
1170 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
1174 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
1178 dev_err(nfc
->parent
, "unsupported block size: %u\n",
1179 mtd
->erasesize
/ mtd
->writesize
);
1183 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
1185 switch (mtd
->writesize
) {
1187 nfc
->small_page
= 1;
1188 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
1192 nfc
->small_page
= 1;
1193 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
1197 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
1201 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
1205 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
1209 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
1213 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
1217 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
1222 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
1224 if (nfc
->small_page
) {
1225 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
1227 if (chip
->chipsize
> (32 << 20)) {
1228 nfc
->addr_count0
= 4;
1229 nfc
->addr_count1
= 3;
1230 } else if (chip
->chipsize
> (2 << 16)) {
1231 nfc
->addr_count0
= 3;
1232 nfc
->addr_count1
= 2;
1234 nfc
->addr_count0
= 2;
1235 nfc
->addr_count1
= 1;
1238 if (chip
->chipsize
> (128 << 20)) {
1239 nfc
->addr_count0
= 5;
1240 nfc
->addr_count1
= 3;
1241 } else if (chip
->chipsize
> (8 << 16)) {
1242 nfc
->addr_count0
= 4;
1243 nfc
->addr_count1
= 2;
1245 nfc
->addr_count0
= 3;
1246 nfc
->addr_count1
= 1;
1250 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
1251 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
1253 nfc
->ctrl_reg
= ctrl
;
1254 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1256 ar934x_nfc_free_buf(nfc
);
1257 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1262 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1263 static struct nand_ecclayout ar934x_nfc_oob_64_hwecc
= {
1266 20, 21, 22, 23, 24, 25, 26,
1267 27, 28, 29, 30, 31, 32, 33,
1268 34, 35, 36, 37, 38, 39, 40,
1269 41, 42, 43, 44, 45, 46, 47,
1285 static int ar934x_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1286 struct mtd_oob_region
*oobregion
)
1291 oobregion
->offset
= 20;
1292 oobregion
->length
= 28;
1297 static int ar934x_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
1298 struct mtd_oob_region
*oobregion
)
1302 oobregion
->offset
= 4;
1303 oobregion
->length
= 16;
1306 oobregion
->offset
= 48;
1307 oobregion
->length
= 16;
1314 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops
= {
1315 .ecc
= ar934x_nfc_ooblayout_ecc
,
1316 .free
= ar934x_nfc_ooblayout_free
,
1321 ar934x_nfc_setup_hwecc(struct ar934x_nfc
*nfc
)
1323 struct nand_chip
*nand
= &nfc
->nand_chip
;
1324 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
1327 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
1328 struct mtd_oob_region oobregion
;
1331 if (!IS_ENABLED(CONFIG_MTD_NAND_AR934X_HW_ECC
)) {
1332 dev_err(nfc
->parent
, "hardware ECC support is disabled\n");
1336 switch (mtd
->writesize
) {
1339 * Writing a subpage separately is not supported, because
1340 * the controller only does ECC on full-page accesses.
1342 nand
->options
= NAND_NO_SUBPAGE_WRITE
;
1344 nand
->ecc
.size
= 512;
1345 nand
->ecc
.bytes
= 7;
1346 nand
->ecc
.strength
= 4;
1347 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1348 nand
->ecc
.layout
= &ar934x_nfc_oob_64_hwecc
;
1350 mtd_set_ooblayout(mtd
, &ar934x_nfc_ecclayout_ops
);
1355 dev_err(nfc
->parent
,
1356 "hardware ECC is not available for %d byte pages\n",
1361 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1362 BUG_ON(!nand
->ecc
.layout
);
1364 BUG_ON(!mtd
->ooblayout
->ecc
);
1367 switch (nand
->ecc
.strength
) {
1369 ecc_cap
= AR934X_NFC_ECC_CTRL_ECC_CAP_4
;
1374 dev_err(nfc
->parent
, "unsupported ECC strength %u\n",
1375 nand
->ecc
.strength
);
1379 nfc
->ecc_thres
= ecc_thres
;
1380 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1381 nfc
->ecc_oob_pos
= nand
->ecc
.layout
->eccpos
[0];
1383 mtd
->ooblayout
->ecc(mtd
, 0, &oobregion
);
1384 nfc
->ecc_oob_pos
= oobregion
.offset
;
1387 nfc
->ecc_ctrl_reg
= ecc_cap
<< AR934X_NFC_ECC_CTRL_ECC_CAP_S
;
1388 nfc
->ecc_ctrl_reg
|= ecc_thres
<< AR934X_NFC_ECC_CTRL_ERR_THRES_S
;
1390 nfc
->ecc_offset_reg
= mtd
->writesize
+ nfc
->ecc_oob_pos
;
1392 nand
->ecc
.mode
= NAND_ECC_HW
;
1393 nand
->ecc
.read_page
= ar934x_nfc_read_page
;
1394 nand
->ecc
.read_page_raw
= ar934x_nfc_read_page_raw
;
1395 nand
->ecc
.write_page
= ar934x_nfc_write_page
;
1396 nand
->ecc
.write_page_raw
= ar934x_nfc_write_page_raw
;
1397 nand
->ecc
.read_oob
= ar934x_nfc_read_oob
;
1398 nand
->ecc
.write_oob
= ar934x_nfc_write_oob
;
1404 ar934x_nfc_probe(struct platform_device
*pdev
)
1406 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
1407 struct ar934x_nfc_platform_data
*pdata
;
1408 struct ar934x_nfc
*nfc
;
1409 struct resource
*res
;
1410 struct mtd_info
*mtd
;
1411 struct nand_chip
*nand
;
1412 struct mtd_part_parser_data ppdata
;
1415 pdata
= pdev
->dev
.platform_data
;
1416 if (pdata
== NULL
) {
1417 dev_err(&pdev
->dev
, "no platform data defined\n");
1421 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1423 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1427 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1429 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1433 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1434 if (IS_ERR(nfc
->base
)) {
1435 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1436 return PTR_ERR(nfc
->base
);
1439 nfc
->irq
= platform_get_irq(pdev
, 0);
1441 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1445 init_waitqueue_head(&nfc
->irq_waitq
);
1446 ret
= request_irq(nfc
->irq
, ar934x_nfc_irq_handler
, 0,
1447 dev_name(&pdev
->dev
), nfc
);
1449 dev_err(&pdev
->dev
, "requast_irq failed, err:%d\n", ret
);
1453 nfc
->parent
= &pdev
->dev
;
1454 nfc
->select_chip
= pdata
->select_chip
;
1455 nfc
->swap_dma
= pdata
->swap_dma
;
1457 nand
= &nfc
->nand_chip
;
1458 mtd
= ar934x_nfc_to_mtd(nfc
);
1460 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1463 mtd
->owner
= THIS_MODULE
;
1465 mtd
->name
= pdata
->name
;
1467 mtd
->name
= dev_name(&pdev
->dev
);
1469 nand
->chip_delay
= 25;
1471 nand
->dev_ready
= ar934x_nfc_dev_ready
;
1472 nand
->cmdfunc
= ar934x_nfc_cmdfunc
;
1473 nand
->read_byte
= ar934x_nfc_read_byte
;
1474 nand
->write_buf
= ar934x_nfc_write_buf
;
1475 nand
->read_buf
= ar934x_nfc_read_buf
;
1476 nand
->select_chip
= ar934x_nfc_select_chip
;
1478 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1482 platform_set_drvdata(pdev
, nfc
);
1484 ar934x_nfc_hw_init(nfc
);
1486 ret
= nand_scan_ident(mtd
, 1, NULL
);
1488 dev_err(&pdev
->dev
, "nand_scan_ident failed, err:%d\n", ret
);
1492 ret
= ar934x_nfc_init_tail(mtd
);
1494 dev_err(&pdev
->dev
, "init tail failed, err:%d\n", ret
);
1498 if (pdata
->scan_fixup
) {
1499 ret
= pdata
->scan_fixup(mtd
);
1504 switch (pdata
->ecc_mode
) {
1505 case AR934X_NFC_ECC_SOFT
:
1506 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1507 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
1508 nand
->ecc
.algo
= NAND_ECC_HAMMING
;
1512 case AR934X_NFC_ECC_SOFT_BCH
:
1513 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1514 nand
->ecc
.mode
= NAND_ECC_SOFT_BCH
;
1516 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1517 nand
->ecc
.algo
= NAND_ECC_BCH
;
1521 case AR934X_NFC_ECC_HW
:
1522 ret
= ar934x_nfc_setup_hwecc(nfc
);
1529 dev_err(nfc
->parent
, "unknown ECC mode %d\n", pdata
->ecc_mode
);
1533 ret
= nand_scan_tail(mtd
);
1535 dev_err(&pdev
->dev
, "scan tail failed, err:%d\n", ret
);
1539 memset(&ppdata
, '\0', sizeof(ppdata
));
1540 ret
= mtd_device_parse_register(mtd
, part_probes
, &ppdata
,
1541 pdata
->parts
, pdata
->nr_parts
);
1543 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1550 ar934x_nfc_free_buf(nfc
);
1552 free_irq(nfc
->irq
, nfc
);
1557 ar934x_nfc_remove(struct platform_device
*pdev
)
1559 struct ar934x_nfc
*nfc
;
1560 struct mtd_info
*mtd
;
1562 nfc
= platform_get_drvdata(pdev
);
1564 mtd
= ar934x_nfc_to_mtd(nfc
);
1566 ar934x_nfc_free_buf(nfc
);
1567 free_irq(nfc
->irq
, nfc
);
1573 static struct platform_driver ar934x_nfc_driver
= {
1574 .probe
= ar934x_nfc_probe
,
1575 .remove
= ar934x_nfc_remove
,
1577 .name
= AR934X_NFC_DRIVER_NAME
,
1578 .owner
= THIS_MODULE
,
1582 module_platform_driver(ar934x_nfc_driver
);
1584 MODULE_LICENSE("GPL v2");
1585 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1586 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1587 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);