2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
22 #include <linux/platform/ar934x_nfc.h>
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
125 /* default timing values */
126 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
130 #define AR934X_NFC_ID_BUF_SIZE 8
131 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133 #define AR934X_NFC_DONE_TIMEOUT 1000
134 #define AR934X_NFC_DMA_RETRIES 20
136 #define AR934X_NFC_USE_IRQ true
137 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
139 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
141 #undef AR934X_NFC_DEBUG_DATA
142 #undef AR934X_NFC_DEBUG
146 static inline __attribute__ ((format (printf
, 2, 3)))
147 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
151 #ifdef AR934X_NFC_DEBUG
152 #define nfc_dbg(_nfc, fmt, ...) \
153 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
155 #define nfc_dbg(_nfc, fmt, ...) \
156 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
157 #endif /* AR934X_NFC_DEBUG */
159 #ifdef AR934X_NFC_DEBUG_DATA
161 nfc_debug_data(const char *label
, void *data
, int len
)
163 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
168 nfc_debug_data(const char *label
, void *data
, int len
) {}
169 #endif /* AR934X_NFC_DEBUG_DATA */
173 struct nand_chip nand_chip
;
174 struct device
*parent
;
176 void (*select_chip
)(int chip_no
);
179 wait_queue_head_t irq_waitq
;
181 bool spurious_irq_expected
;
186 unsigned int addr_count0
;
187 unsigned int addr_count1
;
191 unsigned int buf_size
;
196 int erase1_page_addr
;
198 int rndout_page_addr
;
206 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
209 ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
211 __raw_writel(val
, nfc
->base
+ reg
);
215 ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
217 return __raw_readl(nfc
->base
+ reg
);
220 static inline struct ar934x_nfc_platform_data
*
221 ar934x_nfc_get_platform_data(struct ar934x_nfc
*nfc
)
223 return nfc
->parent
->platform_data
;
227 ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
229 return container_of(mtd
, struct ar934x_nfc
, mtd
);
232 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
234 return AR934X_NFC_USE_IRQ
;
237 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
241 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
243 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
247 __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
251 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
252 return (status
& 0xff) == 0xff;
256 __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
260 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
261 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
265 ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
267 unsigned long timeout
;
269 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
271 if (__ar934x_nfc_dev_ready(nfc
))
273 } while time_before(jiffies
, timeout
);
275 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
276 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
277 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
282 ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
284 unsigned long timeout
;
286 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
288 if (__ar934x_nfc_is_dma_ready(nfc
))
290 } while time_before(jiffies
, timeout
);
292 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
293 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
298 ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
303 timeout
= wait_event_timeout(nfc
->irq_waitq
,
304 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
305 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
309 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
310 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
312 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
315 "timeout waiting for interrupt, status:%08x\n",
325 ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
329 if (ar934x_nfc_use_irq(nfc
))
330 ret
= ar934x_nfc_wait_irq(nfc
);
332 ret
= ar934x_nfc_wait_dev_ready(nfc
);
337 return ar934x_nfc_wait_dma_ready(nfc
);
341 ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
343 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
344 &nfc
->buf_dma
, GFP_KERNEL
);
345 if (nfc
->buf
== NULL
) {
346 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
350 nfc
->buf_size
= size
;
351 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
357 ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
359 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
363 ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
364 u32
*addr0
, u32
*addr1
)
373 a0
= (page_addr
& 0xffff) << 16;
374 a1
= (page_addr
>> 16) & 0xf;
375 } else if (page_addr
!= -1) {
376 /* SEQIN, READ0, etc.. */
378 /* TODO: handle 16bit bus width */
379 if (nfc
->small_page
) {
381 a0
|= (page_addr
& 0xff) << 8;
382 a0
|= ((page_addr
>> 8) & 0xff) << 16;
383 a0
|= ((page_addr
>> 16) & 0xff) << 24;
385 a0
= column
& 0x0FFF;
386 a0
|= (page_addr
& 0xffff) << 16;
388 if (nfc
->addr_count0
> 4)
389 a1
= (page_addr
>> 16) & 0xf;
398 ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
402 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
403 AR934X_NFC_CMD_SEQ_1C
;
404 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
406 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
407 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
409 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
410 ar934x_nfc_wait_dev_ready(nfc
);
414 ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
, int page_addr
,
415 int len
, u32 cmd_reg
, u32 ctrl_reg
, bool write
)
425 if (WARN_ON(len
> nfc
->buf_size
))
426 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
, nfc
->buf_size
);
429 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
432 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
433 dir
= DMA_FROM_DEVICE
;
436 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
438 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
439 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
440 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
442 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
443 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
445 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
446 (write
) ? "write" : "read",
447 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
450 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
451 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
452 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
453 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
454 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
455 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
456 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
457 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
459 if (ar934x_nfc_use_irq(nfc
)) {
460 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, AR934X_NFC_IRQ_MASK
);
462 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
465 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
466 err
= ar934x_nfc_wait_done(nfc
);
468 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
469 (write
) ? "write" : "read", page_addr
);
471 ar934x_nfc_restart(nfc
);
472 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
475 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
476 (write
) ? "write" : "read", page_addr
);
481 ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
485 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
487 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
488 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
490 ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
, cmd_reg
,
491 nfc
->ctrl_reg
, false);
493 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
497 ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
498 int page_addr
, int len
)
502 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
503 column
, page_addr
, len
);
505 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
507 if (nfc
->small_page
) {
508 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
510 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
511 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
514 ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
515 cmd_reg
, nfc
->ctrl_reg
, false);
517 nfc_debug_data("[data] ", nfc
->buf
, len
);
521 ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
528 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
530 ctrl_reg
= nfc
->ctrl_reg
;
531 if (nfc
->small_page
) {
532 /* override number of address cycles for the erase command */
533 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
534 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
535 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
536 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
537 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
538 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
539 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
542 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
543 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
544 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
546 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
547 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
549 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
550 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
551 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
552 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
554 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
555 ar934x_nfc_wait_dev_ready(nfc
);
559 ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
, int column
,
560 int page_addr
, int len
)
564 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
565 column
, page_addr
, len
);
567 nfc_debug_data("[data] ", nfc
->buf
, len
);
569 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
570 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
571 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
573 ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
574 cmd_reg
, nfc
->ctrl_reg
, true);
578 ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
583 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
584 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
586 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
587 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
589 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
590 ar934x_nfc_wait_dev_ready(nfc
);
592 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
594 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
595 cmd_reg
, (status
& 0xff));
598 nfc
->buf
[0 ^ 3] = status
;
600 nfc
->buf
[0] = status
;
604 ar934x_nfc_cmdfunc(struct mtd_info
*mtd
, unsigned int command
, int column
,
607 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
609 nfc
->read_id
= false;
610 if (command
!= NAND_CMD_PAGEPROG
)
615 ar934x_nfc_send_cmd(nfc
, command
);
618 case NAND_CMD_READID
:
620 ar934x_nfc_send_readid(nfc
, command
);
625 if (nfc
->small_page
) {
626 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
627 mtd
->writesize
+ mtd
->oobsize
);
629 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
630 mtd
->writesize
+ mtd
->oobsize
);
631 nfc
->buf_index
= column
;
632 nfc
->rndout_page_addr
= page_addr
;
633 nfc
->rndout_read_cmd
= command
;
637 case NAND_CMD_READOOB
:
639 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
643 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
644 mtd
->writesize
, page_addr
,
648 case NAND_CMD_RNDOUT
:
649 if (WARN_ON(nfc
->small_page
))
652 /* emulate subpage read */
653 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
654 nfc
->rndout_page_addr
,
655 mtd
->writesize
+ mtd
->oobsize
);
656 nfc
->buf_index
= column
;
659 case NAND_CMD_ERASE1
:
660 nfc
->erase1_page_addr
= page_addr
;
663 case NAND_CMD_ERASE2
:
664 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
667 case NAND_CMD_STATUS
:
668 ar934x_nfc_read_status(nfc
);
672 if (nfc
->small_page
) {
673 /* output read command */
674 if (column
>= mtd
->writesize
) {
675 column
-= mtd
->writesize
;
676 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
677 } else if (column
< 256) {
678 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
681 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
684 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
686 nfc
->seqin_column
= column
;
687 nfc
->seqin_page_addr
= page_addr
;
690 case NAND_CMD_PAGEPROG
:
692 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
694 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
695 nfc
->seqin_page_addr
,
701 "unsupported command: %x, column:%d page_addr=%d\n",
702 command
, column
, page_addr
);
708 ar934x_nfc_dev_ready(struct mtd_info
*mtd
)
710 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
712 return __ar934x_nfc_dev_ready(nfc
);
716 ar934x_nfc_select_chip(struct mtd_info
*mtd
, int chip_no
)
718 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
720 if (nfc
->select_chip
)
721 nfc
->select_chip(chip_no
);
725 ar934x_nfc_read_byte(struct mtd_info
*mtd
)
727 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
730 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
732 if (nfc
->swap_dma
|| nfc
->read_id
)
733 data
= nfc
->buf
[nfc
->buf_index
^ 3];
735 data
= nfc
->buf
[nfc
->buf_index
];
743 ar934x_nfc_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
745 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
748 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
751 for (i
= 0; i
< len
; i
++) {
752 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
756 for (i
= 0; i
< len
; i
++) {
757 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
764 ar934x_nfc_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
766 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
770 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
772 buf_index
= nfc
->buf_index
;
774 if (nfc
->swap_dma
|| nfc
->read_id
) {
775 for (i
= 0; i
< len
; i
++) {
776 buf
[i
] = nfc
->buf
[buf_index
^ 3];
780 for (i
= 0; i
< len
; i
++) {
781 buf
[i
] = nfc
->buf
[buf_index
];
786 nfc
->buf_index
= buf_index
;
790 ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
792 struct ar934x_nfc_platform_data
*pdata
;
794 pdata
= ar934x_nfc_get_platform_data(nfc
);
795 if (pdata
->hw_reset
) {
796 pdata
->hw_reset(true);
797 pdata
->hw_reset(false);
802 * TODO: make it configurable via platform data
804 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
805 AR934X_NFC_TIME_SEQ_DEFAULT
);
806 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
807 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
808 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
809 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
811 /* disable WP on all chips, and select chip 0 */
812 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
814 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
816 /* initialize Control register */
817 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
818 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
820 if (nfc
->small_page
) {
821 /* Setup generic sequence register for small page reads. */
822 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
823 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
828 ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
832 if (nfc
->select_chip
)
833 nfc
->select_chip(-1);
835 ctrl_reg
= nfc
->ctrl_reg
;
836 ar934x_nfc_hw_init(nfc
);
837 nfc
->ctrl_reg
= ctrl_reg
;
839 if (nfc
->select_chip
)
842 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
846 ar934x_nfc_irq_handler(int irq
, void *data
)
848 struct ar934x_nfc
*nfc
= data
;
851 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
853 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
855 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
857 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
859 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
861 nfc
->irq_status
= status
;
862 nfc
->spurious_irq_expected
= true;
863 wake_up(&nfc
->irq_waitq
);
865 if (nfc
->spurious_irq_expected
) {
866 nfc
->spurious_irq_expected
= false;
868 dev_warn(nfc
->parent
, "spurious interrupt\n");
876 ar934x_nfc_init_tail(struct mtd_info
*mtd
)
878 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
879 struct nand_chip
*chip
= &nfc
->nand_chip
;
884 switch (mtd
->oobsize
) {
888 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
892 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
897 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
899 switch (mtd
->erasesize
/ mtd
->writesize
) {
901 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
905 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
909 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
913 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
917 dev_err(nfc
->parent
, "unsupported block size: %u\n",
918 mtd
->erasesize
/ mtd
->writesize
);
922 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
924 switch (mtd
->writesize
) {
927 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
932 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
936 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
940 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
944 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
948 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
952 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
956 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
961 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
963 if (nfc
->small_page
) {
964 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
966 if (chip
->chipsize
> (32 << 20)) {
967 nfc
->addr_count0
= 4;
968 nfc
->addr_count1
= 3;
969 } else if (chip
->chipsize
> (2 << 16)) {
970 nfc
->addr_count0
= 3;
971 nfc
->addr_count1
= 2;
973 nfc
->addr_count0
= 2;
974 nfc
->addr_count1
= 1;
977 if (chip
->chipsize
> (128 << 20)) {
978 nfc
->addr_count0
= 5;
979 nfc
->addr_count1
= 3;
980 } else if (chip
->chipsize
> (8 << 16)) {
981 nfc
->addr_count0
= 4;
982 nfc
->addr_count1
= 2;
984 nfc
->addr_count0
= 3;
985 nfc
->addr_count1
= 1;
989 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
990 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
992 nfc
->ctrl_reg
= ctrl
;
993 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
995 ar934x_nfc_free_buf(nfc
);
996 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1002 ar934x_nfc_probe(struct platform_device
*pdev
)
1004 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
1005 struct ar934x_nfc_platform_data
*pdata
;
1006 struct ar934x_nfc
*nfc
;
1007 struct resource
*res
;
1008 struct mtd_info
*mtd
;
1009 struct nand_chip
*nand
;
1010 struct mtd_part_parser_data ppdata
;
1013 pdata
= pdev
->dev
.platform_data
;
1014 if (pdata
== NULL
) {
1015 dev_err(&pdev
->dev
, "no platform data defined\n");
1019 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1021 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1025 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1027 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1031 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1032 if (IS_ERR(nfc
->base
)) {
1033 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1034 return PTR_ERR(nfc
->base
);
1037 nfc
->irq
= platform_get_irq(pdev
, 0);
1039 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1043 init_waitqueue_head(&nfc
->irq_waitq
);
1044 ret
= request_irq(nfc
->irq
, ar934x_nfc_irq_handler
, IRQF_DISABLED
,
1045 dev_name(&pdev
->dev
), nfc
);
1047 dev_err(&pdev
->dev
, "requast_irq failed, err:%d\n", ret
);
1051 nfc
->parent
= &pdev
->dev
;
1052 nfc
->select_chip
= pdata
->select_chip
;
1053 nfc
->swap_dma
= pdata
->swap_dma
;
1055 nand
= &nfc
->nand_chip
;
1059 mtd
->owner
= THIS_MODULE
;
1061 mtd
->name
= pdata
->name
;
1063 mtd
->name
= dev_name(&pdev
->dev
);
1065 nand
->chip_delay
= 25;
1066 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1068 nand
->dev_ready
= ar934x_nfc_dev_ready
;
1069 nand
->cmdfunc
= ar934x_nfc_cmdfunc
;
1070 nand
->read_byte
= ar934x_nfc_read_byte
;
1071 nand
->write_buf
= ar934x_nfc_write_buf
;
1072 nand
->read_buf
= ar934x_nfc_read_buf
;
1073 nand
->select_chip
= ar934x_nfc_select_chip
;
1075 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1079 platform_set_drvdata(pdev
, nfc
);
1081 ar934x_nfc_hw_init(nfc
);
1083 ret
= nand_scan_ident(mtd
, 1, NULL
);
1085 dev_err(&pdev
->dev
, "nand_scan_ident failed, err:%d\n", ret
);
1089 ret
= ar934x_nfc_init_tail(mtd
);
1091 dev_err(&pdev
->dev
, "init tail failed, err:%d\n", ret
);
1095 if (pdata
->scan_fixup
) {
1096 ret
= pdata
->scan_fixup(mtd
);
1101 ret
= nand_scan_tail(mtd
);
1103 dev_err(&pdev
->dev
, "scan tail failed, err:%d\n", ret
);
1107 memset(&ppdata
, '\0', sizeof(ppdata
));
1108 ret
= mtd_device_parse_register(mtd
, part_probes
, &ppdata
,
1109 pdata
->parts
, pdata
->nr_parts
);
1111 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1118 ar934x_nfc_free_buf(nfc
);
1120 free_irq(nfc
->irq
, nfc
);
1125 ar934x_nfc_remove(struct platform_device
*pdev
)
1127 struct ar934x_nfc
*nfc
;
1129 nfc
= platform_get_drvdata(pdev
);
1131 nand_release(&nfc
->mtd
);
1132 ar934x_nfc_free_buf(nfc
);
1133 free_irq(nfc
->irq
, nfc
);
1139 static struct platform_driver ar934x_nfc_driver
= {
1140 .probe
= ar934x_nfc_probe
,
1141 .remove
= ar934x_nfc_remove
,
1143 .name
= AR934X_NFC_DRIVER_NAME
,
1144 .owner
= THIS_MODULE
,
1148 module_platform_driver(ar934x_nfc_driver
);
1150 MODULE_LICENSE("GPL v2");
1151 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1152 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1153 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);