2 * NAND flash driver for the MikroTik RouterBOARD 91x series
4 * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/spinlock.h>
13 #include <linux/module.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/gpio.h>
21 #include <linux/platform_data/rb91x_nand.h>
22 #include <linux/version.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/ath79.h>
27 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
29 #define RB91X_NAND_NRWE BIT(12)
31 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
32 BIT(13) | BIT(14) | BIT(15))
34 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
35 #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
37 #define RB91X_NAND_LOW_DATA_MASK 0x1f
38 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
39 #define RB91X_NAND_HIGH_DATA_SHIFT 8
41 struct rb91x_nand_info
{
42 struct nand_chip chip
;
55 static inline struct rb91x_nand_info
*mtd_to_rbinfo(struct mtd_info
*mtd
)
57 return container_of(mtd
, struct rb91x_nand_info
, mtd
);
60 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
62 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
63 * will not be able to find the kernel that we load.
65 static struct nand_ecclayout rb91x_nand_ecclayout
= {
67 .eccpos
= { 8, 9, 10, 13, 14, 15 },
69 .oobfree
= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
74 static int rb91x_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
75 struct mtd_oob_region
*oobregion
)
79 oobregion
->offset
= 8;
80 oobregion
->length
= 3;
83 oobregion
->offset
= 13;
84 oobregion
->length
= 3;
91 static int rb91x_ooblayout_free(struct mtd_info
*mtd
, int section
,
92 struct mtd_oob_region
*oobregion
)
96 oobregion
->offset
= 0;
97 oobregion
->length
= 4;
100 oobregion
->offset
= 4;
101 oobregion
->length
= 1;
104 oobregion
->offset
= 6;
105 oobregion
->length
= 2;
108 oobregion
->offset
= 11;
109 oobregion
->length
= 2;
116 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops
= {
117 .ecc
= rb91x_ooblayout_ecc
,
118 .free
= rb91x_ooblayout_free
,
122 static struct mtd_partition rb91x_nand_partitions
[] = {
126 .size
= (256 * 1024),
127 .mask_flags
= MTD_WRITEABLE
,
130 .offset
= (256 * 1024),
131 .size
= (4 * 1024 * 1024) - (256 * 1024),
134 .offset
= MTDPART_OFS_NXTBLK
,
135 .size
= MTDPART_SIZ_FULL
,
139 static void rb91x_nand_write(struct rb91x_nand_info
*rbni
,
143 void __iomem
*base
= ath79_gpio_base
;
149 /* enable the latch */
150 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
152 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
153 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
155 /* set data lines to output mode */
156 __raw_writel(oe_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
),
157 base
+ AR71XX_GPIO_REG_OE
);
159 out
= out_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
);
160 for (i
= 0; i
!= len
; i
++) {
163 data
= (buf
[i
] & RB91X_NAND_HIGH_DATA_MASK
) <<
164 RB91X_NAND_HIGH_DATA_SHIFT
;
165 data
|= buf
[i
] & RB91X_NAND_LOW_DATA_MASK
;
167 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
169 /* deactivate WE line */
170 data
|= RB91X_NAND_NRWE
;
171 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
173 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
176 /* restore registers */
177 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
178 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
180 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
182 /* disable the latch */
183 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
186 static void rb91x_nand_read(struct rb91x_nand_info
*rbni
,
190 void __iomem
*base
= ath79_gpio_base
;
195 /* enable read mode */
196 gpio_set_value_cansleep(rbni
->gpio_read
, 1);
199 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
202 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
203 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
205 /* set data lines to input mode */
206 __raw_writel(oe_reg
| RB91X_NAND_DATA_BITS
,
207 base
+ AR71XX_GPIO_REG_OE
);
209 for (i
= 0; i
< len
; i
++) {
213 /* activate RE line */
214 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_CLEAR
);
216 __raw_readl(base
+ AR71XX_GPIO_REG_CLEAR
);
218 /* read input lines */
219 in
= __raw_readl(base
+ AR71XX_GPIO_REG_IN
);
221 /* deactivate RE line */
222 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_SET
);
224 data
= (in
& RB91X_NAND_LOW_DATA_MASK
);
225 data
|= (in
>> RB91X_NAND_HIGH_DATA_SHIFT
) &
226 RB91X_NAND_HIGH_DATA_MASK
;
231 /* restore registers */
232 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
233 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
235 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
238 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
240 /* disable read mode */
241 gpio_set_value_cansleep(rbni
->gpio_read
, 0);
244 static int rb91x_nand_dev_ready(struct mtd_info
*mtd
)
246 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
248 return gpio_get_value_cansleep(rbni
->gpio_rdy
);
251 static void rb91x_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
254 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
256 if (ctrl
& NAND_CTRL_CHANGE
) {
257 gpio_set_value_cansleep(rbni
->gpio_cle
,
258 (ctrl
& NAND_CLE
) ? 1 : 0);
259 gpio_set_value_cansleep(rbni
->gpio_ale
,
260 (ctrl
& NAND_ALE
) ? 1 : 0);
261 gpio_set_value_cansleep(rbni
->gpio_nce
,
262 (ctrl
& NAND_NCE
) ? 0 : 1);
265 if (cmd
!= NAND_CMD_NONE
) {
268 rb91x_nand_write(rbni
, &t
, 1);
272 static u8
rb91x_nand_read_byte(struct mtd_info
*mtd
)
274 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
277 rb91x_nand_read(rbni
, &data
, 1);
282 static void rb91x_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
284 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
286 rb91x_nand_read(rbni
, buf
, len
);
289 static void rb91x_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
291 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
293 rb91x_nand_write(rbni
, buf
, len
);
296 static int rb91x_nand_gpio_init(struct rb91x_nand_info
*info
)
301 * Ensure that the LATCH is disabled before initializing
304 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nle
,
305 GPIOF_OUT_INIT_HIGH
, "LATCH enable");
309 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nce
,
310 GPIOF_OUT_INIT_HIGH
, "NAND nCE");
314 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nrw
,
315 GPIOF_OUT_INIT_HIGH
, "NAND nRW");
319 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_cle
,
320 GPIOF_OUT_INIT_LOW
, "NAND CLE");
324 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_ale
,
325 GPIOF_OUT_INIT_LOW
, "NAND ALE");
329 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_read
,
330 GPIOF_OUT_INIT_LOW
, "NAND READ");
334 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_rdy
,
335 GPIOF_IN
, "NAND RDY");
339 static int rb91x_nand_probe(struct platform_device
*pdev
)
341 struct rb91x_nand_info
*rbni
;
342 struct rb91x_nand_platform_data
*pdata
;
345 pr_info(DRV_DESC
"\n");
347 pdata
= dev_get_platdata(&pdev
->dev
);
351 rbni
= devm_kzalloc(&pdev
->dev
, sizeof(*rbni
), GFP_KERNEL
);
355 rbni
->dev
= &pdev
->dev
;
356 rbni
->gpio_nce
= pdata
->gpio_nce
;
357 rbni
->gpio_ale
= pdata
->gpio_ale
;
358 rbni
->gpio_cle
= pdata
->gpio_cle
;
359 rbni
->gpio_read
= pdata
->gpio_read
;
360 rbni
->gpio_nrw
= pdata
->gpio_nrw
;
361 rbni
->gpio_rdy
= pdata
->gpio_rdy
;
362 rbni
->gpio_nle
= pdata
->gpio_nle
;
364 rbni
->chip
.priv
= &rbni
;
365 rbni
->mtd
.priv
= &rbni
->chip
;
366 rbni
->mtd
.owner
= THIS_MODULE
;
368 rbni
->chip
.cmd_ctrl
= rb91x_nand_cmd_ctrl
;
369 rbni
->chip
.dev_ready
= rb91x_nand_dev_ready
;
370 rbni
->chip
.read_byte
= rb91x_nand_read_byte
;
371 rbni
->chip
.write_buf
= rb91x_nand_write_buf
;
372 rbni
->chip
.read_buf
= rb91x_nand_read_buf
;
374 rbni
->chip
.chip_delay
= 25;
375 rbni
->chip
.ecc
.mode
= NAND_ECC_SOFT
;
376 rbni
->chip
.options
= NAND_NO_SUBPAGE_WRITE
;
378 platform_set_drvdata(pdev
, rbni
);
380 ret
= rb91x_nand_gpio_init(rbni
);
384 ret
= nand_scan_ident(&rbni
->mtd
, 1, NULL
);
388 if (rbni
->mtd
.writesize
== 512)
389 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
390 rbni
->chip
.ecc
.layout
= &rb91x_nand_ecclayout
;
392 mtd_set_ooblayout(&rbni
->mtd
, &rb91x_nand_ecclayout_ops
);
395 ret
= nand_scan_tail(&rbni
->mtd
);
399 ret
= mtd_device_register(&rbni
->mtd
, rb91x_nand_partitions
,
400 ARRAY_SIZE(rb91x_nand_partitions
));
402 goto err_release_nand
;
407 nand_release(&rbni
->mtd
);
411 static int rb91x_nand_remove(struct platform_device
*pdev
)
413 struct rb91x_nand_info
*info
= platform_get_drvdata(pdev
);
415 nand_release(&info
->mtd
);
420 static struct platform_driver rb91x_nand_driver
= {
421 .probe
= rb91x_nand_probe
,
422 .remove
= rb91x_nand_remove
,
424 .name
= RB91X_NAND_DRIVER_NAME
,
425 .owner
= THIS_MODULE
,
429 module_platform_driver(rb91x_nand_driver
);
431 MODULE_DESCRIPTION(DRV_DESC
);
432 MODULE_VERSION(DRV_VERSION
);
433 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
434 MODULE_LICENSE("GPL v2");