2 * NAND flash driver for the MikroTik RouterBOARD 91x series
4 * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/version.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/module.h>
15 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
16 #include <linux/mtd/nand.h>
18 #include <linux/mtd/rawnand.h>
19 #endif#include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_data/rb91x_nand.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
28 #include <asm/mach-ath79/ath79.h>
30 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
32 #define RB91X_NAND_NRWE BIT(12)
34 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
35 BIT(13) | BIT(14) | BIT(15))
37 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
38 #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
40 #define RB91X_NAND_LOW_DATA_MASK 0x1f
41 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
42 #define RB91X_NAND_HIGH_DATA_SHIFT 8
44 struct rb91x_nand_info
{
45 struct nand_chip chip
;
46 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
60 static inline struct rb91x_nand_info
*mtd_to_rbinfo(struct mtd_info
*mtd
)
62 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
63 return container_of(mtd
, struct rb91x_nand_info
, mtd
);
65 struct nand_chip
*chip
= mtd_to_nand(mtd
);
67 return container_of(chip
, struct rb91x_nand_info
, chip
);
71 static struct mtd_info
*rbinfo_to_mtd(struct rb91x_nand_info
*nfc
)
73 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
76 return nand_to_mtd(&nfc
->chip
);
81 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
83 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
84 * will not be able to find the kernel that we load.
86 static struct nand_ecclayout rb91x_nand_ecclayout
= {
88 .eccpos
= { 8, 9, 10, 13, 14, 15 },
90 .oobfree
= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
95 static int rb91x_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
96 struct mtd_oob_region
*oobregion
)
100 oobregion
->offset
= 8;
101 oobregion
->length
= 3;
104 oobregion
->offset
= 13;
105 oobregion
->length
= 3;
112 static int rb91x_ooblayout_free(struct mtd_info
*mtd
, int section
,
113 struct mtd_oob_region
*oobregion
)
117 oobregion
->offset
= 0;
118 oobregion
->length
= 4;
121 oobregion
->offset
= 4;
122 oobregion
->length
= 1;
125 oobregion
->offset
= 6;
126 oobregion
->length
= 2;
129 oobregion
->offset
= 11;
130 oobregion
->length
= 2;
137 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops
= {
138 .ecc
= rb91x_ooblayout_ecc
,
139 .free
= rb91x_ooblayout_free
,
143 static struct mtd_partition rb91x_nand_partitions
[] = {
147 .size
= (256 * 1024),
148 .mask_flags
= MTD_WRITEABLE
,
151 .offset
= (256 * 1024),
152 .size
= (4 * 1024 * 1024) - (256 * 1024),
155 .offset
= MTDPART_OFS_NXTBLK
,
156 .size
= MTDPART_SIZ_FULL
,
160 static void rb91x_nand_write(struct rb91x_nand_info
*rbni
,
164 void __iomem
*base
= ath79_gpio_base
;
170 /* enable the latch */
171 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
173 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
174 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
176 /* set data lines to output mode */
177 __raw_writel(oe_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
),
178 base
+ AR71XX_GPIO_REG_OE
);
180 out
= out_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
);
181 for (i
= 0; i
!= len
; i
++) {
184 data
= (buf
[i
] & RB91X_NAND_HIGH_DATA_MASK
) <<
185 RB91X_NAND_HIGH_DATA_SHIFT
;
186 data
|= buf
[i
] & RB91X_NAND_LOW_DATA_MASK
;
188 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
190 /* deactivate WE line */
191 data
|= RB91X_NAND_NRWE
;
192 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
194 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
197 /* restore registers */
198 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
199 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
201 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
203 /* disable the latch */
204 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
207 static void rb91x_nand_read(struct rb91x_nand_info
*rbni
,
211 void __iomem
*base
= ath79_gpio_base
;
216 /* enable read mode */
217 gpio_set_value_cansleep(rbni
->gpio_read
, 1);
220 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
223 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
224 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
226 /* set data lines to input mode */
227 __raw_writel(oe_reg
| RB91X_NAND_DATA_BITS
,
228 base
+ AR71XX_GPIO_REG_OE
);
230 for (i
= 0; i
< len
; i
++) {
234 /* activate RE line */
235 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_CLEAR
);
237 __raw_readl(base
+ AR71XX_GPIO_REG_CLEAR
);
239 /* read input lines */
240 in
= __raw_readl(base
+ AR71XX_GPIO_REG_IN
);
242 /* deactivate RE line */
243 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_SET
);
245 data
= (in
& RB91X_NAND_LOW_DATA_MASK
);
246 data
|= (in
>> RB91X_NAND_HIGH_DATA_SHIFT
) &
247 RB91X_NAND_HIGH_DATA_MASK
;
252 /* restore registers */
253 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
254 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
256 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
259 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
261 /* disable read mode */
262 gpio_set_value_cansleep(rbni
->gpio_read
, 0);
265 static int rb91x_nand_dev_ready(struct mtd_info
*mtd
)
267 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
269 return gpio_get_value_cansleep(rbni
->gpio_rdy
);
272 static void rb91x_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
275 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
277 if (ctrl
& NAND_CTRL_CHANGE
) {
278 gpio_set_value_cansleep(rbni
->gpio_cle
,
279 (ctrl
& NAND_CLE
) ? 1 : 0);
280 gpio_set_value_cansleep(rbni
->gpio_ale
,
281 (ctrl
& NAND_ALE
) ? 1 : 0);
282 gpio_set_value_cansleep(rbni
->gpio_nce
,
283 (ctrl
& NAND_NCE
) ? 0 : 1);
286 if (cmd
!= NAND_CMD_NONE
) {
289 rb91x_nand_write(rbni
, &t
, 1);
293 static u8
rb91x_nand_read_byte(struct mtd_info
*mtd
)
295 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
298 rb91x_nand_read(rbni
, &data
, 1);
303 static void rb91x_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
305 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
307 rb91x_nand_read(rbni
, buf
, len
);
310 static void rb91x_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
312 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
314 rb91x_nand_write(rbni
, buf
, len
);
317 static int rb91x_nand_gpio_init(struct rb91x_nand_info
*info
)
322 * Ensure that the LATCH is disabled before initializing
325 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nle
,
326 GPIOF_OUT_INIT_HIGH
, "LATCH enable");
330 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nce
,
331 GPIOF_OUT_INIT_HIGH
, "NAND nCE");
335 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nrw
,
336 GPIOF_OUT_INIT_HIGH
, "NAND nRW");
340 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_cle
,
341 GPIOF_OUT_INIT_LOW
, "NAND CLE");
345 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_ale
,
346 GPIOF_OUT_INIT_LOW
, "NAND ALE");
350 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_read
,
351 GPIOF_OUT_INIT_LOW
, "NAND READ");
355 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_rdy
,
356 GPIOF_IN
, "NAND RDY");
360 static int rb91x_nand_probe(struct platform_device
*pdev
)
362 struct rb91x_nand_info
*rbni
;
363 struct rb91x_nand_platform_data
*pdata
;
364 struct mtd_info
*mtd
;
367 pr_info(DRV_DESC
"\n");
369 pdata
= dev_get_platdata(&pdev
->dev
);
373 rbni
= devm_kzalloc(&pdev
->dev
, sizeof(*rbni
), GFP_KERNEL
);
377 rbni
->dev
= &pdev
->dev
;
378 rbni
->gpio_nce
= pdata
->gpio_nce
;
379 rbni
->gpio_ale
= pdata
->gpio_ale
;
380 rbni
->gpio_cle
= pdata
->gpio_cle
;
381 rbni
->gpio_read
= pdata
->gpio_read
;
382 rbni
->gpio_nrw
= pdata
->gpio_nrw
;
383 rbni
->gpio_rdy
= pdata
->gpio_rdy
;
384 rbni
->gpio_nle
= pdata
->gpio_nle
;
386 rbni
->chip
.priv
= &rbni
;
387 mtd
= rbinfo_to_mtd(rbni
);
389 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
390 mtd
->priv
= &rbni
->chip
;
392 mtd
->owner
= THIS_MODULE
;
394 rbni
->chip
.cmd_ctrl
= rb91x_nand_cmd_ctrl
;
395 rbni
->chip
.dev_ready
= rb91x_nand_dev_ready
;
396 rbni
->chip
.read_byte
= rb91x_nand_read_byte
;
397 rbni
->chip
.write_buf
= rb91x_nand_write_buf
;
398 rbni
->chip
.read_buf
= rb91x_nand_read_buf
;
400 rbni
->chip
.chip_delay
= 25;
401 rbni
->chip
.ecc
.mode
= NAND_ECC_SOFT
;
402 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
403 rbni
->chip
.ecc
.algo
= NAND_ECC_HAMMING
;
405 rbni
->chip
.options
= NAND_NO_SUBPAGE_WRITE
;
407 platform_set_drvdata(pdev
, rbni
);
409 ret
= rb91x_nand_gpio_init(rbni
);
413 ret
= nand_scan_ident(mtd
, 1, NULL
);
417 if (mtd
->writesize
== 512)
418 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
419 rbni
->chip
.ecc
.layout
= &rb91x_nand_ecclayout
;
421 mtd_set_ooblayout(mtd
, &rb91x_nand_ecclayout_ops
);
424 ret
= nand_scan_tail(mtd
);
428 ret
= mtd_device_register(mtd
, rb91x_nand_partitions
,
429 ARRAY_SIZE(rb91x_nand_partitions
));
431 goto err_release_nand
;
440 static int rb91x_nand_remove(struct platform_device
*pdev
)
442 struct rb91x_nand_info
*info
= platform_get_drvdata(pdev
);
444 nand_release(rbinfo_to_mtd(info
));
449 static struct platform_driver rb91x_nand_driver
= {
450 .probe
= rb91x_nand_probe
,
451 .remove
= rb91x_nand_remove
,
453 .name
= RB91X_NAND_DRIVER_NAME
,
454 .owner
= THIS_MODULE
,
458 module_platform_driver(rb91x_nand_driver
);
460 MODULE_DESCRIPTION(DRV_DESC
);
461 MODULE_VERSION(DRV_VERSION
);
462 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
463 MODULE_LICENSE("GPL v2");