2 * NAND flash driver for the MikroTik RouterBOARD 91x series
4 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/spinlock.h>
13 #include <linux/module.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <asm/mach-ath79/ar71xx_regs.h>
22 #include <asm/mach-ath79/ath79.h>
24 #define DRV_NAME "rb91x-nand"
25 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
27 #define RB91X_NAND_NRE_ENABLE BIT(3)
28 #define RB91X_NAND_RDY BIT(4)
29 #define RB91X_LATCH_ENABLE BIT(11)
30 #define RB91X_NAND_NRWE BIT(12)
31 #define RB91X_NAND_NCE BIT(13)
32 #define RB91X_NAND_CLE BIT(14)
33 #define RB91X_NAND_ALE BIT(15)
35 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
36 BIT(13) | BIT(14) | BIT(15))
38 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
39 #define RB91X_NAND_OUTPUT_BITS \
40 (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
42 #define RB91X_NAND_LOW_DATA_MASK 0x1f
43 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
44 #define RB91X_NAND_HIGH_DATA_SHIFT 8
46 struct rb91x_nand_info
{
47 struct nand_chip chip
;
51 static inline struct rb91x_nand_info
*mtd_to_rbinfo(struct mtd_info
*mtd
)
53 return container_of(mtd
, struct rb91x_nand_info
, mtd
);
57 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
58 * will not be able to find the kernel that we load.
60 static struct nand_ecclayout rb91x_nand_ecclayout
= {
62 .eccpos
= { 8, 9, 10, 13, 14, 15 },
64 .oobfree
= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
67 static struct mtd_partition rb91x_nand_partitions
[] = {
72 .mask_flags
= MTD_WRITEABLE
,
75 .offset
= (256 * 1024),
76 .size
= (4 * 1024 * 1024) - (256 * 1024),
79 .offset
= MTDPART_OFS_NXTBLK
,
80 .size
= MTDPART_SIZ_FULL
,
84 static void rb91x_change_gpo(u32 clear
, u32 set
)
86 void __iomem
*base
= ath79_gpio_base
;
87 static unsigned on
= 0xE002800;
88 static unsigned off
= 0x0000C008;
89 static unsigned oe
= 0;
90 static DEFINE_SPINLOCK(lock
);
93 spin_lock_irqsave(&lock
, flags
);
95 on
= (on
| set
) & ~clear
;
96 off
= (off
| clear
) & ~set
;
99 oe
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
101 if (on
& RB91X_LATCH_ENABLE
) {
104 t
= oe
& __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
106 __raw_writel(t
, base
+ AR71XX_GPIO_REG_OE
);
107 __raw_writel(off
, base
+ AR71XX_GPIO_REG_CLEAR
);
108 __raw_writel(on
, base
+ AR71XX_GPIO_REG_SET
);
109 } else if (clear
& RB91X_LATCH_ENABLE
) {
110 oe
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
111 __raw_writel(RB91X_LATCH_ENABLE
,
112 base
+ AR71XX_GPIO_REG_CLEAR
);
114 __raw_readl(base
+ AR71XX_GPIO_REG_CLEAR
);
117 spin_unlock_irqrestore(&lock
, flags
);
120 static inline void rb91x_latch_enable(void)
122 rb91x_change_gpo(RB91X_LATCH_ENABLE
, 0);
125 static inline void rb91x_latch_disable(void)
127 rb91x_change_gpo(0, RB91X_LATCH_ENABLE
);
130 static void rb91x_nand_write(const u8
*buf
, unsigned len
)
132 void __iomem
*base
= ath79_gpio_base
;
138 rb91x_latch_enable();
140 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
141 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
143 /* set data lines to output mode */
144 __raw_writel(oe_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
),
145 base
+ AR71XX_GPIO_REG_OE
);
147 out
= out_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
);
148 for (i
= 0; i
!= len
; i
++) {
151 data
= (buf
[i
] & RB91X_NAND_HIGH_DATA_MASK
) <<
152 RB91X_NAND_HIGH_DATA_SHIFT
;
153 data
|= buf
[i
] & RB91X_NAND_LOW_DATA_MASK
;
155 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
157 /* deactivate WE line */
158 data
|= RB91X_NAND_NRWE
;
159 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
161 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
164 /* restore registers */
165 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
166 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
168 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
170 rb91x_latch_disable();
173 static void rb91x_nand_read(u8
*read_buf
, unsigned len
)
175 void __iomem
*base
= ath79_gpio_base
;
181 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
183 /* select nRE mode */
184 rb91x_change_gpo(0, RB91X_NAND_NRE_ENABLE
);
187 rb91x_latch_enable();
189 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
191 /* set data lines to input mode */
192 __raw_writel(oe_reg
| RB91X_NAND_DATA_BITS
,
193 base
+ AR71XX_GPIO_REG_OE
);
195 for (i
= 0; i
< len
; i
++) {
199 /* activate RE line */
200 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_CLEAR
);
202 __raw_readl(base
+ AR71XX_GPIO_REG_CLEAR
);
204 /* read input lines */
205 in
= __raw_readl(base
+ AR71XX_GPIO_REG_IN
);
207 /* deactivate RE line */
208 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_SET
);
210 data
= (in
& RB91X_NAND_LOW_DATA_MASK
);
211 data
|= (in
>> RB91X_NAND_HIGH_DATA_SHIFT
) &
212 RB91X_NAND_HIGH_DATA_MASK
;
217 /* restore registers */
218 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
219 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
221 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
224 rb91x_latch_disable();
226 /* deselect nRE mode */
227 rb91x_change_gpo(RB91X_NAND_NRE_ENABLE
, 0);
230 static int rb91x_nand_dev_ready(struct mtd_info
*mtd
)
232 void __iomem
*base
= ath79_gpio_base
;
234 return !!(__raw_readl(base
+ AR71XX_GPIO_REG_IN
) & RB91X_NAND_RDY
);
237 static void rb91x_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
240 if (ctrl
& NAND_CTRL_CHANGE
) {
244 if (!(ctrl
& NAND_NCE
))
245 on
|= RB91X_NAND_NCE
;
248 on
|= RB91X_NAND_CLE
;
251 on
|= RB91X_NAND_ALE
;
253 off
= on
^ (RB91X_NAND_ALE
| RB91X_NAND_NCE
| RB91X_NAND_CLE
);
254 rb91x_change_gpo(off
, on
);
257 if (cmd
!= NAND_CMD_NONE
) {
260 rb91x_nand_write(&t
, 1);
264 static u8
rb91x_nand_read_byte(struct mtd_info
*mtd
)
268 rb91x_nand_read(&data
, 1);
273 static void rb91x_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
275 rb91x_nand_read(buf
, len
);
278 static void rb91x_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
280 rb91x_nand_write(buf
, len
);
283 static int rb91x_nand_probe(struct platform_device
*pdev
)
285 struct rb91x_nand_info
*info
;
288 pr_info(DRV_DESC
"\n");
290 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
294 info
->chip
.priv
= &info
;
295 info
->mtd
.priv
= &info
->chip
;
296 info
->mtd
.owner
= THIS_MODULE
;
298 info
->chip
.cmd_ctrl
= rb91x_nand_cmd_ctrl
;
299 info
->chip
.dev_ready
= rb91x_nand_dev_ready
;
300 info
->chip
.read_byte
= rb91x_nand_read_byte
;
301 info
->chip
.write_buf
= rb91x_nand_write_buf
;
302 info
->chip
.read_buf
= rb91x_nand_read_buf
;
304 info
->chip
.chip_delay
= 25;
305 info
->chip
.ecc
.mode
= NAND_ECC_SOFT
;
307 platform_set_drvdata(pdev
, info
);
309 ret
= nand_scan_ident(&info
->mtd
, 1, NULL
);
313 if (info
->mtd
.writesize
== 512)
314 info
->chip
.ecc
.layout
= &rb91x_nand_ecclayout
;
316 ret
= nand_scan_tail(&info
->mtd
);
320 ret
= mtd_device_register(&info
->mtd
, rb91x_nand_partitions
,
321 ARRAY_SIZE(rb91x_nand_partitions
));
323 goto err_release_nand
;
328 nand_release(&info
->mtd
);
332 static int rb91x_nand_remove(struct platform_device
*pdev
)
334 struct rb91x_nand_info
*info
= platform_get_drvdata(pdev
);
336 nand_release(&info
->mtd
);
341 static struct platform_driver rb91x_nand_driver
= {
342 .probe
= rb91x_nand_probe
,
343 .remove
= rb91x_nand_remove
,
346 .owner
= THIS_MODULE
,
350 module_platform_driver(rb91x_nand_driver
);
352 MODULE_DESCRIPTION(DRV_DESC
);
353 MODULE_VERSION(DRV_VERSION
);
354 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
355 MODULE_LICENSE("GPL v2");