2 * NAND flash driver for the MikroTik RouterBOARD 91x series
4 * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/version.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/module.h>
15 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
16 #include <linux/mtd/nand.h>
18 #include <linux/mtd/rawnand.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_data/rb91x_nand.h>
28 #include <asm/mach-ath79/ar71xx_regs.h>
29 #include <asm/mach-ath79/ath79.h>
31 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
33 #define RB91X_NAND_NRWE BIT(12)
35 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
36 BIT(13) | BIT(14) | BIT(15))
38 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
39 #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
41 #define RB91X_NAND_LOW_DATA_MASK 0x1f
42 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
43 #define RB91X_NAND_HIGH_DATA_SHIFT 8
45 struct rb91x_nand_info
{
46 struct nand_chip chip
;
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
61 static inline struct rb91x_nand_info
*mtd_to_rbinfo(struct mtd_info
*mtd
)
63 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
64 return container_of(mtd
, struct rb91x_nand_info
, mtd
);
66 struct nand_chip
*chip
= mtd_to_nand(mtd
);
68 return container_of(chip
, struct rb91x_nand_info
, chip
);
72 static struct mtd_info
*rbinfo_to_mtd(struct rb91x_nand_info
*nfc
)
74 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
77 return nand_to_mtd(&nfc
->chip
);
82 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
84 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
85 * will not be able to find the kernel that we load.
87 static struct nand_ecclayout rb91x_nand_ecclayout
= {
89 .eccpos
= { 8, 9, 10, 13, 14, 15 },
91 .oobfree
= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
96 static int rb91x_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
97 struct mtd_oob_region
*oobregion
)
101 oobregion
->offset
= 8;
102 oobregion
->length
= 3;
105 oobregion
->offset
= 13;
106 oobregion
->length
= 3;
113 static int rb91x_ooblayout_free(struct mtd_info
*mtd
, int section
,
114 struct mtd_oob_region
*oobregion
)
118 oobregion
->offset
= 0;
119 oobregion
->length
= 4;
122 oobregion
->offset
= 4;
123 oobregion
->length
= 1;
126 oobregion
->offset
= 6;
127 oobregion
->length
= 2;
130 oobregion
->offset
= 11;
131 oobregion
->length
= 2;
138 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops
= {
139 .ecc
= rb91x_ooblayout_ecc
,
140 .free
= rb91x_ooblayout_free
,
144 static struct mtd_partition rb91x_nand_partitions
[] = {
148 .size
= (256 * 1024),
149 .mask_flags
= MTD_WRITEABLE
,
152 .offset
= (256 * 1024),
153 .size
= (4 * 1024 * 1024) - (256 * 1024),
156 .offset
= MTDPART_OFS_NXTBLK
,
157 .size
= MTDPART_SIZ_FULL
,
161 static void rb91x_nand_write(struct rb91x_nand_info
*rbni
,
165 void __iomem
*base
= ath79_gpio_base
;
171 /* enable the latch */
172 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
174 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
175 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
177 /* set data lines to output mode */
178 __raw_writel(oe_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
),
179 base
+ AR71XX_GPIO_REG_OE
);
181 out
= out_reg
& ~(RB91X_NAND_DATA_BITS
| RB91X_NAND_NRWE
);
182 for (i
= 0; i
!= len
; i
++) {
185 data
= (buf
[i
] & RB91X_NAND_HIGH_DATA_MASK
) <<
186 RB91X_NAND_HIGH_DATA_SHIFT
;
187 data
|= buf
[i
] & RB91X_NAND_LOW_DATA_MASK
;
189 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
191 /* deactivate WE line */
192 data
|= RB91X_NAND_NRWE
;
193 __raw_writel(data
, base
+ AR71XX_GPIO_REG_OUT
);
195 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
198 /* restore registers */
199 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
200 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
202 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
204 /* disable the latch */
205 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
208 static void rb91x_nand_read(struct rb91x_nand_info
*rbni
,
212 void __iomem
*base
= ath79_gpio_base
;
217 /* enable read mode */
218 gpio_set_value_cansleep(rbni
->gpio_read
, 1);
221 gpio_set_value_cansleep(rbni
->gpio_nle
, 0);
224 oe_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OE
);
225 out_reg
= __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
227 /* set data lines to input mode */
228 __raw_writel(oe_reg
| RB91X_NAND_DATA_BITS
,
229 base
+ AR71XX_GPIO_REG_OE
);
231 for (i
= 0; i
< len
; i
++) {
235 /* activate RE line */
236 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_CLEAR
);
238 __raw_readl(base
+ AR71XX_GPIO_REG_CLEAR
);
240 /* read input lines */
241 in
= __raw_readl(base
+ AR71XX_GPIO_REG_IN
);
243 /* deactivate RE line */
244 __raw_writel(RB91X_NAND_NRWE
, base
+ AR71XX_GPIO_REG_SET
);
246 data
= (in
& RB91X_NAND_LOW_DATA_MASK
);
247 data
|= (in
>> RB91X_NAND_HIGH_DATA_SHIFT
) &
248 RB91X_NAND_HIGH_DATA_MASK
;
253 /* restore registers */
254 __raw_writel(out_reg
, base
+ AR71XX_GPIO_REG_OUT
);
255 __raw_writel(oe_reg
, base
+ AR71XX_GPIO_REG_OE
);
257 __raw_readl(base
+ AR71XX_GPIO_REG_OUT
);
260 gpio_set_value_cansleep(rbni
->gpio_nle
, 1);
262 /* disable read mode */
263 gpio_set_value_cansleep(rbni
->gpio_read
, 0);
266 static int rb91x_nand_dev_ready(struct mtd_info
*mtd
)
268 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
270 return gpio_get_value_cansleep(rbni
->gpio_rdy
);
273 static void rb91x_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
276 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
278 if (ctrl
& NAND_CTRL_CHANGE
) {
279 gpio_set_value_cansleep(rbni
->gpio_cle
,
280 (ctrl
& NAND_CLE
) ? 1 : 0);
281 gpio_set_value_cansleep(rbni
->gpio_ale
,
282 (ctrl
& NAND_ALE
) ? 1 : 0);
283 gpio_set_value_cansleep(rbni
->gpio_nce
,
284 (ctrl
& NAND_NCE
) ? 0 : 1);
287 if (cmd
!= NAND_CMD_NONE
) {
290 rb91x_nand_write(rbni
, &t
, 1);
294 static u8
rb91x_nand_read_byte(struct mtd_info
*mtd
)
296 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
299 rb91x_nand_read(rbni
, &data
, 1);
304 static void rb91x_nand_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
306 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
308 rb91x_nand_read(rbni
, buf
, len
);
311 static void rb91x_nand_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
313 struct rb91x_nand_info
*rbni
= mtd_to_rbinfo(mtd
);
315 rb91x_nand_write(rbni
, buf
, len
);
318 static int rb91x_nand_gpio_init(struct rb91x_nand_info
*info
)
323 * Ensure that the LATCH is disabled before initializing
326 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nle
,
327 GPIOF_OUT_INIT_HIGH
, "LATCH enable");
331 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nce
,
332 GPIOF_OUT_INIT_HIGH
, "NAND nCE");
336 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_nrw
,
337 GPIOF_OUT_INIT_HIGH
, "NAND nRW");
341 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_cle
,
342 GPIOF_OUT_INIT_LOW
, "NAND CLE");
346 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_ale
,
347 GPIOF_OUT_INIT_LOW
, "NAND ALE");
351 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_read
,
352 GPIOF_OUT_INIT_LOW
, "NAND READ");
356 ret
= devm_gpio_request_one(info
->dev
, info
->gpio_rdy
,
357 GPIOF_IN
, "NAND RDY");
361 static int rb91x_nand_probe(struct platform_device
*pdev
)
363 struct rb91x_nand_info
*rbni
;
364 struct rb91x_nand_platform_data
*pdata
;
365 struct mtd_info
*mtd
;
368 pr_info(DRV_DESC
"\n");
370 pdata
= dev_get_platdata(&pdev
->dev
);
374 rbni
= devm_kzalloc(&pdev
->dev
, sizeof(*rbni
), GFP_KERNEL
);
378 rbni
->dev
= &pdev
->dev
;
379 rbni
->gpio_nce
= pdata
->gpio_nce
;
380 rbni
->gpio_ale
= pdata
->gpio_ale
;
381 rbni
->gpio_cle
= pdata
->gpio_cle
;
382 rbni
->gpio_read
= pdata
->gpio_read
;
383 rbni
->gpio_nrw
= pdata
->gpio_nrw
;
384 rbni
->gpio_rdy
= pdata
->gpio_rdy
;
385 rbni
->gpio_nle
= pdata
->gpio_nle
;
387 rbni
->chip
.priv
= &rbni
;
388 mtd
= rbinfo_to_mtd(rbni
);
390 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
391 mtd
->priv
= &rbni
->chip
;
393 mtd
->owner
= THIS_MODULE
;
395 rbni
->chip
.cmd_ctrl
= rb91x_nand_cmd_ctrl
;
396 rbni
->chip
.dev_ready
= rb91x_nand_dev_ready
;
397 rbni
->chip
.read_byte
= rb91x_nand_read_byte
;
398 rbni
->chip
.write_buf
= rb91x_nand_write_buf
;
399 rbni
->chip
.read_buf
= rb91x_nand_read_buf
;
401 rbni
->chip
.chip_delay
= 25;
402 rbni
->chip
.ecc
.mode
= NAND_ECC_SOFT
;
403 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
404 rbni
->chip
.ecc
.algo
= NAND_ECC_HAMMING
;
406 rbni
->chip
.options
= NAND_NO_SUBPAGE_WRITE
;
408 platform_set_drvdata(pdev
, rbni
);
410 ret
= rb91x_nand_gpio_init(rbni
);
414 ret
= nand_scan_ident(mtd
, 1, NULL
);
418 if (mtd
->writesize
== 512)
419 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
420 rbni
->chip
.ecc
.layout
= &rb91x_nand_ecclayout
;
422 mtd_set_ooblayout(mtd
, &rb91x_nand_ecclayout_ops
);
425 ret
= nand_scan_tail(mtd
);
429 ret
= mtd_device_register(mtd
, rb91x_nand_partitions
,
430 ARRAY_SIZE(rb91x_nand_partitions
));
432 goto err_release_nand
;
437 nand_release(&rbni
->chip
);
441 static int rb91x_nand_remove(struct platform_device
*pdev
)
443 struct rb91x_nand_info
*info
= platform_get_drvdata(pdev
);
445 nand_release(&rbni
->chip
);
450 static struct platform_driver rb91x_nand_driver
= {
451 .probe
= rb91x_nand_probe
,
452 .remove
= rb91x_nand_remove
,
454 .name
= RB91X_NAND_DRIVER_NAME
,
455 .owner
= THIS_MODULE
,
459 module_platform_driver(rb91x_nand_driver
);
461 MODULE_DESCRIPTION(DRV_DESC
);
462 MODULE_VERSION(DRV_VERSION
);
463 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
464 MODULE_LICENSE("GPL v2");