2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level
= -1;
28 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
29 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
36 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
37 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
42 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
43 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
46 static void ag71xx_dump_regs(struct ag71xx
*ag
)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
51 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
52 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
53 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
54 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
58 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
59 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
63 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
68 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
69 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
72 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag
->dev
->name
, label
, intr
,
76 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
77 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
78 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
79 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
80 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
81 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
89 dma_free_coherent(NULL
, ring
->size
* ring
->desc_size
,
90 ring
->descs_cpu
, ring
->descs_dma
);
93 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
, unsigned int size
)
98 ring
->desc_size
= sizeof(struct ag71xx_desc
);
99 if (ring
->desc_size
% cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring
, ring
->desc_size
,
102 roundup(ring
->desc_size
, cache_line_size()));
103 ring
->desc_size
= roundup(ring
->desc_size
, cache_line_size());
106 ring
->descs_cpu
= dma_alloc_coherent(NULL
, size
* ring
->desc_size
,
107 &ring
->descs_dma
, GFP_ATOMIC
);
108 if (!ring
->descs_cpu
) {
115 ring
->buf
= kzalloc(size
* sizeof(*ring
->buf
), GFP_KERNEL
);
121 for (i
= 0; i
< size
; i
++) {
122 int idx
= i
* ring
->desc_size
;
123 ring
->buf
[i
].desc
= (struct ag71xx_desc
*)&ring
->descs_cpu
[idx
];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring
, i
, ring
->buf
[i
].desc
);
134 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
136 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
137 struct net_device
*dev
= ag
->dev
;
139 while (ring
->curr
!= ring
->dirty
) {
140 u32 i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
142 if (!ag71xx_desc_empty(ring
->buf
[i
].desc
)) {
143 ring
->buf
[i
].desc
->ctrl
= 0;
144 dev
->stats
.tx_errors
++;
147 if (ring
->buf
[i
].skb
)
148 dev_kfree_skb_any(ring
->buf
[i
].skb
);
150 ring
->buf
[i
].skb
= NULL
;
155 /* flush descriptors */
160 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
162 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
165 for (i
= 0; i
< AG71XX_TX_RING_SIZE
; i
++) {
166 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
167 ring
->desc_size
* ((i
+ 1) % AG71XX_TX_RING_SIZE
));
169 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
170 ring
->buf
[i
].skb
= NULL
;
173 /* flush descriptors */
180 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
182 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
188 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
189 if (ring
->buf
[i
].skb
) {
190 dma_unmap_single(&ag
->dev
->dev
, ring
->buf
[i
].dma_addr
,
191 AG71XX_RX_PKT_SIZE
, DMA_FROM_DEVICE
);
192 kfree_skb(ring
->buf
[i
].skb
);
196 static int ag71xx_rx_reserve(struct ag71xx
*ag
)
200 if (ag71xx_get_pdata(ag
)->is_ar724x
) {
201 if (!ag71xx_has_ar8216(ag
))
205 reserve
+= 4 - (ag
->phy_dev
->pkt_align
% 4);
210 return reserve
+ AG71XX_RX_PKT_RESERVE
;
214 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
216 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
217 unsigned int reserve
= ag71xx_rx_reserve(ag
);
222 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
223 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
224 ring
->desc_size
* ((i
+ 1) % AG71XX_RX_RING_SIZE
));
226 DBG("ag71xx: RX desc at %p, next is %08x\n",
228 ring
->buf
[i
].desc
->next
);
231 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
235 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
+ reserve
);
242 skb_reserve(skb
, reserve
);
244 dma_addr
= dma_map_single(&ag
->dev
->dev
, skb
->data
,
247 ring
->buf
[i
].skb
= skb
;
248 ring
->buf
[i
].dma_addr
= dma_addr
;
249 ring
->buf
[i
].desc
->data
= (u32
) dma_addr
;
250 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
253 /* flush descriptors */
262 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
264 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
265 unsigned int reserve
= ag71xx_rx_reserve(ag
);
269 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
272 i
= ring
->dirty
% AG71XX_RX_RING_SIZE
;
274 if (ring
->buf
[i
].skb
== NULL
) {
278 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
+ reserve
);
282 skb_reserve(skb
, reserve
);
285 dma_addr
= dma_map_single(&ag
->dev
->dev
, skb
->data
,
289 ring
->buf
[i
].skb
= skb
;
290 ring
->buf
[i
].dma_addr
= dma_addr
;
291 ring
->buf
[i
].desc
->data
= (u32
) dma_addr
;
294 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
298 /* flush descriptors */
301 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
306 static int ag71xx_rings_init(struct ag71xx
*ag
)
310 ret
= ag71xx_ring_alloc(&ag
->tx_ring
, AG71XX_TX_RING_SIZE
);
314 ag71xx_ring_tx_init(ag
);
316 ret
= ag71xx_ring_alloc(&ag
->rx_ring
, AG71XX_RX_RING_SIZE
);
320 ret
= ag71xx_ring_rx_init(ag
);
324 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
326 ag71xx_ring_rx_clean(ag
);
327 ag71xx_ring_free(&ag
->rx_ring
);
329 ag71xx_ring_tx_clean(ag
);
330 ag71xx_ring_free(&ag
->tx_ring
);
333 static unsigned char *ag71xx_speed_str(struct ag71xx
*ag
)
347 static void ag71xx_dma_reset(struct ag71xx
*ag
)
352 ag71xx_dump_dma_regs(ag
);
355 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
356 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
359 * give the hardware some time to really stop all rx/tx activity
360 * clearing the descriptors too early causes random memory corruption
364 /* clear descriptor addresses */
365 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, 0);
366 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, 0);
368 /* clear pending RX/TX interrupts */
369 for (i
= 0; i
< 256; i
++) {
370 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
371 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
374 /* clear pending errors */
375 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
376 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
378 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
380 printk(KERN_ALERT
"%s: unable to clear DMA Rx status: %08x\n",
383 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
385 /* mask out reserved bits */
389 printk(KERN_ALERT
"%s: unable to clear DMA Tx status: %08x\n",
392 ag71xx_dump_dma_regs(ag
);
395 static void ag71xx_hw_start(struct ag71xx
*ag
)
397 /* start RX engine */
398 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
400 /* enable interrupts */
401 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
404 static void ag71xx_hw_stop(struct ag71xx
*ag
)
406 /* disable all interrupts */
407 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
409 ag71xx_dma_reset(ag
);
412 void ag71xx_link_adjust(struct ag71xx
*ag
)
414 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
422 netif_carrier_off(ag
->dev
);
423 if (netif_msg_link(ag
))
424 printk(KERN_INFO
"%s: link down\n", ag
->dev
->name
);
428 cfg2
= ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
);
429 cfg2
&= ~(MAC_CFG2_IF_1000
| MAC_CFG2_IF_10_100
| MAC_CFG2_FDX
);
430 cfg2
|= (ag
->duplex
) ? MAC_CFG2_FDX
: 0;
432 ifctl
= ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
);
433 ifctl
&= ~(MAC_IFCTL_SPEED
);
435 fifo5
= ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
);
436 fifo5
&= ~FIFO_CFG5_BM
;
440 mii_speed
= MII_CTRL_SPEED_1000
;
441 cfg2
|= MAC_CFG2_IF_1000
;
442 fifo5
|= FIFO_CFG5_BM
;
445 mii_speed
= MII_CTRL_SPEED_100
;
446 cfg2
|= MAC_CFG2_IF_10_100
;
447 ifctl
|= MAC_IFCTL_SPEED
;
450 mii_speed
= MII_CTRL_SPEED_10
;
451 cfg2
|= MAC_CFG2_IF_10_100
;
458 if (pdata
->is_ar91xx
)
459 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x00780fff);
460 else if (pdata
->is_ar724x
)
461 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, pdata
->fifo_cfg3
);
463 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x008001ff);
466 pdata
->set_pll(ag
->speed
);
468 ag71xx_mii_ctrl_set_speed(ag
, mii_speed
);
470 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG2
, cfg2
);
471 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, fifo5
);
472 ag71xx_wr(ag
, AG71XX_REG_MAC_IFCTL
, ifctl
);
476 netif_carrier_on(ag
->dev
);
477 if (netif_msg_link(ag
))
478 printk(KERN_INFO
"%s: link up (%sMbps/%s duplex)\n",
480 ag71xx_speed_str(ag
),
481 (DUPLEX_FULL
== ag
->duplex
) ? "Full" : "Half");
483 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
485 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
486 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
487 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
489 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
491 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
492 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
493 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
495 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
497 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
498 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
499 ag71xx_mii_ctrl_rr(ag
));
502 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
506 t
= (((u32
) mac
[5]) << 24) | (((u32
) mac
[4]) << 16)
507 | (((u32
) mac
[3]) << 8) | ((u32
) mac
[2]);
509 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
511 t
= (((u32
) mac
[1]) << 24) | (((u32
) mac
[0]) << 16);
512 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
515 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
516 MAC_CFG1_SRX | MAC_CFG1_STX)
518 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
520 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
521 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
522 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
523 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
524 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
527 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
528 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
529 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
530 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
531 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
532 FIFO_CFG5_17 | FIFO_CFG5_SF)
534 static void ag71xx_hw_init(struct ag71xx
*ag
)
536 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
538 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
541 ar71xx_device_stop(pdata
->reset_bit
);
543 ar71xx_device_start(pdata
->reset_bit
);
546 /* setup MAC configuration registers */
547 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_INIT
);
549 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
550 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
552 /* setup max frame length */
553 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, AG71XX_TX_MTU_LEN
);
555 /* setup MII interface type */
556 ag71xx_mii_ctrl_set_if(ag
, pdata
->mii_if
);
558 /* setup FIFO configuration registers */
559 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
560 if (pdata
->is_ar724x
) {
561 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, pdata
->fifo_cfg1
);
562 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, pdata
->fifo_cfg2
);
564 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
565 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
567 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
568 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
570 ag71xx_dma_reset(ag
);
573 static int ag71xx_open(struct net_device
*dev
)
575 struct ag71xx
*ag
= netdev_priv(dev
);
578 ret
= ag71xx_rings_init(ag
);
582 napi_enable(&ag
->napi
);
584 netif_carrier_off(dev
);
585 ag71xx_phy_start(ag
);
587 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
588 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
590 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
592 netif_start_queue(dev
);
597 ag71xx_rings_cleanup(ag
);
601 static int ag71xx_stop(struct net_device
*dev
)
603 struct ag71xx
*ag
= netdev_priv(dev
);
606 netif_carrier_off(dev
);
609 spin_lock_irqsave(&ag
->lock
, flags
);
611 netif_stop_queue(dev
);
615 napi_disable(&ag
->napi
);
616 del_timer_sync(&ag
->oom_timer
);
618 spin_unlock_irqrestore(&ag
->lock
, flags
);
620 ag71xx_rings_cleanup(ag
);
625 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
626 struct net_device
*dev
)
628 struct ag71xx
*ag
= netdev_priv(dev
);
629 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
630 struct ag71xx_desc
*desc
;
634 i
= ring
->curr
% AG71XX_TX_RING_SIZE
;
635 desc
= ring
->buf
[i
].desc
;
637 if (!ag71xx_desc_empty(desc
))
640 if (ag71xx_has_ar8216(ag
))
641 ag71xx_add_ar8216_header(ag
, skb
);
644 DBG("%s: packet len is too small\n", ag
->dev
->name
);
648 dma_addr
= dma_map_single(&dev
->dev
, skb
->data
, skb
->len
,
651 ring
->buf
[i
].skb
= skb
;
652 ring
->buf
[i
].timestamp
= jiffies
;
654 /* setup descriptor fields */
655 desc
->data
= (u32
) dma_addr
;
656 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
658 /* flush descriptor */
662 if (ring
->curr
== (ring
->dirty
+ AG71XX_TX_THRES_STOP
)) {
663 DBG("%s: tx queue full\n", ag
->dev
->name
);
664 netif_stop_queue(dev
);
667 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
669 /* enable TX engine */
670 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
675 dev
->stats
.tx_dropped
++;
681 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
683 struct ag71xx
*ag
= netdev_priv(dev
);
688 if (ag
->phy_dev
== NULL
)
691 spin_lock_irq(&ag
->lock
);
692 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
693 spin_unlock_irq(&ag
->lock
);
698 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
704 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
711 if (ag
->phy_dev
== NULL
)
714 return phy_mii_ioctl(ag
->phy_dev
, ifr
, cmd
);
723 static void ag71xx_oom_timer_handler(unsigned long data
)
725 struct net_device
*dev
= (struct net_device
*) data
;
726 struct ag71xx
*ag
= netdev_priv(dev
);
728 napi_schedule(&ag
->napi
);
731 static void ag71xx_tx_timeout(struct net_device
*dev
)
733 struct ag71xx
*ag
= netdev_priv(dev
);
735 if (netif_msg_tx_err(ag
))
736 printk(KERN_DEBUG
"%s: tx timeout\n", ag
->dev
->name
);
738 schedule_work(&ag
->restart_work
);
741 static void ag71xx_restart_work_func(struct work_struct
*work
)
743 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
);
744 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
746 ag71xx_stop(ag
->dev
);
748 if (pdata
->is_ar724x
)
751 ag71xx_open(ag
->dev
);
754 static int ag71xx_tx_packets(struct ag71xx
*ag
)
756 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
759 DBG("%s: processing TX ring\n", ag
->dev
->name
);
762 while (ring
->dirty
!= ring
->curr
) {
763 unsigned int i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
764 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
765 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
767 if (!ag71xx_desc_empty(desc
))
770 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
772 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
773 ag
->dev
->stats
.tx_packets
++;
775 dev_kfree_skb_any(skb
);
776 ring
->buf
[i
].skb
= NULL
;
782 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
784 if ((ring
->curr
- ring
->dirty
) < AG71XX_TX_THRES_WAKEUP
)
785 netif_wake_queue(ag
->dev
);
790 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
792 struct net_device
*dev
= ag
->dev
;
793 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
796 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
797 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
799 while (done
< limit
) {
800 unsigned int i
= ring
->curr
% AG71XX_RX_RING_SIZE
;
801 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
806 if (ag71xx_desc_empty(desc
))
809 if ((ring
->dirty
+ AG71XX_RX_RING_SIZE
) == ring
->curr
) {
814 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
816 skb
= ring
->buf
[i
].skb
;
817 pktlen
= ag71xx_desc_pktlen(desc
);
818 pktlen
-= ETH_FCS_LEN
;
820 dma_unmap_single(&dev
->dev
, ring
->buf
[i
].dma_addr
,
821 AG71XX_RX_PKT_SIZE
, DMA_FROM_DEVICE
);
823 dev
->last_rx
= jiffies
;
824 dev
->stats
.rx_packets
++;
825 dev
->stats
.rx_bytes
+= pktlen
;
827 skb_put(skb
, pktlen
);
828 if (ag71xx_has_ar8216(ag
))
829 err
= ag71xx_remove_ar8216_header(ag
, skb
, pktlen
);
832 dev
->stats
.rx_dropped
++;
836 skb
->ip_summed
= CHECKSUM_NONE
;
838 ag
->phy_dev
->netif_receive_skb(skb
);
840 skb
->protocol
= eth_type_trans(skb
, dev
);
841 netif_receive_skb(skb
);
845 ring
->buf
[i
].skb
= NULL
;
851 ag71xx_ring_rx_refill(ag
);
853 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
854 dev
->name
, ring
->curr
, ring
->dirty
, done
);
859 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
861 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
862 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
863 struct net_device
*dev
= ag
->dev
;
864 struct ag71xx_ring
*rx_ring
;
871 tx_done
= ag71xx_tx_packets(ag
);
873 DBG("%s: processing RX ring\n", dev
->name
);
874 rx_done
= ag71xx_rx_packets(ag
, limit
);
876 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
878 rx_ring
= &ag
->rx_ring
;
879 if (rx_ring
->buf
[rx_ring
->dirty
% AG71XX_RX_RING_SIZE
].skb
== NULL
)
882 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
883 if (unlikely(status
& RX_STATUS_OF
)) {
884 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
885 dev
->stats
.rx_fifo_errors
++;
888 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
891 if (rx_done
< limit
) {
892 if (status
& RX_STATUS_PR
)
895 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
896 if (status
& TX_STATUS_PS
)
899 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
900 dev
->name
, rx_done
, tx_done
, limit
);
904 /* enable interrupts */
905 spin_lock_irqsave(&ag
->lock
, flags
);
906 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
907 spin_unlock_irqrestore(&ag
->lock
, flags
);
912 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
913 dev
->name
, rx_done
, tx_done
, limit
);
917 if (netif_msg_rx_err(ag
))
918 printk(KERN_DEBUG
"%s: out of memory\n", dev
->name
);
920 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
925 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
927 struct net_device
*dev
= dev_id
;
928 struct ag71xx
*ag
= netdev_priv(dev
);
931 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
932 ag71xx_dump_intr(ag
, "raw", status
);
934 if (unlikely(!status
))
937 if (unlikely(status
& AG71XX_INT_ERR
)) {
938 if (status
& AG71XX_INT_TX_BE
) {
939 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
940 dev_err(&dev
->dev
, "TX BUS error\n");
942 if (status
& AG71XX_INT_RX_BE
) {
943 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
944 dev_err(&dev
->dev
, "RX BUS error\n");
948 if (likely(status
& AG71XX_INT_POLL
)) {
949 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
950 DBG("%s: enable polling mode\n", dev
->name
);
951 napi_schedule(&ag
->napi
);
954 ag71xx_debugfs_update_int_stats(ag
, status
);
959 static void ag71xx_set_multicast_list(struct net_device
*dev
)
964 #ifdef CONFIG_NET_POLL_CONTROLLER
966 * Polling 'interrupt' - used by things like netconsole to send skbs
967 * without having to re-enable interrupts. It's not called while
968 * the interrupt routine is executing.
970 static void ag71xx_netpoll(struct net_device
*dev
)
972 disable_irq(dev
->irq
);
973 ag71xx_interrupt(dev
->irq
, dev
);
974 enable_irq(dev
->irq
);
978 static const struct net_device_ops ag71xx_netdev_ops
= {
979 .ndo_open
= ag71xx_open
,
980 .ndo_stop
= ag71xx_stop
,
981 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
982 .ndo_set_multicast_list
= ag71xx_set_multicast_list
,
983 .ndo_do_ioctl
= ag71xx_do_ioctl
,
984 .ndo_tx_timeout
= ag71xx_tx_timeout
,
985 .ndo_change_mtu
= eth_change_mtu
,
986 .ndo_set_mac_address
= eth_mac_addr
,
987 .ndo_validate_addr
= eth_validate_addr
,
988 #ifdef CONFIG_NET_POLL_CONTROLLER
989 .ndo_poll_controller
= ag71xx_netpoll
,
993 static int __devinit
ag71xx_probe(struct platform_device
*pdev
)
995 struct net_device
*dev
;
996 struct resource
*res
;
998 struct ag71xx_platform_data
*pdata
;
1001 pdata
= pdev
->dev
.platform_data
;
1003 dev_err(&pdev
->dev
, "no platform data specified\n");
1008 if (pdata
->mii_bus_dev
== NULL
) {
1009 dev_err(&pdev
->dev
, "no MII bus device specified\n");
1014 dev
= alloc_etherdev(sizeof(*ag
));
1016 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1021 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1023 ag
= netdev_priv(dev
);
1026 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
1027 AG71XX_DEFAULT_MSG_ENABLE
);
1028 spin_lock_init(&ag
->lock
);
1030 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
1032 dev_err(&pdev
->dev
, "no mac_base resource found\n");
1037 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
1038 if (!ag
->mac_base
) {
1039 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
1044 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mii_ctrl");
1046 dev_err(&pdev
->dev
, "no mii_ctrl resource found\n");
1048 goto err_unmap_base
;
1051 ag
->mii_ctrl
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
1052 if (!ag
->mii_ctrl
) {
1053 dev_err(&pdev
->dev
, "unable to ioremap mii_ctrl\n");
1055 goto err_unmap_base
;
1058 dev
->irq
= platform_get_irq(pdev
, 0);
1059 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
1063 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
1064 goto err_unmap_mii_ctrl
;
1067 dev
->base_addr
= (unsigned long)ag
->mac_base
;
1068 dev
->netdev_ops
= &ag71xx_netdev_ops
;
1069 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
1071 INIT_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
1073 init_timer(&ag
->oom_timer
);
1074 ag
->oom_timer
.data
= (unsigned long) dev
;
1075 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
1077 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
1079 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
1081 err
= register_netdev(dev
);
1083 dev_err(&pdev
->dev
, "unable to register net device\n");
1087 printk(KERN_INFO
"%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1088 dev
->name
, dev
->base_addr
, dev
->irq
);
1090 ag71xx_dump_regs(ag
);
1094 ag71xx_dump_regs(ag
);
1096 err
= ag71xx_phy_connect(ag
);
1098 goto err_unregister_netdev
;
1100 err
= ag71xx_debugfs_init(ag
);
1102 goto err_phy_disconnect
;
1104 platform_set_drvdata(pdev
, dev
);
1109 ag71xx_phy_disconnect(ag
);
1110 err_unregister_netdev
:
1111 unregister_netdev(dev
);
1113 free_irq(dev
->irq
, dev
);
1115 iounmap(ag
->mii_ctrl
);
1117 iounmap(ag
->mac_base
);
1121 platform_set_drvdata(pdev
, NULL
);
1125 static int __devexit
ag71xx_remove(struct platform_device
*pdev
)
1127 struct net_device
*dev
= platform_get_drvdata(pdev
);
1130 struct ag71xx
*ag
= netdev_priv(dev
);
1132 ag71xx_debugfs_exit(ag
);
1133 ag71xx_phy_disconnect(ag
);
1134 unregister_netdev(dev
);
1135 free_irq(dev
->irq
, dev
);
1136 iounmap(ag
->mii_ctrl
);
1137 iounmap(ag
->mac_base
);
1139 platform_set_drvdata(pdev
, NULL
);
1145 static struct platform_driver ag71xx_driver
= {
1146 .probe
= ag71xx_probe
,
1147 .remove
= __exit_p(ag71xx_remove
),
1149 .name
= AG71XX_DRV_NAME
,
1153 static int __init
ag71xx_module_init(void)
1157 ret
= ag71xx_debugfs_root_init();
1161 ret
= ag71xx_mdio_driver_init();
1163 goto err_debugfs_exit
;
1165 ret
= platform_driver_register(&ag71xx_driver
);
1172 ag71xx_mdio_driver_exit();
1174 ag71xx_debugfs_root_exit();
1179 static void __exit
ag71xx_module_exit(void)
1181 platform_driver_unregister(&ag71xx_driver
);
1182 ag71xx_mdio_driver_exit();
1183 ag71xx_debugfs_root_exit();
1186 module_init(ag71xx_module_init
);
1187 module_exit(ag71xx_module_exit
);
1189 MODULE_VERSION(AG71XX_DRV_VERSION
);
1190 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1191 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1192 MODULE_LICENSE("GPL v2");
1193 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);