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ag71xx: keep the rx engine stopped while the link is not up, should hopefully fix...
[openwrt/staging/chunkeey.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
347 {
348 u32 t;
349
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
357 }
358
359 static void ag71xx_dma_reset(struct ag71xx *ag)
360 {
361 u32 val;
362 int i;
363
364 ag71xx_dump_dma_regs(ag);
365
366 /* stop RX and TX */
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
369
370 /*
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
373 */
374 mdelay(1);
375
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
379
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
384 }
385
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 if (val)
392 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
393 ag->dev->name, val);
394
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396
397 /* mask out reserved bits */
398 val &= ~0xff000000;
399
400 if (val)
401 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
402 ag->dev->name, val);
403
404 ag71xx_dump_dma_regs(ag);
405 }
406
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
409
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
417 FIFO_CFG4_VT)
418
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
425
426 static void ag71xx_hw_init(struct ag71xx *ag)
427 {
428 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
429
430 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
431 udelay(20);
432
433 ar71xx_device_stop(pdata->reset_bit);
434 mdelay(100);
435 ar71xx_device_start(pdata->reset_bit);
436 mdelay(100);
437
438 /* setup MAC configuration registers */
439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
440
441 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
442 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
443
444 /* setup max frame length */
445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
446
447 /* setup MII interface type */
448 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
449
450 /* setup FIFO configuration registers */
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
452 if (pdata->is_ar724x) {
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
455 } else {
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
458 }
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
461
462 ag71xx_dma_reset(ag);
463 }
464
465 static void ag71xx_hw_start(struct ag71xx *ag)
466 {
467 /* start RX engine */
468 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
469
470 /* enable interrupts */
471 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
472 }
473
474 static void ag71xx_hw_stop(struct ag71xx *ag)
475 {
476 /* disable all interrupts and stop the rx engine */
477 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
478 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
479 }
480
481 void ag71xx_link_adjust(struct ag71xx *ag)
482 {
483 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
484 u32 cfg2;
485 u32 ifctl;
486 u32 fifo5;
487 u32 mii_speed;
488
489 if (!ag->link) {
490 ag71xx_hw_stop(ag);
491 netif_carrier_off(ag->dev);
492 if (netif_msg_link(ag))
493 printk(KERN_INFO "%s: link down\n", ag->dev->name);
494 return;
495 }
496
497 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
498 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
499 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
500
501 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
502 ifctl &= ~(MAC_IFCTL_SPEED);
503
504 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
505 fifo5 &= ~FIFO_CFG5_BM;
506
507 switch (ag->speed) {
508 case SPEED_1000:
509 mii_speed = MII_CTRL_SPEED_1000;
510 cfg2 |= MAC_CFG2_IF_1000;
511 fifo5 |= FIFO_CFG5_BM;
512 break;
513 case SPEED_100:
514 mii_speed = MII_CTRL_SPEED_100;
515 cfg2 |= MAC_CFG2_IF_10_100;
516 ifctl |= MAC_IFCTL_SPEED;
517 break;
518 case SPEED_10:
519 mii_speed = MII_CTRL_SPEED_10;
520 cfg2 |= MAC_CFG2_IF_10_100;
521 break;
522 default:
523 BUG();
524 return;
525 }
526
527 if (pdata->is_ar91xx)
528 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
529 else if (pdata->is_ar724x)
530 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
531 else
532 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
533
534 if (pdata->set_pll)
535 pdata->set_pll(ag->speed);
536
537 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
538
539 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
540 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
541 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
542 ag71xx_hw_start(ag);
543
544 netif_carrier_on(ag->dev);
545 if (netif_msg_link(ag))
546 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
547 ag->dev->name,
548 ag71xx_speed_str(ag),
549 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
550
551 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
552 ag->dev->name,
553 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
554 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
555 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
556
557 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
558 ag->dev->name,
559 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
560 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
561 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
562
563 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
564 ag->dev->name,
565 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
566 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
567 ag71xx_mii_ctrl_rr(ag));
568 }
569
570 static int ag71xx_open(struct net_device *dev)
571 {
572 struct ag71xx *ag = netdev_priv(dev);
573 int ret;
574
575 ret = ag71xx_rings_init(ag);
576 if (ret)
577 goto err;
578
579 napi_enable(&ag->napi);
580
581 netif_carrier_off(dev);
582 ag71xx_phy_start(ag);
583
584 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
585 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
586
587 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
588
589 netif_start_queue(dev);
590
591 return 0;
592
593 err:
594 ag71xx_rings_cleanup(ag);
595 return ret;
596 }
597
598 static int ag71xx_stop(struct net_device *dev)
599 {
600 struct ag71xx *ag = netdev_priv(dev);
601 unsigned long flags;
602
603 netif_carrier_off(dev);
604 ag71xx_phy_stop(ag);
605
606 spin_lock_irqsave(&ag->lock, flags);
607
608 netif_stop_queue(dev);
609
610 ag71xx_hw_stop(ag);
611 ag71xx_dma_reset(ag);
612
613 napi_disable(&ag->napi);
614 del_timer_sync(&ag->oom_timer);
615
616 spin_unlock_irqrestore(&ag->lock, flags);
617
618 ag71xx_rings_cleanup(ag);
619
620 return 0;
621 }
622
623 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
624 struct net_device *dev)
625 {
626 struct ag71xx *ag = netdev_priv(dev);
627 struct ag71xx_ring *ring = &ag->tx_ring;
628 struct ag71xx_desc *desc;
629 dma_addr_t dma_addr;
630 int i;
631
632 i = ring->curr % ring->size;
633 desc = ring->buf[i].desc;
634
635 if (!ag71xx_desc_empty(desc))
636 goto err_drop;
637
638 if (ag71xx_has_ar8216(ag))
639 ag71xx_add_ar8216_header(ag, skb);
640
641 if (skb->len <= 0) {
642 DBG("%s: packet len is too small\n", ag->dev->name);
643 goto err_drop;
644 }
645
646 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
647 DMA_TO_DEVICE);
648
649 ring->buf[i].skb = skb;
650 ring->buf[i].timestamp = jiffies;
651
652 /* setup descriptor fields */
653 desc->data = (u32) dma_addr;
654 desc->ctrl = (skb->len & DESC_PKTLEN_M);
655
656 /* flush descriptor */
657 wmb();
658
659 ring->curr++;
660 if (ring->curr == (ring->dirty + ring->size)) {
661 DBG("%s: tx queue full\n", ag->dev->name);
662 netif_stop_queue(dev);
663 }
664
665 DBG("%s: packet injected into TX queue\n", ag->dev->name);
666
667 /* enable TX engine */
668 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
669
670 return NETDEV_TX_OK;
671
672 err_drop:
673 dev->stats.tx_dropped++;
674
675 dev_kfree_skb(skb);
676 return NETDEV_TX_OK;
677 }
678
679 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
680 {
681 struct ag71xx *ag = netdev_priv(dev);
682 int ret;
683
684 switch (cmd) {
685 case SIOCETHTOOL:
686 if (ag->phy_dev == NULL)
687 break;
688
689 spin_lock_irq(&ag->lock);
690 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
691 spin_unlock_irq(&ag->lock);
692 return ret;
693
694 case SIOCSIFHWADDR:
695 if (copy_from_user
696 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
697 return -EFAULT;
698 return 0;
699
700 case SIOCGIFHWADDR:
701 if (copy_to_user
702 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
703 return -EFAULT;
704 return 0;
705
706 case SIOCGMIIPHY:
707 case SIOCGMIIREG:
708 case SIOCSMIIREG:
709 if (ag->phy_dev == NULL)
710 break;
711
712 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
713
714 default:
715 break;
716 }
717
718 return -EOPNOTSUPP;
719 }
720
721 static void ag71xx_oom_timer_handler(unsigned long data)
722 {
723 struct net_device *dev = (struct net_device *) data;
724 struct ag71xx *ag = netdev_priv(dev);
725
726 napi_schedule(&ag->napi);
727 }
728
729 static void ag71xx_tx_timeout(struct net_device *dev)
730 {
731 struct ag71xx *ag = netdev_priv(dev);
732
733 if (netif_msg_tx_err(ag))
734 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
735
736 schedule_work(&ag->restart_work);
737 }
738
739 static void ag71xx_restart_work_func(struct work_struct *work)
740 {
741 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
742 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
743
744 ag71xx_stop(ag->dev);
745
746 if (pdata->is_ar724x)
747 ag71xx_hw_init(ag);
748
749 ag71xx_open(ag->dev);
750 }
751
752 static int ag71xx_tx_packets(struct ag71xx *ag)
753 {
754 struct ag71xx_ring *ring = &ag->tx_ring;
755 int sent;
756
757 DBG("%s: processing TX ring\n", ag->dev->name);
758
759 sent = 0;
760 while (ring->dirty != ring->curr) {
761 unsigned int i = ring->dirty % ring->size;
762 struct ag71xx_desc *desc = ring->buf[i].desc;
763 struct sk_buff *skb = ring->buf[i].skb;
764
765 if (!ag71xx_desc_empty(desc))
766 break;
767
768 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
769
770 ag->dev->stats.tx_bytes += skb->len;
771 ag->dev->stats.tx_packets++;
772
773 dev_kfree_skb_any(skb);
774 ring->buf[i].skb = NULL;
775
776 ring->dirty++;
777 sent++;
778 }
779
780 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
781
782 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
783 netif_wake_queue(ag->dev);
784
785 return sent;
786 }
787
788 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
789 {
790 struct net_device *dev = ag->dev;
791 struct ag71xx_ring *ring = &ag->rx_ring;
792 int done = 0;
793
794 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
795 dev->name, limit, ring->curr, ring->dirty);
796
797 while (done < limit) {
798 unsigned int i = ring->curr % ring->size;
799 struct ag71xx_desc *desc = ring->buf[i].desc;
800 struct sk_buff *skb;
801 int pktlen;
802 int err = 0;
803
804 if (ag71xx_desc_empty(desc))
805 break;
806
807 if ((ring->dirty + ring->size) == ring->curr) {
808 ag71xx_assert(0);
809 break;
810 }
811
812 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
813
814 skb = ring->buf[i].skb;
815 pktlen = ag71xx_desc_pktlen(desc);
816 pktlen -= ETH_FCS_LEN;
817
818 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
819 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
820
821 dev->last_rx = jiffies;
822 dev->stats.rx_packets++;
823 dev->stats.rx_bytes += pktlen;
824
825 skb_put(skb, pktlen);
826 if (ag71xx_has_ar8216(ag))
827 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
828
829 if (err) {
830 dev->stats.rx_dropped++;
831 kfree_skb(skb);
832 } else {
833 skb->dev = dev;
834 skb->ip_summed = CHECKSUM_NONE;
835 if (ag->phy_dev) {
836 ag->phy_dev->netif_receive_skb(skb);
837 } else {
838 skb->protocol = eth_type_trans(skb, dev);
839 netif_receive_skb(skb);
840 }
841 }
842
843 ring->buf[i].skb = NULL;
844 done++;
845
846 ring->curr++;
847 }
848
849 ag71xx_ring_rx_refill(ag);
850
851 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
852 dev->name, ring->curr, ring->dirty, done);
853
854 return done;
855 }
856
857 static int ag71xx_poll(struct napi_struct *napi, int limit)
858 {
859 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
860 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
861 struct net_device *dev = ag->dev;
862 struct ag71xx_ring *rx_ring;
863 unsigned long flags;
864 u32 status;
865 int tx_done;
866 int rx_done;
867
868 pdata->ddr_flush();
869 tx_done = ag71xx_tx_packets(ag);
870
871 DBG("%s: processing RX ring\n", dev->name);
872 rx_done = ag71xx_rx_packets(ag, limit);
873
874 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
875
876 rx_ring = &ag->rx_ring;
877 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
878 goto oom;
879
880 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
881 if (unlikely(status & RX_STATUS_OF)) {
882 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
883 dev->stats.rx_fifo_errors++;
884
885 /* restart RX */
886 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
887 }
888
889 if (rx_done < limit) {
890 if (status & RX_STATUS_PR)
891 goto more;
892
893 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
894 if (status & TX_STATUS_PS)
895 goto more;
896
897 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
898 dev->name, rx_done, tx_done, limit);
899
900 napi_complete(napi);
901
902 /* enable interrupts */
903 spin_lock_irqsave(&ag->lock, flags);
904 ag71xx_int_enable(ag, AG71XX_INT_POLL);
905 spin_unlock_irqrestore(&ag->lock, flags);
906 return rx_done;
907 }
908
909 more:
910 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
911 dev->name, rx_done, tx_done, limit);
912 return rx_done;
913
914 oom:
915 if (netif_msg_rx_err(ag))
916 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
917
918 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
919 napi_complete(napi);
920 return 0;
921 }
922
923 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
924 {
925 struct net_device *dev = dev_id;
926 struct ag71xx *ag = netdev_priv(dev);
927 u32 status;
928
929 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
930 ag71xx_dump_intr(ag, "raw", status);
931
932 if (unlikely(!status))
933 return IRQ_NONE;
934
935 if (unlikely(status & AG71XX_INT_ERR)) {
936 if (status & AG71XX_INT_TX_BE) {
937 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
938 dev_err(&dev->dev, "TX BUS error\n");
939 }
940 if (status & AG71XX_INT_RX_BE) {
941 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
942 dev_err(&dev->dev, "RX BUS error\n");
943 }
944 }
945
946 if (likely(status & AG71XX_INT_POLL)) {
947 ag71xx_int_disable(ag, AG71XX_INT_POLL);
948 DBG("%s: enable polling mode\n", dev->name);
949 napi_schedule(&ag->napi);
950 }
951
952 ag71xx_debugfs_update_int_stats(ag, status);
953
954 return IRQ_HANDLED;
955 }
956
957 static void ag71xx_set_multicast_list(struct net_device *dev)
958 {
959 /* TODO */
960 }
961
962 #ifdef CONFIG_NET_POLL_CONTROLLER
963 /*
964 * Polling 'interrupt' - used by things like netconsole to send skbs
965 * without having to re-enable interrupts. It's not called while
966 * the interrupt routine is executing.
967 */
968 static void ag71xx_netpoll(struct net_device *dev)
969 {
970 disable_irq(dev->irq);
971 ag71xx_interrupt(dev->irq, dev);
972 enable_irq(dev->irq);
973 }
974 #endif
975
976 static const struct net_device_ops ag71xx_netdev_ops = {
977 .ndo_open = ag71xx_open,
978 .ndo_stop = ag71xx_stop,
979 .ndo_start_xmit = ag71xx_hard_start_xmit,
980 .ndo_set_multicast_list = ag71xx_set_multicast_list,
981 .ndo_do_ioctl = ag71xx_do_ioctl,
982 .ndo_tx_timeout = ag71xx_tx_timeout,
983 .ndo_change_mtu = eth_change_mtu,
984 .ndo_set_mac_address = eth_mac_addr,
985 .ndo_validate_addr = eth_validate_addr,
986 #ifdef CONFIG_NET_POLL_CONTROLLER
987 .ndo_poll_controller = ag71xx_netpoll,
988 #endif
989 };
990
991 static int __devinit ag71xx_probe(struct platform_device *pdev)
992 {
993 struct net_device *dev;
994 struct resource *res;
995 struct ag71xx *ag;
996 struct ag71xx_platform_data *pdata;
997 int err;
998
999 pdata = pdev->dev.platform_data;
1000 if (!pdata) {
1001 dev_err(&pdev->dev, "no platform data specified\n");
1002 err = -ENXIO;
1003 goto err_out;
1004 }
1005
1006 if (pdata->mii_bus_dev == NULL) {
1007 dev_err(&pdev->dev, "no MII bus device specified\n");
1008 err = -EINVAL;
1009 goto err_out;
1010 }
1011
1012 dev = alloc_etherdev(sizeof(*ag));
1013 if (!dev) {
1014 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1015 err = -ENOMEM;
1016 goto err_out;
1017 }
1018
1019 SET_NETDEV_DEV(dev, &pdev->dev);
1020
1021 ag = netdev_priv(dev);
1022 ag->pdev = pdev;
1023 ag->dev = dev;
1024 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1025 AG71XX_DEFAULT_MSG_ENABLE);
1026 spin_lock_init(&ag->lock);
1027
1028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1029 if (!res) {
1030 dev_err(&pdev->dev, "no mac_base resource found\n");
1031 err = -ENXIO;
1032 goto err_out;
1033 }
1034
1035 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1036 if (!ag->mac_base) {
1037 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1038 err = -ENOMEM;
1039 goto err_free_dev;
1040 }
1041
1042 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1043 if (!res) {
1044 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1045 err = -ENXIO;
1046 goto err_unmap_base;
1047 }
1048
1049 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1050 if (!ag->mii_ctrl) {
1051 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1052 err = -ENOMEM;
1053 goto err_unmap_base;
1054 }
1055
1056 dev->irq = platform_get_irq(pdev, 0);
1057 err = request_irq(dev->irq, ag71xx_interrupt,
1058 IRQF_DISABLED,
1059 dev->name, dev);
1060 if (err) {
1061 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1062 goto err_unmap_mii_ctrl;
1063 }
1064
1065 dev->base_addr = (unsigned long)ag->mac_base;
1066 dev->netdev_ops = &ag71xx_netdev_ops;
1067 dev->ethtool_ops = &ag71xx_ethtool_ops;
1068
1069 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1070
1071 init_timer(&ag->oom_timer);
1072 ag->oom_timer.data = (unsigned long) dev;
1073 ag->oom_timer.function = ag71xx_oom_timer_handler;
1074
1075 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1076 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1077
1078 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1079
1080 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1081
1082 err = register_netdev(dev);
1083 if (err) {
1084 dev_err(&pdev->dev, "unable to register net device\n");
1085 goto err_free_irq;
1086 }
1087
1088 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1089 dev->name, dev->base_addr, dev->irq);
1090
1091 ag71xx_dump_regs(ag);
1092
1093 ag71xx_hw_init(ag);
1094
1095 ag71xx_dump_regs(ag);
1096
1097 err = ag71xx_phy_connect(ag);
1098 if (err)
1099 goto err_unregister_netdev;
1100
1101 err = ag71xx_debugfs_init(ag);
1102 if (err)
1103 goto err_phy_disconnect;
1104
1105 platform_set_drvdata(pdev, dev);
1106
1107 return 0;
1108
1109 err_phy_disconnect:
1110 ag71xx_phy_disconnect(ag);
1111 err_unregister_netdev:
1112 unregister_netdev(dev);
1113 err_free_irq:
1114 free_irq(dev->irq, dev);
1115 err_unmap_mii_ctrl:
1116 iounmap(ag->mii_ctrl);
1117 err_unmap_base:
1118 iounmap(ag->mac_base);
1119 err_free_dev:
1120 kfree(dev);
1121 err_out:
1122 platform_set_drvdata(pdev, NULL);
1123 return err;
1124 }
1125
1126 static int __devexit ag71xx_remove(struct platform_device *pdev)
1127 {
1128 struct net_device *dev = platform_get_drvdata(pdev);
1129
1130 if (dev) {
1131 struct ag71xx *ag = netdev_priv(dev);
1132
1133 ag71xx_debugfs_exit(ag);
1134 ag71xx_phy_disconnect(ag);
1135 unregister_netdev(dev);
1136 free_irq(dev->irq, dev);
1137 iounmap(ag->mii_ctrl);
1138 iounmap(ag->mac_base);
1139 kfree(dev);
1140 platform_set_drvdata(pdev, NULL);
1141 }
1142
1143 return 0;
1144 }
1145
1146 static struct platform_driver ag71xx_driver = {
1147 .probe = ag71xx_probe,
1148 .remove = __exit_p(ag71xx_remove),
1149 .driver = {
1150 .name = AG71XX_DRV_NAME,
1151 }
1152 };
1153
1154 static int __init ag71xx_module_init(void)
1155 {
1156 int ret;
1157
1158 ret = ag71xx_debugfs_root_init();
1159 if (ret)
1160 goto err_out;
1161
1162 ret = ag71xx_mdio_driver_init();
1163 if (ret)
1164 goto err_debugfs_exit;
1165
1166 ret = platform_driver_register(&ag71xx_driver);
1167 if (ret)
1168 goto err_mdio_exit;
1169
1170 return 0;
1171
1172 err_mdio_exit:
1173 ag71xx_mdio_driver_exit();
1174 err_debugfs_exit:
1175 ag71xx_debugfs_root_exit();
1176 err_out:
1177 return ret;
1178 }
1179
1180 static void __exit ag71xx_module_exit(void)
1181 {
1182 platform_driver_unregister(&ag71xx_driver);
1183 ag71xx_mdio_driver_exit();
1184 ag71xx_debugfs_root_exit();
1185 }
1186
1187 module_init(ag71xx_module_init);
1188 module_exit(ag71xx_module_exit);
1189
1190 MODULE_VERSION(AG71XX_DRV_VERSION);
1191 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1192 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1193 MODULE_LICENSE("GPL v2");
1194 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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