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ag71xx driver: store descriptor pointers in ag71xx_buf
[openwrt/staging/yousong.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * sizeof(struct ag71xx_desc),
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96 int i;
97
98 ring->descs_cpu = dma_alloc_coherent(NULL,
99 size * sizeof(struct ag71xx_desc),
100 &ring->descs_dma,
101 GFP_ATOMIC);
102 if (!ring->descs_cpu) {
103 err = -ENOMEM;
104 goto err;
105 }
106
107 ring->size = size;
108
109 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
110 if (!ring->buf) {
111 err = -ENOMEM;
112 goto err;
113 }
114
115 for (i = 0; i < size; i++) {
116 struct ag71xx_desc *descs = (struct ag71xx_desc *) ring->descs_cpu;
117 ring->buf[i].desc = &descs[i];
118 }
119
120 return 0;
121
122 err:
123 return err;
124 }
125
126 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
127 {
128 struct ag71xx_ring *ring = &ag->tx_ring;
129 struct net_device *dev = ag->dev;
130
131 while (ring->curr != ring->dirty) {
132 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
133
134 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
135 ring->buf[i].desc->ctrl = 0;
136 dev->stats.tx_errors++;
137 }
138
139 if (ring->buf[i].skb)
140 dev_kfree_skb_any(ring->buf[i].skb);
141
142 ring->buf[i].skb = NULL;
143
144 ring->dirty++;
145 }
146
147 /* flush descriptors */
148 wmb();
149
150 }
151
152 static void ag71xx_ring_tx_init(struct ag71xx *ag)
153 {
154 struct ag71xx_ring *ring = &ag->tx_ring;
155 int i;
156
157 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
158 ring->buf[i].desc->next = (u32) (ring->descs_dma +
159 sizeof(struct ag71xx_desc) * ((i + 1) % AG71XX_TX_RING_SIZE));
160
161 ring->buf[i].desc->ctrl = DESC_EMPTY;
162 ring->buf[i].skb = NULL;
163 }
164
165 /* flush descriptors */
166 wmb();
167
168 ring->curr = 0;
169 ring->dirty = 0;
170 }
171
172 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
173 {
174 struct ag71xx_ring *ring = &ag->rx_ring;
175 int i;
176
177 if (!ring->buf)
178 return;
179
180 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
181 if (ring->buf[i].skb)
182 kfree_skb(ring->buf[i].skb);
183
184 }
185
186 static int ag71xx_ring_rx_init(struct ag71xx *ag)
187 {
188 struct ag71xx_ring *ring = &ag->rx_ring;
189 unsigned int i;
190 int ret;
191
192 ret = 0;
193 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
194 ring->buf[i].desc->next = (u32) (ring->descs_dma +
195 sizeof(struct ag71xx_desc) * ((i + 1) % AG71XX_RX_RING_SIZE));
196
197 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
198 struct sk_buff *skb;
199
200 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
201 if (!skb) {
202 ret = -ENOMEM;
203 break;
204 }
205
206 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
207 DMA_FROM_DEVICE);
208
209 skb->dev = ag->dev;
210 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
211
212 ring->buf[i].skb = skb;
213 ring->buf[i].desc->data = virt_to_phys(skb->data);
214 ring->buf[i].desc->ctrl = DESC_EMPTY;
215 }
216
217 /* flush descriptors */
218 wmb();
219
220 ring->curr = 0;
221 ring->dirty = 0;
222
223 return ret;
224 }
225
226 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
227 {
228 struct ag71xx_ring *ring = &ag->rx_ring;
229 unsigned int count;
230
231 count = 0;
232 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
233 unsigned int i;
234
235 i = ring->dirty % AG71XX_RX_RING_SIZE;
236
237 if (ring->buf[i].skb == NULL) {
238 struct sk_buff *skb;
239
240 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
241 if (skb == NULL)
242 break;
243
244 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246
247 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
248 skb->dev = ag->dev;
249
250 ring->buf[i].skb = skb;
251 ring->buf[i].desc->data = virt_to_phys(skb->data);
252 }
253
254 ring->buf[i].desc->ctrl = DESC_EMPTY;
255 count++;
256 }
257
258 /* flush descriptors */
259 wmb();
260
261 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
262
263 return count;
264 }
265
266 static int ag71xx_rings_init(struct ag71xx *ag)
267 {
268 int ret;
269
270 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
271 if (ret)
272 return ret;
273
274 ag71xx_ring_tx_init(ag);
275
276 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
277 if (ret)
278 return ret;
279
280 ret = ag71xx_ring_rx_init(ag);
281 return ret;
282 }
283
284 static void ag71xx_rings_cleanup(struct ag71xx *ag)
285 {
286 ag71xx_ring_rx_clean(ag);
287 ag71xx_ring_free(&ag->rx_ring);
288
289 ag71xx_ring_tx_clean(ag);
290 ag71xx_ring_free(&ag->tx_ring);
291 }
292
293 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
294 {
295 u32 t;
296
297 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
298 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
299
300 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
301
302 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
303 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
304 }
305
306 static void ag71xx_dma_reset(struct ag71xx *ag)
307 {
308 int i;
309
310 ag71xx_dump_dma_regs(ag);
311
312 /* stop RX and TX */
313 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
314 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
315
316 /* clear descriptor addresses */
317 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
318 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
319
320 /* clear pending RX/TX interrupts */
321 for (i = 0; i < 256; i++) {
322 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
323 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
324 }
325
326 /* clear pending errors */
327 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
328 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
329
330 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
331 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
332 ag->dev->name);
333
334 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
335 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
336 ag->dev->name);
337
338 ag71xx_dump_dma_regs(ag);
339 }
340
341 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
342 MAC_CFG1_SRX | MAC_CFG1_STX)
343
344 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
345
346 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
347 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
348 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
349 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
350 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
351 FIFO_CFG4_VT)
352
353 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
354 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
355 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
356 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
357 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
358 FIFO_CFG5_17 | FIFO_CFG5_SF)
359
360 static void ag71xx_hw_init(struct ag71xx *ag)
361 {
362 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
363
364 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
365 udelay(20);
366
367 ar71xx_device_stop(pdata->reset_bit);
368 mdelay(100);
369 ar71xx_device_start(pdata->reset_bit);
370 mdelay(100);
371
372 /* setup MAC configuration registers */
373 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
374 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
375 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
376
377 /* setup max frame length */
378 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
379
380 /* setup MII interface type */
381 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
382
383 /* setup FIFO configuration registers */
384 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
385 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
386 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
387 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
388 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
389
390 ag71xx_dma_reset(ag);
391 }
392
393 static void ag71xx_hw_start(struct ag71xx *ag)
394 {
395 /* start RX engine */
396 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
397
398 /* enable interrupts */
399 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
400 }
401
402 static void ag71xx_hw_stop(struct ag71xx *ag)
403 {
404 /* disable all interrupts */
405 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
406
407 ag71xx_dma_reset(ag);
408 }
409
410 static int ag71xx_open(struct net_device *dev)
411 {
412 struct ag71xx *ag = netdev_priv(dev);
413 int ret;
414
415 ret = ag71xx_rings_init(ag);
416 if (ret)
417 goto err;
418
419 napi_enable(&ag->napi);
420
421 netif_carrier_off(dev);
422 ag71xx_phy_start(ag);
423
424 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
425 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
426
427 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
428
429 ag71xx_hw_start(ag);
430
431 netif_start_queue(dev);
432
433 return 0;
434
435 err:
436 ag71xx_rings_cleanup(ag);
437 return ret;
438 }
439
440 static int ag71xx_stop(struct net_device *dev)
441 {
442 struct ag71xx *ag = netdev_priv(dev);
443 unsigned long flags;
444
445 spin_lock_irqsave(&ag->lock, flags);
446
447 netif_stop_queue(dev);
448
449 ag71xx_hw_stop(ag);
450
451 netif_carrier_off(dev);
452 ag71xx_phy_stop(ag);
453
454 napi_disable(&ag->napi);
455 del_timer_sync(&ag->oom_timer);
456
457 spin_unlock_irqrestore(&ag->lock, flags);
458
459 ag71xx_rings_cleanup(ag);
460
461 return 0;
462 }
463
464 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
465 {
466 struct ag71xx *ag = netdev_priv(dev);
467 struct ag71xx_ring *ring = &ag->tx_ring;
468 struct ag71xx_desc *desc;
469 int i;
470
471 i = ring->curr % AG71XX_TX_RING_SIZE;
472 desc = ring->buf[i].desc;
473
474 if (!ag71xx_desc_empty(desc))
475 goto err_drop;
476
477 ag71xx_add_ar8216_header(ag, skb);
478
479 if (skb->len <= 0) {
480 DBG("%s: packet len is too small\n", ag->dev->name);
481 goto err_drop;
482 }
483
484 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
485
486 ring->buf[i].skb = skb;
487
488 /* setup descriptor fields */
489 desc->data = virt_to_phys(skb->data);
490 desc->ctrl = (skb->len & DESC_PKTLEN_M);
491
492 /* flush descriptor */
493 wmb();
494
495 ring->curr++;
496 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
497 DBG("%s: tx queue full\n", ag->dev->name);
498 netif_stop_queue(dev);
499 }
500
501 DBG("%s: packet injected into TX queue\n", ag->dev->name);
502
503 /* enable TX engine */
504 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
505
506 dev->trans_start = jiffies;
507
508 return 0;
509
510 err_drop:
511 dev->stats.tx_dropped++;
512
513 dev_kfree_skb(skb);
514 return 0;
515 }
516
517 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
518 {
519 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
520 struct ag71xx *ag = netdev_priv(dev);
521 int ret;
522
523 switch (cmd) {
524 case SIOCETHTOOL:
525 if (ag->phy_dev == NULL)
526 break;
527
528 spin_lock_irq(&ag->lock);
529 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
530 spin_unlock_irq(&ag->lock);
531 return ret;
532
533 case SIOCSIFHWADDR:
534 if (copy_from_user
535 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
536 return -EFAULT;
537 return 0;
538
539 case SIOCGIFHWADDR:
540 if (copy_to_user
541 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
542 return -EFAULT;
543 return 0;
544
545 case SIOCGMIIPHY:
546 case SIOCGMIIREG:
547 case SIOCSMIIREG:
548 if (ag->phy_dev == NULL)
549 break;
550
551 return phy_mii_ioctl(ag->phy_dev, data, cmd);
552
553 default:
554 break;
555 }
556
557 return -EOPNOTSUPP;
558 }
559
560 static void ag71xx_oom_timer_handler(unsigned long data)
561 {
562 struct net_device *dev = (struct net_device *) data;
563 struct ag71xx *ag = netdev_priv(dev);
564
565 netif_rx_schedule(dev, &ag->napi);
566 }
567
568 static void ag71xx_tx_timeout(struct net_device *dev)
569 {
570 struct ag71xx *ag = netdev_priv(dev);
571
572 if (netif_msg_tx_err(ag))
573 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
574
575 schedule_work(&ag->restart_work);
576 }
577
578 static void ag71xx_restart_work_func(struct work_struct *work)
579 {
580 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
581
582 ag71xx_stop(ag->dev);
583 ag71xx_open(ag->dev);
584 }
585
586 static void ag71xx_tx_packets(struct ag71xx *ag)
587 {
588 struct ag71xx_ring *ring = &ag->tx_ring;
589 unsigned int sent;
590
591 DBG("%s: processing TX ring\n", ag->dev->name);
592
593 sent = 0;
594 while (ring->dirty != ring->curr) {
595 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
596 struct ag71xx_desc *desc = ring->buf[i].desc;
597 struct sk_buff *skb = ring->buf[i].skb;
598
599 if (!ag71xx_desc_empty(desc))
600 break;
601
602 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
603
604 ag->dev->stats.tx_bytes += skb->len;
605 ag->dev->stats.tx_packets++;
606
607 dev_kfree_skb_any(skb);
608 ring->buf[i].skb = NULL;
609
610 ring->dirty++;
611 sent++;
612 }
613
614 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
615
616 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
617 netif_wake_queue(ag->dev);
618
619 }
620
621 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
622 {
623 struct net_device *dev = ag->dev;
624 struct ag71xx_ring *ring = &ag->rx_ring;
625 int done = 0;
626
627 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
628 dev->name, limit, ring->curr, ring->dirty);
629
630 while (done < limit) {
631 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
632 struct ag71xx_desc *desc = ring->buf[i].desc;
633 struct sk_buff *skb;
634 int pktlen;
635
636 if (ag71xx_desc_empty(desc))
637 break;
638
639 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
640 ag71xx_assert(0);
641 break;
642 }
643
644 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
645
646 skb = ring->buf[i].skb;
647 pktlen = ag71xx_desc_pktlen(desc);
648 pktlen -= ETH_FCS_LEN;
649
650 skb_put(skb, pktlen);
651
652 skb->dev = dev;
653 skb->ip_summed = CHECKSUM_NONE;
654
655 dev->last_rx = jiffies;
656 dev->stats.rx_packets++;
657 dev->stats.rx_bytes += pktlen;
658
659 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
660 dev->stats.rx_dropped++;
661 kfree_skb(skb);
662 } else {
663 skb->protocol = eth_type_trans(skb, dev);
664 netif_receive_skb(skb);
665 }
666
667 ring->buf[i].skb = NULL;
668 done++;
669
670 ring->curr++;
671 }
672
673 ag71xx_ring_rx_refill(ag);
674
675 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
676 dev->name, ring->curr, ring->dirty, done);
677
678 return done;
679 }
680
681 static int ag71xx_poll(struct napi_struct *napi, int limit)
682 {
683 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
684 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
685 struct net_device *dev = ag->dev;
686 struct ag71xx_ring *rx_ring;
687 unsigned long flags;
688 u32 status;
689 int done;
690
691 pdata->ddr_flush();
692 ag71xx_tx_packets(ag);
693
694 DBG("%s: processing RX ring\n", dev->name);
695 done = ag71xx_rx_packets(ag, limit);
696
697 rx_ring = &ag->rx_ring;
698 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
699 goto oom;
700
701 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
702 if (unlikely(status & RX_STATUS_OF)) {
703 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
704 dev->stats.rx_fifo_errors++;
705
706 /* restart RX */
707 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
708 }
709
710 if (done < limit) {
711 if (status & RX_STATUS_PR)
712 goto more;
713
714 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
715 if (status & TX_STATUS_PS)
716 goto more;
717
718 DBG("%s: disable polling mode, done=%d, limit=%d\n",
719 dev->name, done, limit);
720
721 netif_rx_complete(dev, napi);
722
723 /* enable interrupts */
724 spin_lock_irqsave(&ag->lock, flags);
725 ag71xx_int_enable(ag, AG71XX_INT_POLL);
726 spin_unlock_irqrestore(&ag->lock, flags);
727 return done;
728 }
729
730 more:
731 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
732 dev->name, done, limit);
733 return done;
734
735 oom:
736 if (netif_msg_rx_err(ag))
737 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
738
739 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
740 netif_rx_complete(dev, napi);
741 return 0;
742 }
743
744 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
745 {
746 struct net_device *dev = dev_id;
747 struct ag71xx *ag = netdev_priv(dev);
748 u32 status;
749
750 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
751 ag71xx_dump_intr(ag, "raw", status);
752
753 if (unlikely(!status))
754 return IRQ_NONE;
755
756 if (unlikely(status & AG71XX_INT_ERR)) {
757 if (status & AG71XX_INT_TX_BE) {
758 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
759 dev_err(&dev->dev, "TX BUS error\n");
760 }
761 if (status & AG71XX_INT_RX_BE) {
762 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
763 dev_err(&dev->dev, "RX BUS error\n");
764 }
765 }
766
767 if (likely(status & AG71XX_INT_POLL)) {
768 ag71xx_int_disable(ag, AG71XX_INT_POLL);
769 DBG("%s: enable polling mode\n", dev->name);
770 netif_rx_schedule(dev, &ag->napi);
771 }
772
773 return IRQ_HANDLED;
774 }
775
776 static void ag71xx_set_multicast_list(struct net_device *dev)
777 {
778 /* TODO */
779 }
780
781 static int __init ag71xx_probe(struct platform_device *pdev)
782 {
783 struct net_device *dev;
784 struct resource *res;
785 struct ag71xx *ag;
786 struct ag71xx_platform_data *pdata;
787 int err;
788
789 pdata = pdev->dev.platform_data;
790 if (!pdata) {
791 dev_err(&pdev->dev, "no platform data specified\n");
792 err = -ENXIO;
793 goto err_out;
794 }
795
796 dev = alloc_etherdev(sizeof(*ag));
797 if (!dev) {
798 dev_err(&pdev->dev, "alloc_etherdev failed\n");
799 err = -ENOMEM;
800 goto err_out;
801 }
802
803 SET_NETDEV_DEV(dev, &pdev->dev);
804
805 ag = netdev_priv(dev);
806 ag->pdev = pdev;
807 ag->dev = dev;
808 ag->mii_bus = ag71xx_mdio_bus->mii_bus;
809 ag->msg_enable = netif_msg_init(ag71xx_debug,
810 AG71XX_DEFAULT_MSG_ENABLE);
811 spin_lock_init(&ag->lock);
812
813 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
814 if (!res) {
815 dev_err(&pdev->dev, "no mac_base resource found\n");
816 err = -ENXIO;
817 goto err_out;
818 }
819
820 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
821 if (!ag->mac_base) {
822 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
823 err = -ENOMEM;
824 goto err_free_dev;
825 }
826
827 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
828 if (!res) {
829 dev_err(&pdev->dev, "no mac_base2 resource found\n");
830 err = -ENXIO;
831 goto err_unmap_base1;
832 }
833
834 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
835 if (!ag->mac_base) {
836 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
837 err = -ENOMEM;
838 goto err_unmap_base1;
839 }
840
841 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
842 if (!res) {
843 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
844 err = -ENXIO;
845 goto err_unmap_base2;
846 }
847
848 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
849 if (!ag->mii_ctrl) {
850 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
851 err = -ENOMEM;
852 goto err_unmap_base2;
853 }
854
855 dev->irq = platform_get_irq(pdev, 0);
856 err = request_irq(dev->irq, ag71xx_interrupt,
857 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
858 dev->name, dev);
859 if (err) {
860 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
861 goto err_unmap_mii_ctrl;
862 }
863
864 dev->base_addr = (unsigned long)ag->mac_base;
865 dev->open = ag71xx_open;
866 dev->stop = ag71xx_stop;
867 dev->hard_start_xmit = ag71xx_hard_start_xmit;
868 dev->set_multicast_list = ag71xx_set_multicast_list;
869 dev->do_ioctl = ag71xx_do_ioctl;
870 dev->ethtool_ops = &ag71xx_ethtool_ops;
871
872 dev->tx_timeout = ag71xx_tx_timeout;
873 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
874
875 init_timer(&ag->oom_timer);
876 ag->oom_timer.data = (unsigned long) dev;
877 ag->oom_timer.function = ag71xx_oom_timer_handler;
878
879 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
880
881 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
882
883 err = register_netdev(dev);
884 if (err) {
885 dev_err(&pdev->dev, "unable to register net device\n");
886 goto err_free_irq;
887 }
888
889 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
890 dev->name, dev->base_addr, dev->irq);
891
892 ag71xx_dump_regs(ag);
893
894 ag71xx_hw_init(ag);
895
896 ag71xx_dump_regs(ag);
897
898 /* Reset the mdio bus explicitly */
899 if (ag->mii_bus) {
900 mutex_lock(&ag->mii_bus->mdio_lock);
901 ag->mii_bus->reset(ag->mii_bus);
902 mutex_unlock(&ag->mii_bus->mdio_lock);
903 }
904
905 err = ag71xx_phy_connect(ag);
906 if (err)
907 goto err_unregister_netdev;
908
909 platform_set_drvdata(pdev, dev);
910
911 return 0;
912
913 err_unregister_netdev:
914 unregister_netdev(dev);
915 err_free_irq:
916 free_irq(dev->irq, dev);
917 err_unmap_mii_ctrl:
918 iounmap(ag->mii_ctrl);
919 err_unmap_base2:
920 iounmap(ag->mac_base2);
921 err_unmap_base1:
922 iounmap(ag->mac_base);
923 err_free_dev:
924 kfree(dev);
925 err_out:
926 platform_set_drvdata(pdev, NULL);
927 return err;
928 }
929
930 static int __exit ag71xx_remove(struct platform_device *pdev)
931 {
932 struct net_device *dev = platform_get_drvdata(pdev);
933
934 if (dev) {
935 struct ag71xx *ag = netdev_priv(dev);
936
937 ag71xx_phy_disconnect(ag);
938 unregister_netdev(dev);
939 free_irq(dev->irq, dev);
940 iounmap(ag->mii_ctrl);
941 iounmap(ag->mac_base2);
942 iounmap(ag->mac_base);
943 kfree(dev);
944 platform_set_drvdata(pdev, NULL);
945 }
946
947 return 0;
948 }
949
950 static struct platform_driver ag71xx_driver = {
951 .probe = ag71xx_probe,
952 .remove = __exit_p(ag71xx_remove),
953 .driver = {
954 .name = AG71XX_DRV_NAME,
955 }
956 };
957
958 static int __init ag71xx_module_init(void)
959 {
960 int ret;
961
962 ret = ag71xx_mdio_driver_init();
963 if (ret)
964 goto err_out;
965
966 ret = platform_driver_register(&ag71xx_driver);
967 if (ret)
968 goto err_mdio_exit;
969
970 return 0;
971
972 err_mdio_exit:
973 ag71xx_mdio_driver_exit();
974 err_out:
975 return ret;
976 }
977
978 static void __exit ag71xx_module_exit(void)
979 {
980 platform_driver_unregister(&ag71xx_driver);
981 ag71xx_mdio_driver_exit();
982 }
983
984 module_init(ag71xx_module_init);
985 module_exit(ag71xx_module_exit);
986
987 MODULE_VERSION(AG71XX_DRV_VERSION);
988 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
989 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
990 MODULE_LICENSE("GPL v2");
991 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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