2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level
= -1;
28 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
29 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
36 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
37 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
42 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
43 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
46 static void ag71xx_dump_regs(struct ag71xx
*ag
)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
51 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
52 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
53 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
54 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
58 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
59 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
63 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
68 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
69 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
72 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag
->dev
->name
, label
, intr
,
76 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
77 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
78 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
79 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
80 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
81 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
89 dma_free_coherent(NULL
, ring
->size
* ring
->desc_size
,
90 ring
->descs_cpu
, ring
->descs_dma
);
93 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
, unsigned int size
)
98 ring
->desc_size
= sizeof(struct ag71xx_desc
);
99 if (ring
->desc_size
% cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring
, ring
->desc_size
,
102 roundup(ring
->desc_size
, cache_line_size()));
103 ring
->desc_size
= roundup(ring
->desc_size
, cache_line_size());
106 ring
->descs_cpu
= dma_alloc_coherent(NULL
, size
* ring
->desc_size
,
107 &ring
->descs_dma
, GFP_ATOMIC
);
108 if (!ring
->descs_cpu
) {
115 ring
->buf
= kzalloc(size
* sizeof(*ring
->buf
), GFP_KERNEL
);
121 for (i
= 0; i
< size
; i
++) {
122 ring
->buf
[i
].desc
= (struct ag71xx_desc
*)&ring
->descs_cpu
[i
* ring
->desc_size
];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring
, i
, ring
->buf
[i
].desc
);
133 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
135 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
136 struct net_device
*dev
= ag
->dev
;
138 while (ring
->curr
!= ring
->dirty
) {
139 u32 i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
141 if (!ag71xx_desc_empty(ring
->buf
[i
].desc
)) {
142 ring
->buf
[i
].desc
->ctrl
= 0;
143 dev
->stats
.tx_errors
++;
146 if (ring
->buf
[i
].skb
)
147 dev_kfree_skb_any(ring
->buf
[i
].skb
);
149 ring
->buf
[i
].skb
= NULL
;
154 /* flush descriptors */
159 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
161 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
164 for (i
= 0; i
< AG71XX_TX_RING_SIZE
; i
++) {
165 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
166 ring
->desc_size
* ((i
+ 1) % AG71XX_TX_RING_SIZE
));
168 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
169 ring
->buf
[i
].skb
= NULL
;
172 /* flush descriptors */
179 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
181 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
187 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
188 if (ring
->buf
[i
].skb
) {
189 dma_unmap_single(&ag
->dev
->dev
, ring
->buf
[i
].dma_addr
,
190 AG71XX_RX_PKT_SIZE
, DMA_FROM_DEVICE
);
191 kfree_skb(ring
->buf
[i
].skb
);
195 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
197 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
202 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
203 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
204 ring
->desc_size
* ((i
+ 1) % AG71XX_RX_RING_SIZE
));
206 DBG("ag71xx: RX desc at %p, next is %08x\n",
208 ring
->buf
[i
].desc
->next
);
211 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
215 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
+ AG71XX_RX_PKT_RESERVE
);
222 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
224 dma_addr
= dma_map_single(&ag
->dev
->dev
, skb
->data
,
227 ring
->buf
[i
].skb
= skb
;
228 ring
->buf
[i
].dma_addr
= dma_addr
;
229 ring
->buf
[i
].desc
->data
= (u32
) dma_addr
;
230 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
233 /* flush descriptors */
242 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
244 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
248 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
251 i
= ring
->dirty
% AG71XX_RX_RING_SIZE
;
253 if (ring
->buf
[i
].skb
== NULL
) {
257 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
+
258 AG71XX_RX_PKT_RESERVE
);
262 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
265 dma_addr
= dma_map_single(&ag
->dev
->dev
, skb
->data
,
269 ring
->buf
[i
].skb
= skb
;
270 ring
->buf
[i
].dma_addr
= dma_addr
;
271 ring
->buf
[i
].desc
->data
= (u32
) dma_addr
;
274 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
278 /* flush descriptors */
281 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
286 static int ag71xx_rings_init(struct ag71xx
*ag
)
290 ret
= ag71xx_ring_alloc(&ag
->tx_ring
, AG71XX_TX_RING_SIZE
);
294 ag71xx_ring_tx_init(ag
);
296 ret
= ag71xx_ring_alloc(&ag
->rx_ring
, AG71XX_RX_RING_SIZE
);
300 ret
= ag71xx_ring_rx_init(ag
);
304 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
306 ag71xx_ring_rx_clean(ag
);
307 ag71xx_ring_free(&ag
->rx_ring
);
309 ag71xx_ring_tx_clean(ag
);
310 ag71xx_ring_free(&ag
->tx_ring
);
313 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
317 t
= (((u32
) mac
[0]) << 24) | (((u32
) mac
[1]) << 16)
318 | (((u32
) mac
[2]) << 8) | ((u32
) mac
[3]);
320 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
322 t
= (((u32
) mac
[4]) << 24) | (((u32
) mac
[5]) << 16);
323 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
326 static void ag71xx_dma_reset(struct ag71xx
*ag
)
331 ag71xx_dump_dma_regs(ag
);
334 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
335 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
337 /* clear descriptor addresses */
338 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, 0);
339 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, 0);
341 /* clear pending RX/TX interrupts */
342 for (i
= 0; i
< 256; i
++) {
343 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
344 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
347 /* clear pending errors */
348 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
349 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
351 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
353 printk(KERN_ALERT
"%s: unable to clear DMA Rx status: %08x\n",
356 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
358 /* mask out reserved bits */
362 printk(KERN_ALERT
"%s: unable to clear DMA Tx status: %08x\n",
365 ag71xx_dump_dma_regs(ag
);
368 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
369 MAC_CFG1_SRX | MAC_CFG1_STX)
371 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
373 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
374 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
375 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
376 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
377 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
380 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
381 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
382 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
383 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
384 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
385 FIFO_CFG5_17 | FIFO_CFG5_SF)
387 static void ag71xx_hw_init(struct ag71xx
*ag
)
389 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
391 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
394 ar71xx_device_stop(pdata
->reset_bit
);
396 ar71xx_device_start(pdata
->reset_bit
);
399 /* setup MAC configuration registers */
400 if (pdata
->is_ar724x
)
401 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
,
402 MAC_CFG1_INIT
| MAC_CFG1_TFC
| MAC_CFG1_RFC
);
404 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_INIT
);
406 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
407 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
409 /* setup max frame length */
410 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, AG71XX_TX_MTU_LEN
);
412 /* setup MII interface type */
413 ag71xx_mii_ctrl_set_if(ag
, pdata
->mii_if
);
415 /* setup FIFO configuration registers */
416 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
417 if (pdata
->is_ar724x
) {
418 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, pdata
->fifo_cfg1
);
419 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, pdata
->fifo_cfg2
);
421 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
422 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
424 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
425 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
427 ag71xx_dma_reset(ag
);
430 static void ag71xx_hw_start(struct ag71xx
*ag
)
432 /* start RX engine */
433 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
435 /* enable interrupts */
436 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
439 static void ag71xx_hw_stop(struct ag71xx
*ag
)
441 /* disable all interrupts */
442 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
444 ag71xx_dma_reset(ag
);
447 static int ag71xx_open(struct net_device
*dev
)
449 struct ag71xx
*ag
= netdev_priv(dev
);
452 ret
= ag71xx_rings_init(ag
);
456 napi_enable(&ag
->napi
);
458 netif_carrier_off(dev
);
459 ag71xx_phy_start(ag
);
461 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
462 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
464 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
468 netif_start_queue(dev
);
473 ag71xx_rings_cleanup(ag
);
477 static int ag71xx_stop(struct net_device
*dev
)
479 struct ag71xx
*ag
= netdev_priv(dev
);
482 spin_lock_irqsave(&ag
->lock
, flags
);
484 netif_stop_queue(dev
);
488 netif_carrier_off(dev
);
491 napi_disable(&ag
->napi
);
492 del_timer_sync(&ag
->oom_timer
);
494 spin_unlock_irqrestore(&ag
->lock
, flags
);
496 ag71xx_rings_cleanup(ag
);
501 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
502 struct net_device
*dev
)
504 struct ag71xx
*ag
= netdev_priv(dev
);
505 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
506 struct ag71xx_desc
*desc
;
510 i
= ring
->curr
% AG71XX_TX_RING_SIZE
;
511 desc
= ring
->buf
[i
].desc
;
513 if (!ag71xx_desc_empty(desc
))
516 ag71xx_add_ar8216_header(ag
, skb
);
519 DBG("%s: packet len is too small\n", ag
->dev
->name
);
523 dma_addr
= dma_map_single(&dev
->dev
, skb
->data
, skb
->len
,
526 ring
->buf
[i
].skb
= skb
;
528 /* setup descriptor fields */
529 desc
->data
= (u32
) dma_addr
;
530 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
532 /* flush descriptor */
536 if (ring
->curr
== (ring
->dirty
+ AG71XX_TX_THRES_STOP
)) {
537 DBG("%s: tx queue full\n", ag
->dev
->name
);
538 netif_stop_queue(dev
);
541 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
543 /* enable TX engine */
544 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
546 dev
->trans_start
= jiffies
;
551 dev
->stats
.tx_dropped
++;
557 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
559 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*) &ifr
->ifr_data
;
560 struct ag71xx
*ag
= netdev_priv(dev
);
565 if (ag
->phy_dev
== NULL
)
568 spin_lock_irq(&ag
->lock
);
569 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
570 spin_unlock_irq(&ag
->lock
);
575 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
581 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
588 if (ag
->phy_dev
== NULL
)
591 return phy_mii_ioctl(ag
->phy_dev
, data
, cmd
);
600 static void ag71xx_oom_timer_handler(unsigned long data
)
602 struct net_device
*dev
= (struct net_device
*) data
;
603 struct ag71xx
*ag
= netdev_priv(dev
);
605 napi_schedule(&ag
->napi
);
608 static void ag71xx_tx_timeout(struct net_device
*dev
)
610 struct ag71xx
*ag
= netdev_priv(dev
);
612 if (netif_msg_tx_err(ag
))
613 printk(KERN_DEBUG
"%s: tx timeout\n", ag
->dev
->name
);
615 schedule_work(&ag
->restart_work
);
618 static void ag71xx_restart_work_func(struct work_struct
*work
)
620 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
);
622 ag71xx_stop(ag
->dev
);
623 ag71xx_open(ag
->dev
);
626 static int ag71xx_tx_packets(struct ag71xx
*ag
)
628 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
631 DBG("%s: processing TX ring\n", ag
->dev
->name
);
634 while (ring
->dirty
!= ring
->curr
) {
635 unsigned int i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
636 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
637 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
639 if (!ag71xx_desc_empty(desc
))
642 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
644 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
645 ag
->dev
->stats
.tx_packets
++;
647 dev_kfree_skb_any(skb
);
648 ring
->buf
[i
].skb
= NULL
;
654 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
656 if ((ring
->curr
- ring
->dirty
) < AG71XX_TX_THRES_WAKEUP
)
657 netif_wake_queue(ag
->dev
);
662 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
664 struct net_device
*dev
= ag
->dev
;
665 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
668 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
669 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
671 while (done
< limit
) {
672 unsigned int i
= ring
->curr
% AG71XX_RX_RING_SIZE
;
673 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
677 if (ag71xx_desc_empty(desc
))
680 if ((ring
->dirty
+ AG71XX_RX_RING_SIZE
) == ring
->curr
) {
685 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
687 skb
= ring
->buf
[i
].skb
;
688 pktlen
= ag71xx_desc_pktlen(desc
);
689 pktlen
-= ETH_FCS_LEN
;
691 dma_unmap_single(&dev
->dev
, ring
->buf
[i
].dma_addr
,
692 AG71XX_RX_PKT_SIZE
, DMA_FROM_DEVICE
);
694 skb_put(skb
, pktlen
);
697 skb
->ip_summed
= CHECKSUM_NONE
;
699 dev
->last_rx
= jiffies
;
700 dev
->stats
.rx_packets
++;
701 dev
->stats
.rx_bytes
+= pktlen
;
703 if (ag71xx_remove_ar8216_header(ag
, skb
) != 0) {
704 dev
->stats
.rx_dropped
++;
707 skb
->protocol
= eth_type_trans(skb
, dev
);
708 netif_receive_skb(skb
);
711 ring
->buf
[i
].skb
= NULL
;
717 ag71xx_ring_rx_refill(ag
);
719 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
720 dev
->name
, ring
->curr
, ring
->dirty
, done
);
725 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
727 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
728 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
729 struct net_device
*dev
= ag
->dev
;
730 struct ag71xx_ring
*rx_ring
;
737 tx_done
= ag71xx_tx_packets(ag
);
739 DBG("%s: processing RX ring\n", dev
->name
);
740 rx_done
= ag71xx_rx_packets(ag
, limit
);
742 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
744 rx_ring
= &ag
->rx_ring
;
745 if (rx_ring
->buf
[rx_ring
->dirty
% AG71XX_RX_RING_SIZE
].skb
== NULL
)
748 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
749 if (unlikely(status
& RX_STATUS_OF
)) {
750 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
751 dev
->stats
.rx_fifo_errors
++;
754 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
757 if (rx_done
< limit
) {
758 if (status
& RX_STATUS_PR
)
761 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
762 if (status
& TX_STATUS_PS
)
765 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
766 dev
->name
, rx_done
, tx_done
, limit
);
770 /* enable interrupts */
771 spin_lock_irqsave(&ag
->lock
, flags
);
772 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
773 spin_unlock_irqrestore(&ag
->lock
, flags
);
778 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
779 dev
->name
, rx_done
, tx_done
, limit
);
783 if (netif_msg_rx_err(ag
))
784 printk(KERN_DEBUG
"%s: out of memory\n", dev
->name
);
786 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
791 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
793 struct net_device
*dev
= dev_id
;
794 struct ag71xx
*ag
= netdev_priv(dev
);
797 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
798 ag71xx_dump_intr(ag
, "raw", status
);
800 if (unlikely(!status
))
803 if (unlikely(status
& AG71XX_INT_ERR
)) {
804 if (status
& AG71XX_INT_TX_BE
) {
805 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
806 dev_err(&dev
->dev
, "TX BUS error\n");
808 if (status
& AG71XX_INT_RX_BE
) {
809 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
810 dev_err(&dev
->dev
, "RX BUS error\n");
814 if (likely(status
& AG71XX_INT_POLL
)) {
815 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
816 DBG("%s: enable polling mode\n", dev
->name
);
817 napi_schedule(&ag
->napi
);
820 ag71xx_debugfs_update_int_stats(ag
, status
);
825 static void ag71xx_set_multicast_list(struct net_device
*dev
)
830 static const struct net_device_ops ag71xx_netdev_ops
= {
831 .ndo_open
= ag71xx_open
,
832 .ndo_stop
= ag71xx_stop
,
833 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
834 .ndo_set_multicast_list
= ag71xx_set_multicast_list
,
835 .ndo_do_ioctl
= ag71xx_do_ioctl
,
836 .ndo_tx_timeout
= ag71xx_tx_timeout
,
837 .ndo_change_mtu
= eth_change_mtu
,
838 .ndo_set_mac_address
= eth_mac_addr
,
839 .ndo_validate_addr
= eth_validate_addr
,
842 static int __init
ag71xx_probe(struct platform_device
*pdev
)
844 struct net_device
*dev
;
845 struct resource
*res
;
847 struct ag71xx_platform_data
*pdata
;
850 pdata
= pdev
->dev
.platform_data
;
852 dev_err(&pdev
->dev
, "no platform data specified\n");
857 if (pdata
->mii_bus_dev
== NULL
) {
858 dev_err(&pdev
->dev
, "no MII bus device specified\n");
863 dev
= alloc_etherdev(sizeof(*ag
));
865 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
870 SET_NETDEV_DEV(dev
, &pdev
->dev
);
872 ag
= netdev_priv(dev
);
875 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
876 AG71XX_DEFAULT_MSG_ENABLE
);
877 spin_lock_init(&ag
->lock
);
879 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
881 dev_err(&pdev
->dev
, "no mac_base resource found\n");
886 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
888 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
893 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mii_ctrl");
895 dev_err(&pdev
->dev
, "no mii_ctrl resource found\n");
900 ag
->mii_ctrl
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
902 dev_err(&pdev
->dev
, "unable to ioremap mii_ctrl\n");
907 dev
->irq
= platform_get_irq(pdev
, 0);
908 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
909 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
912 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
913 goto err_unmap_mii_ctrl
;
916 dev
->base_addr
= (unsigned long)ag
->mac_base
;
917 dev
->netdev_ops
= &ag71xx_netdev_ops
;
918 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
920 INIT_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
922 init_timer(&ag
->oom_timer
);
923 ag
->oom_timer
.data
= (unsigned long) dev
;
924 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
926 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
928 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
930 err
= register_netdev(dev
);
932 dev_err(&pdev
->dev
, "unable to register net device\n");
936 printk(KERN_INFO
"%s: Atheros AG71xx at 0x%08lx, irq %d\n",
937 dev
->name
, dev
->base_addr
, dev
->irq
);
939 ag71xx_dump_regs(ag
);
943 ag71xx_dump_regs(ag
);
945 err
= ag71xx_phy_connect(ag
);
947 goto err_unregister_netdev
;
949 err
= ag71xx_debugfs_init(ag
);
951 goto err_phy_disconnect
;
953 platform_set_drvdata(pdev
, dev
);
958 ag71xx_phy_disconnect(ag
);
959 err_unregister_netdev
:
960 unregister_netdev(dev
);
962 free_irq(dev
->irq
, dev
);
964 iounmap(ag
->mii_ctrl
);
966 iounmap(ag
->mac_base
);
970 platform_set_drvdata(pdev
, NULL
);
974 static int __exit
ag71xx_remove(struct platform_device
*pdev
)
976 struct net_device
*dev
= platform_get_drvdata(pdev
);
979 struct ag71xx
*ag
= netdev_priv(dev
);
981 ag71xx_debugfs_exit(ag
);
982 ag71xx_phy_disconnect(ag
);
983 unregister_netdev(dev
);
984 free_irq(dev
->irq
, dev
);
985 iounmap(ag
->mii_ctrl
);
986 iounmap(ag
->mac_base
);
988 platform_set_drvdata(pdev
, NULL
);
994 static struct platform_driver ag71xx_driver
= {
995 .probe
= ag71xx_probe
,
996 .remove
= __exit_p(ag71xx_remove
),
998 .name
= AG71XX_DRV_NAME
,
1002 static int __init
ag71xx_module_init(void)
1006 ret
= ag71xx_debugfs_root_init();
1010 ret
= ag71xx_mdio_driver_init();
1012 goto err_debugfs_exit
;
1014 ret
= platform_driver_register(&ag71xx_driver
);
1021 ag71xx_mdio_driver_exit();
1023 ag71xx_debugfs_root_exit();
1028 static void __exit
ag71xx_module_exit(void)
1030 platform_driver_unregister(&ag71xx_driver
);
1031 ag71xx_mdio_driver_exit();
1032 ag71xx_debugfs_root_exit();
1035 module_init(ag71xx_module_init
);
1036 module_exit(ag71xx_module_exit
);
1038 MODULE_VERSION(AG71XX_DRV_VERSION
);
1039 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1040 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1041 MODULE_LICENSE("GPL v2");
1042 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);