2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug
= -1;
28 module_param(ag71xx_debug
, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug
, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_regs(struct ag71xx
*ag
)
33 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
35 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
36 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
37 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
38 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
39 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
40 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
42 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
43 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
44 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
45 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
47 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
48 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
49 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
50 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
52 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
53 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
54 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
57 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
62 dma_free_coherent(NULL
, ring
->size
* sizeof(*ring
->descs
),
63 ring
->descs
, ring
->descs_dma
);
66 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
, unsigned int size
)
70 ring
->descs
= dma_alloc_coherent(NULL
, size
* sizeof(*ring
->descs
),
80 ring
->buf
= kzalloc(size
* sizeof(*ring
->buf
), GFP_KERNEL
);
92 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
94 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
95 struct net_device
*dev
= ag
->dev
;
97 while (ring
->curr
!= ring
->dirty
) {
98 u32 i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
100 if (!ag71xx_desc_empty(&ring
->descs
[i
])) {
101 ring
->descs
[i
].ctrl
= 0;
102 dev
->stats
.tx_errors
++;
105 if (ring
->buf
[i
].skb
)
106 dev_kfree_skb_any(ring
->buf
[i
].skb
);
108 ring
->buf
[i
].skb
= NULL
;
113 /* flush descriptors */
118 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
120 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
123 for (i
= 0; i
< AG71XX_TX_RING_SIZE
; i
++) {
124 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
125 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_TX_RING_SIZE
));
127 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
128 ring
->buf
[i
].skb
= NULL
;
131 /* flush descriptors */
138 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
140 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
146 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
147 if (ring
->buf
[i
].skb
)
148 kfree_skb(ring
->buf
[i
].skb
);
152 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
154 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
159 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
160 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
161 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_RX_RING_SIZE
));
163 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
166 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
173 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
175 ring
->buf
[i
].skb
= skb
;
176 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
177 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
180 /* flush descriptors */
189 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
191 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
195 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
198 i
= ring
->dirty
% AG71XX_RX_RING_SIZE
;
200 if (ring
->buf
[i
].skb
== NULL
) {
203 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
205 printk(KERN_ERR
"%s: no memory for skb\n",
210 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
212 ring
->buf
[i
].skb
= skb
;
213 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
216 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
220 /* flush descriptors */
223 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
228 static int ag71xx_rings_init(struct ag71xx
*ag
)
232 ret
= ag71xx_ring_alloc(&ag
->tx_ring
, AG71XX_TX_RING_SIZE
);
236 ag71xx_ring_tx_init(ag
);
238 ret
= ag71xx_ring_alloc(&ag
->rx_ring
, AG71XX_RX_RING_SIZE
);
242 ret
= ag71xx_ring_rx_init(ag
);
246 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
248 ag71xx_ring_rx_clean(ag
);
249 ag71xx_ring_free(&ag
->rx_ring
);
251 ag71xx_ring_tx_clean(ag
);
252 ag71xx_ring_free(&ag
->tx_ring
);
255 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
259 t
= (((u32
) mac
[0]) << 24) | (((u32
) mac
[1]) << 16)
260 | (((u32
) mac
[2]) << 8) | ((u32
) mac
[2]);
262 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
264 t
= (((u32
) mac
[4]) << 24) | (((u32
) mac
[5]) << 16);
265 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
268 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
269 MAC_CFG1_SRX | MAC_CFG1_STX)
270 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
272 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
273 MAC_CFG1_SRX | MAC_CFG1_STX | \
274 MAC_CFG1_TFC | MAC_CFG1_RFC)
275 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
277 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
279 static void ag71xx_hw_init(struct ag71xx
*ag
)
281 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
283 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
286 ar71xx_device_stop(pdata
->reset_bit
);
288 ar71xx_device_start(pdata
->reset_bit
);
291 /* setup MII interface type */
292 ag71xx_mii_ctrl_set_if(ag
, pdata
->mii_if
);
294 /* setup MAC configuration registers */
295 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
,
296 pdata
->is_ar91xx
? AR91XX_MAC_CFG1_INIT
: AR71XX_MAC_CFG1_INIT
);
297 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
298 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
300 /* setup max frame length */
301 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, AG71XX_TX_MTU_LEN
);
303 /* setup FIFO configuration registers */
304 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
305 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
306 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
307 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, 0x0000ffff);
308 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
,
309 pdata
->is_ar91xx
? AR91XX_FIFO_CFG5_INIT
310 : AR71XX_FIFO_CFG5_INIT
);
313 static void ag71xx_hw_start(struct ag71xx
*ag
)
315 /* start RX engine */
316 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
318 /* enable interrupts */
319 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
322 static void ag71xx_hw_stop(struct ag71xx
*ag
)
325 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
326 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
328 /* disable all interrupts */
329 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
332 static int ag71xx_open(struct net_device
*dev
)
334 struct ag71xx
*ag
= netdev_priv(dev
);
337 ret
= ag71xx_rings_init(ag
);
341 napi_enable(&ag
->napi
);
343 netif_carrier_off(dev
);
344 ag71xx_phy_start(ag
);
346 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
347 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
349 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
353 netif_start_queue(dev
);
358 ag71xx_rings_cleanup(ag
);
362 static int ag71xx_stop(struct net_device
*dev
)
364 struct ag71xx
*ag
= netdev_priv(dev
);
367 spin_lock_irqsave(&ag
->lock
, flags
);
369 netif_stop_queue(dev
);
373 netif_carrier_off(dev
);
376 napi_disable(&ag
->napi
);
378 spin_unlock_irqrestore(&ag
->lock
, flags
);
380 ag71xx_rings_cleanup(ag
);
385 static int ag71xx_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
387 struct ag71xx
*ag
= netdev_priv(dev
);
388 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
389 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
390 struct ag71xx_desc
*desc
;
394 i
= ring
->curr
% AG71XX_TX_RING_SIZE
;
395 desc
= &ring
->descs
[i
];
397 spin_lock_irqsave(&ag
->lock
, flags
);
399 spin_unlock_irqrestore(&ag
->lock
, flags
);
401 if (!ag71xx_desc_empty(desc
))
405 DBG("%s: packet len is too small\n", ag
->dev
->name
);
409 dma_cache_wback_inv((unsigned long)skb
->data
, skb
->len
);
411 ring
->buf
[i
].skb
= skb
;
413 /* setup descriptor fields */
414 desc
->data
= virt_to_phys(skb
->data
);
415 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
417 /* flush descriptor */
421 if (ring
->curr
== (ring
->dirty
+ AG71XX_TX_THRES_STOP
)) {
422 DBG("%s: tx queue full\n", ag
->dev
->name
);
423 netif_stop_queue(dev
);
426 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
428 /* enable TX engine */
429 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
431 dev
->trans_start
= jiffies
;
436 dev
->stats
.tx_dropped
++;
442 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
444 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*) &ifr
->ifr_data
;
445 struct ag71xx
*ag
= netdev_priv(dev
);
450 if (ag
->phy_dev
== NULL
)
453 spin_lock_irq(&ag
->lock
);
454 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
455 spin_unlock_irq(&ag
->lock
);
460 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
466 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
473 if (ag
->phy_dev
== NULL
)
476 return phy_mii_ioctl(ag
->phy_dev
, data
, cmd
);
485 static void ag71xx_tx_packets(struct ag71xx
*ag
)
487 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
488 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
491 DBG("%s: processing TX ring\n", ag
->dev
->name
);
493 #ifdef AG71XX_NAPI_TX
498 while (ring
->dirty
!= ring
->curr
) {
499 unsigned int i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
500 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
501 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
503 if (!ag71xx_desc_empty(desc
))
506 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
508 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
509 ag
->dev
->stats
.tx_packets
++;
511 dev_kfree_skb_any(skb
);
512 ring
->buf
[i
].skb
= NULL
;
518 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
520 if ((ring
->curr
- ring
->dirty
) < AG71XX_TX_THRES_WAKEUP
)
521 netif_wake_queue(ag
->dev
);
525 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
527 struct net_device
*dev
= ag
->dev
;
528 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
529 #ifndef AG71XX_NAPI_TX
530 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
535 #ifndef AG71XX_NAPI_TX
536 spin_lock_irqsave(&ag
->lock
, flags
);
538 spin_unlock_irqrestore(&ag
->lock
, flags
);
541 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
542 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
544 while (done
< limit
) {
545 unsigned int i
= ring
->curr
% AG71XX_RX_RING_SIZE
;
546 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
550 if (ag71xx_desc_empty(desc
))
553 if ((ring
->dirty
+ AG71XX_RX_RING_SIZE
) == ring
->curr
) {
558 skb
= ring
->buf
[i
].skb
;
559 pktlen
= ag71xx_desc_pktlen(desc
);
560 pktlen
-= ETH_FCS_LEN
;
562 /* TODO: move it into the refill function */
563 dma_cache_wback_inv((unsigned long)skb
->data
, pktlen
);
564 skb_put(skb
, pktlen
);
567 skb
->protocol
= eth_type_trans(skb
, dev
);
568 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
570 netif_receive_skb(skb
);
572 dev
->last_rx
= jiffies
;
573 dev
->stats
.rx_packets
++;
574 dev
->stats
.rx_bytes
+= pktlen
;
576 ring
->buf
[i
].skb
= NULL
;
579 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
582 if ((ring
->curr
- ring
->dirty
) > (AG71XX_RX_RING_SIZE
/ 4))
583 ag71xx_ring_rx_refill(ag
);
586 ag71xx_ring_rx_refill(ag
);
588 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
589 dev
->name
, ring
->curr
, ring
->dirty
, done
);
594 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
596 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
597 #ifdef AG71XX_NAPI_TX
598 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
600 struct net_device
*dev
= ag
->dev
;
605 #ifdef AG71XX_NAPI_TX
607 ag71xx_tx_packets(ag
);
610 DBG("%s: processing RX ring\n", dev
->name
);
611 done
= ag71xx_rx_packets(ag
, limit
);
613 /* TODO: add OOM handler */
615 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
616 status
&= AG71XX_INT_POLL
;
618 if ((done
< limit
) && (!status
)) {
619 DBG("%s: disable polling mode, done=%d, status=%x\n",
620 dev
->name
, done
, status
);
622 netif_rx_complete(dev
, napi
);
624 /* enable interrupts */
625 spin_lock_irqsave(&ag
->lock
, flags
);
626 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
627 spin_unlock_irqrestore(&ag
->lock
, flags
);
631 if (status
& AG71XX_INT_RX_OF
) {
632 if (netif_msg_rx_err(ag
))
633 printk(KERN_ALERT
"%s: rx owerflow, restarting dma\n",
637 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
639 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
642 DBG("%s: stay in polling mode, done=%d, status=%x\n",
643 dev
->name
, done
, status
);
647 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
649 struct net_device
*dev
= dev_id
;
650 struct ag71xx
*ag
= netdev_priv(dev
);
653 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
654 status
&= ag71xx_rr(ag
, AG71XX_REG_INT_ENABLE
);
656 if (unlikely(!status
))
659 if (unlikely(status
& AG71XX_INT_ERR
)) {
660 if (status
& AG71XX_INT_TX_BE
) {
661 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
662 dev_err(&dev
->dev
, "TX BUS error\n");
664 if (status
& AG71XX_INT_RX_BE
) {
665 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
666 dev_err(&dev
->dev
, "RX BUS error\n");
671 if (unlikely(status
& AG71XX_INT_TX_UR
)) {
672 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_UR
);
673 DBG("%s: TX underrun\n", dev
->name
);
677 #ifndef AG71XX_NAPI_TX
678 if (likely(status
& AG71XX_INT_TX_PS
))
679 ag71xx_tx_packets(ag
);
682 if (likely(status
& AG71XX_INT_POLL
)) {
683 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
684 DBG("%s: enable polling mode\n", dev
->name
);
685 netif_rx_schedule(dev
, &ag
->napi
);
691 static void ag71xx_set_multicast_list(struct net_device
*dev
)
696 static int __init
ag71xx_probe(struct platform_device
*pdev
)
698 struct net_device
*dev
;
699 struct resource
*res
;
701 struct ag71xx_platform_data
*pdata
;
704 pdata
= pdev
->dev
.platform_data
;
706 dev_err(&pdev
->dev
, "no platform data specified\n");
711 dev
= alloc_etherdev(sizeof(*ag
));
713 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
718 SET_NETDEV_DEV(dev
, &pdev
->dev
);
720 ag
= netdev_priv(dev
);
723 ag
->mii_bus
= &ag71xx_mdio_bus
->mii_bus
;
724 ag
->msg_enable
= netif_msg_init(ag71xx_debug
,
725 AG71XX_DEFAULT_MSG_ENABLE
);
726 spin_lock_init(&ag
->lock
);
728 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
730 dev_err(&pdev
->dev
, "no mac_base resource found\n");
735 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
737 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
742 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base2");
744 dev_err(&pdev
->dev
, "no mac_base2 resource found\n");
746 goto err_unmap_base1
;
749 ag
->mac_base2
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
751 dev_err(&pdev
->dev
, "unable to ioremap mac_base2\n");
753 goto err_unmap_base1
;
756 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mii_ctrl");
758 dev_err(&pdev
->dev
, "no mii_ctrl resource found\n");
760 goto err_unmap_base2
;
763 ag
->mii_ctrl
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
765 dev_err(&pdev
->dev
, "unable to ioremap mii_ctrl\n");
767 goto err_unmap_base2
;
770 dev
->irq
= platform_get_irq(pdev
, 0);
771 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
772 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
775 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
776 goto err_unmap_mii_ctrl
;
779 dev
->base_addr
= (unsigned long)ag
->mac_base
;
780 dev
->open
= ag71xx_open
;
781 dev
->stop
= ag71xx_stop
;
782 dev
->hard_start_xmit
= ag71xx_hard_start_xmit
;
783 dev
->set_multicast_list
= ag71xx_set_multicast_list
;
784 dev
->do_ioctl
= ag71xx_do_ioctl
;
785 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
787 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
789 if (is_valid_ether_addr(pdata
->mac_addr
))
790 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
792 dev
->dev_addr
[0] = 0xde;
793 dev
->dev_addr
[1] = 0xad;
794 get_random_bytes(&dev
->dev_addr
[2], 3);
795 dev
->dev_addr
[5] = pdev
->id
& 0xff;
798 err
= register_netdev(dev
);
800 dev_err(&pdev
->dev
, "unable to register net device\n");
804 printk(KERN_INFO
"%s: Atheros AG71xx at 0x%08lx, irq %d\n",
805 dev
->name
, dev
->base_addr
, dev
->irq
);
807 ag71xx_dump_regs(ag
);
811 ag71xx_dump_regs(ag
);
813 /* Reset the mdio bus explicitly */
815 mutex_lock(&ag
->mii_bus
->mdio_lock
);
816 ag
->mii_bus
->reset(ag
->mii_bus
);
817 mutex_unlock(&ag
->mii_bus
->mdio_lock
);
820 err
= ag71xx_phy_connect(ag
);
822 goto err_unregister_netdev
;
824 platform_set_drvdata(pdev
, dev
);
828 err_unregister_netdev
:
829 unregister_netdev(dev
);
831 free_irq(dev
->irq
, dev
);
833 iounmap(ag
->mii_ctrl
);
835 iounmap(ag
->mac_base2
);
837 iounmap(ag
->mac_base
);
841 platform_set_drvdata(pdev
, NULL
);
845 static int __exit
ag71xx_remove(struct platform_device
*pdev
)
847 struct net_device
*dev
= platform_get_drvdata(pdev
);
850 struct ag71xx
*ag
= netdev_priv(dev
);
852 ag71xx_phy_disconnect(ag
);
853 unregister_netdev(dev
);
854 free_irq(dev
->irq
, dev
);
855 iounmap(ag
->mii_ctrl
);
856 iounmap(ag
->mac_base2
);
857 iounmap(ag
->mac_base
);
859 platform_set_drvdata(pdev
, NULL
);
865 static struct platform_driver ag71xx_driver
= {
866 .probe
= ag71xx_probe
,
867 .remove
= __exit_p(ag71xx_remove
),
869 .name
= AG71XX_DRV_NAME
,
873 static int __init
ag71xx_module_init(void)
877 ret
= ag71xx_mdio_driver_init();
881 ret
= platform_driver_register(&ag71xx_driver
);
888 ag71xx_mdio_driver_exit();
893 static void __exit
ag71xx_module_exit(void)
895 platform_driver_unregister(&ag71xx_driver
);
896 ag71xx_mdio_driver_exit();
899 module_init(ag71xx_module_init
);
900 module_exit(ag71xx_module_exit
);
902 MODULE_VERSION(AG71XX_DRV_VERSION
);
903 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
904 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
905 MODULE_LICENSE("GPL v2");
906 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);