2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
34 #include <linux/bitops.h>
36 #include <asm/mach-ath79/ar71xx_regs.h>
37 #include <asm/mach-ath79/ath79.h>
38 #include <asm/mach-ath79/ag71xx_platform.h>
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.35"
44 * For our NAPI weight bigger does *NOT* mean better - it means more
45 * D-cache misses and lots more wasted cycles than we'll ever
46 * possibly gain from saving instructions.
48 #define AG71XX_NAPI_WEIGHT 32
49 #define AG71XX_OOM_REFILL (1 + HZ/10)
51 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
52 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
53 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
55 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
56 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
58 #define AG71XX_TX_MTU_LEN 1540
60 #define AG71XX_TX_RING_SPLIT 512
61 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
63 #define AG71XX_TX_RING_SIZE_DEFAULT 128
64 #define AG71XX_RX_RING_SIZE_DEFAULT 256
66 #define AG71XX_TX_RING_SIZE_MAX 128
67 #define AG71XX_RX_RING_SIZE_MAX 256
69 #ifdef CONFIG_AG71XX_DEBUG
70 #define DBG(fmt, args...) pr_debug(fmt, ## args)
72 #define DBG(fmt, args...) do {} while (0)
75 #define ag71xx_assert(_cond) \
79 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
86 #define DESC_EMPTY BIT(31)
87 #define DESC_MORE BIT(24)
88 #define DESC_PKTLEN_M 0xfff
91 } __attribute__((aligned(4)));
93 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
103 unsigned long timestamp
;
109 struct ag71xx_buf
*buf
;
111 dma_addr_t descs_dma
;
119 struct mii_bus
*mii_bus
;
120 int mii_irq
[PHY_MAX_ADDR
];
121 void __iomem
*mdio_base
;
122 struct ag71xx_mdio_platform_data
*pdata
;
125 struct ag71xx_int_stats
{
135 struct ag71xx_napi_stats
{
136 unsigned long napi_calls
;
137 unsigned long rx_count
;
138 unsigned long rx_packets
;
139 unsigned long rx_packets_max
;
140 unsigned long tx_count
;
141 unsigned long tx_packets
;
142 unsigned long tx_packets_max
;
144 unsigned long rx
[AG71XX_NAPI_WEIGHT
+ 1];
145 unsigned long tx
[AG71XX_NAPI_WEIGHT
+ 1];
148 struct ag71xx_debug
{
149 struct dentry
*debugfs_dir
;
151 struct ag71xx_int_stats int_stats
;
152 struct ag71xx_napi_stats napi_stats
;
156 void __iomem
*mac_base
;
159 struct platform_device
*pdev
;
160 struct net_device
*dev
;
161 struct napi_struct napi
;
164 struct ag71xx_desc
*stop_desc
;
165 dma_addr_t stop_desc_dma
;
167 struct ag71xx_ring rx_ring
;
168 struct ag71xx_ring tx_ring
;
170 struct mii_bus
*mii_bus
;
171 struct phy_device
*phy_dev
;
178 unsigned int max_frame_len
;
179 unsigned int desc_pktlen_mask
;
180 unsigned int rx_buf_size
;
182 struct delayed_work restart_work
;
183 struct delayed_work link_work
;
184 struct timer_list oom_timer
;
186 #ifdef CONFIG_AG71XX_DEBUG_FS
187 struct ag71xx_debug debug
;
191 extern struct ethtool_ops ag71xx_ethtool_ops
;
192 void ag71xx_link_adjust(struct ag71xx
*ag
);
194 int ag71xx_mdio_driver_init(void) __init
;
195 void ag71xx_mdio_driver_exit(void);
197 int ag71xx_phy_connect(struct ag71xx
*ag
);
198 void ag71xx_phy_disconnect(struct ag71xx
*ag
);
199 void ag71xx_phy_start(struct ag71xx
*ag
);
200 void ag71xx_phy_stop(struct ag71xx
*ag
);
202 static inline struct ag71xx_platform_data
*ag71xx_get_pdata(struct ag71xx
*ag
)
204 return ag
->pdev
->dev
.platform_data
;
207 static inline int ag71xx_desc_empty(struct ag71xx_desc
*desc
)
209 return (desc
->ctrl
& DESC_EMPTY
) != 0;
212 static inline struct ag71xx_desc
*
213 ag71xx_ring_desc(struct ag71xx_ring
*ring
, int idx
)
215 return (struct ag71xx_desc
*) &ring
->descs_cpu
[idx
* AG71XX_DESC_SIZE
];
219 ag71xx_ring_size_order(int size
)
221 return fls(size
- 1);
224 /* Register offsets */
225 #define AG71XX_REG_MAC_CFG1 0x0000
226 #define AG71XX_REG_MAC_CFG2 0x0004
227 #define AG71XX_REG_MAC_IPG 0x0008
228 #define AG71XX_REG_MAC_HDX 0x000c
229 #define AG71XX_REG_MAC_MFL 0x0010
230 #define AG71XX_REG_MII_CFG 0x0020
231 #define AG71XX_REG_MII_CMD 0x0024
232 #define AG71XX_REG_MII_ADDR 0x0028
233 #define AG71XX_REG_MII_CTRL 0x002c
234 #define AG71XX_REG_MII_STATUS 0x0030
235 #define AG71XX_REG_MII_IND 0x0034
236 #define AG71XX_REG_MAC_IFCTL 0x0038
237 #define AG71XX_REG_MAC_ADDR1 0x0040
238 #define AG71XX_REG_MAC_ADDR2 0x0044
239 #define AG71XX_REG_FIFO_CFG0 0x0048
240 #define AG71XX_REG_FIFO_CFG1 0x004c
241 #define AG71XX_REG_FIFO_CFG2 0x0050
242 #define AG71XX_REG_FIFO_CFG3 0x0054
243 #define AG71XX_REG_FIFO_CFG4 0x0058
244 #define AG71XX_REG_FIFO_CFG5 0x005c
245 #define AG71XX_REG_FIFO_RAM0 0x0060
246 #define AG71XX_REG_FIFO_RAM1 0x0064
247 #define AG71XX_REG_FIFO_RAM2 0x0068
248 #define AG71XX_REG_FIFO_RAM3 0x006c
249 #define AG71XX_REG_FIFO_RAM4 0x0070
250 #define AG71XX_REG_FIFO_RAM5 0x0074
251 #define AG71XX_REG_FIFO_RAM6 0x0078
252 #define AG71XX_REG_FIFO_RAM7 0x007c
254 #define AG71XX_REG_TX_CTRL 0x0180
255 #define AG71XX_REG_TX_DESC 0x0184
256 #define AG71XX_REG_TX_STATUS 0x0188
257 #define AG71XX_REG_RX_CTRL 0x018c
258 #define AG71XX_REG_RX_DESC 0x0190
259 #define AG71XX_REG_RX_STATUS 0x0194
260 #define AG71XX_REG_INT_ENABLE 0x0198
261 #define AG71XX_REG_INT_STATUS 0x019c
263 #define AG71XX_REG_FIFO_DEPTH 0x01a8
264 #define AG71XX_REG_RX_SM 0x01b0
265 #define AG71XX_REG_TX_SM 0x01b4
267 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
268 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
269 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
270 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
271 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
272 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
273 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
274 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
276 #define MAC_CFG2_FDX BIT(0)
277 #define MAC_CFG2_CRC_EN BIT(1)
278 #define MAC_CFG2_PAD_CRC_EN BIT(2)
279 #define MAC_CFG2_LEN_CHECK BIT(4)
280 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
281 #define MAC_CFG2_IF_1000 BIT(9)
282 #define MAC_CFG2_IF_10_100 BIT(8)
284 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
285 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
286 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
287 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
288 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
289 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
290 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
292 #define FIFO_CFG0_ENABLE_SHIFT 8
294 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
295 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
296 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
297 #define FIFO_CFG4_CE BIT(3) /* Code Error */
298 #define FIFO_CFG4_CR BIT(4) /* CRC error */
299 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
300 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
301 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
302 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
303 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
304 #define FIFO_CFG4_DR BIT(10) /* Dribble */
305 #define FIFO_CFG4_LE BIT(11) /* Long Event */
306 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
307 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
308 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
309 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
310 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
311 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
313 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
314 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
315 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
316 #define FIFO_CFG5_CE BIT(3) /* Code Error */
317 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
318 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
319 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
320 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
321 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
322 #define FIFO_CFG5_DR BIT(9) /* Dribble */
323 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
324 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
325 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
326 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
327 #define FIFO_CFG5_LE BIT(14) /* Long Event */
328 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
329 #define FIFO_CFG5_16 BIT(16) /* unknown */
330 #define FIFO_CFG5_17 BIT(17) /* unknown */
331 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
332 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
334 #define AG71XX_INT_TX_PS BIT(0)
335 #define AG71XX_INT_TX_UR BIT(1)
336 #define AG71XX_INT_TX_BE BIT(3)
337 #define AG71XX_INT_RX_PR BIT(4)
338 #define AG71XX_INT_RX_OF BIT(6)
339 #define AG71XX_INT_RX_BE BIT(7)
341 #define MAC_IFCTL_SPEED BIT(16)
343 #define MII_CFG_CLK_DIV_4 0
344 #define MII_CFG_CLK_DIV_6 2
345 #define MII_CFG_CLK_DIV_8 3
346 #define MII_CFG_CLK_DIV_10 4
347 #define MII_CFG_CLK_DIV_14 5
348 #define MII_CFG_CLK_DIV_20 6
349 #define MII_CFG_CLK_DIV_28 7
350 #define MII_CFG_CLK_DIV_34 8
351 #define MII_CFG_CLK_DIV_42 9
352 #define MII_CFG_CLK_DIV_50 10
353 #define MII_CFG_CLK_DIV_58 11
354 #define MII_CFG_CLK_DIV_66 12
355 #define MII_CFG_CLK_DIV_74 13
356 #define MII_CFG_CLK_DIV_82 14
357 #define MII_CFG_CLK_DIV_98 15
358 #define MII_CFG_RESET BIT(31)
360 #define MII_CMD_WRITE 0x0
361 #define MII_CMD_READ 0x1
362 #define MII_ADDR_SHIFT 8
363 #define MII_IND_BUSY BIT(0)
364 #define MII_IND_INVALID BIT(2)
366 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
368 #define TX_STATUS_PS BIT(0) /* Packet Sent */
369 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
370 #define TX_STATUS_BE BIT(3) /* Bus Error */
372 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
374 #define RX_STATUS_PR BIT(0) /* Packet Received */
375 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
376 #define RX_STATUS_BE BIT(3) /* Bus Error */
378 static inline void ag71xx_check_reg_offset(struct ag71xx
*ag
, unsigned reg
)
381 case AG71XX_REG_MAC_CFG1
... AG71XX_REG_MAC_MFL
:
382 case AG71XX_REG_MAC_IFCTL
... AG71XX_REG_TX_SM
:
383 case AG71XX_REG_MII_CFG
:
391 static inline void ag71xx_wr(struct ag71xx
*ag
, unsigned reg
, u32 value
)
393 ag71xx_check_reg_offset(ag
, reg
);
395 __raw_writel(value
, ag
->mac_base
+ reg
);
397 (void) __raw_readl(ag
->mac_base
+ reg
);
400 static inline u32
ag71xx_rr(struct ag71xx
*ag
, unsigned reg
)
402 ag71xx_check_reg_offset(ag
, reg
);
404 return __raw_readl(ag
->mac_base
+ reg
);
407 static inline void ag71xx_sb(struct ag71xx
*ag
, unsigned reg
, u32 mask
)
411 ag71xx_check_reg_offset(ag
, reg
);
413 r
= ag
->mac_base
+ reg
;
414 __raw_writel(__raw_readl(r
) | mask
, r
);
416 (void)__raw_readl(r
);
419 static inline void ag71xx_cb(struct ag71xx
*ag
, unsigned reg
, u32 mask
)
423 ag71xx_check_reg_offset(ag
, reg
);
425 r
= ag
->mac_base
+ reg
;
426 __raw_writel(__raw_readl(r
) & ~mask
, r
);
428 (void) __raw_readl(r
);
431 static inline void ag71xx_int_enable(struct ag71xx
*ag
, u32 ints
)
433 ag71xx_sb(ag
, AG71XX_REG_INT_ENABLE
, ints
);
436 static inline void ag71xx_int_disable(struct ag71xx
*ag
, u32 ints
)
438 ag71xx_cb(ag
, AG71XX_REG_INT_ENABLE
, ints
);
441 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
442 void ag71xx_add_ar8216_header(struct ag71xx
*ag
, struct sk_buff
*skb
);
443 int ag71xx_remove_ar8216_header(struct ag71xx
*ag
, struct sk_buff
*skb
,
445 static inline int ag71xx_has_ar8216(struct ag71xx
*ag
)
447 return ag71xx_get_pdata(ag
)->has_ar8216
;
450 static inline void ag71xx_add_ar8216_header(struct ag71xx
*ag
,
455 static inline int ag71xx_remove_ar8216_header(struct ag71xx
*ag
,
461 static inline int ag71xx_has_ar8216(struct ag71xx
*ag
)
467 #ifdef CONFIG_AG71XX_DEBUG_FS
468 int ag71xx_debugfs_root_init(void);
469 void ag71xx_debugfs_root_exit(void);
470 int ag71xx_debugfs_init(struct ag71xx
*ag
);
471 void ag71xx_debugfs_exit(struct ag71xx
*ag
);
472 void ag71xx_debugfs_update_int_stats(struct ag71xx
*ag
, u32 status
);
473 void ag71xx_debugfs_update_napi_stats(struct ag71xx
*ag
, int rx
, int tx
);
475 static inline int ag71xx_debugfs_root_init(void) { return 0; }
476 static inline void ag71xx_debugfs_root_exit(void) {}
477 static inline int ag71xx_debugfs_init(struct ag71xx
*ag
) { return 0; }
478 static inline void ag71xx_debugfs_exit(struct ag71xx
*ag
) {}
479 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx
*ag
,
481 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx
*ag
,
483 #endif /* CONFIG_AG71XX_DEBUG_FS */
485 void ag71xx_ar7240_start(struct ag71xx
*ag
);
486 void ag71xx_ar7240_stop(struct ag71xx
*ag
);
487 int ag71xx_ar7240_init(struct ag71xx
*ag
);
488 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
);
490 int ag71xx_mdio_mii_read(struct ag71xx_mdio
*am
, int addr
, int reg
);
491 void ag71xx_mdio_mii_write(struct ag71xx_mdio
*am
, int addr
, int reg
, u16 val
);
493 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
495 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
496 unsigned reg_addr
, u16 reg_val
);
498 #endif /* _AG71XX_H */