2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
40 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
42 #define AR7240_REG_VTU 0x0040
43 #define AR7240_VTU_OP BITM(3)
44 #define AR7240_VTU_OP_NOOP 0x0
45 #define AR7240_VTU_OP_FLUSH 0x1
46 #define AR7240_VTU_OP_LOAD 0x2
47 #define AR7240_VTU_OP_PURGE 0x3
48 #define AR7240_VTU_OP_REMOVE_PORT 0x4
49 #define AR7240_VTU_ACTIVE BIT(3)
50 #define AR7240_VTU_FULL BIT(4)
51 #define AR7240_VTU_PORT BITS(8, 4)
52 #define AR7240_VTU_PORT_S 8
53 #define AR7240_VTU_VID BITS(16, 12)
54 #define AR7240_VTU_VID_S 16
55 #define AR7240_VTU_PRIO BITS(28, 3)
56 #define AR7240_VTU_PRIO_S 28
57 #define AR7240_VTU_PRIO_EN BIT(31)
59 #define AR7240_REG_VTU_DATA 0x0044
60 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
61 #define AR7240_VTUDATA_VALID BIT(11)
63 #define AR7240_REG_ATU 0x50
64 #define AR7240_ATU_FLUSH_ALL 0x1
66 #define AR7240_REG_AT_CTRL 0x5c
67 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
68 #define AR7240_AT_CTRL_AGE_EN BIT(17)
69 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
70 #define AR7240_AT_CTRL_RESERVED BIT(19)
71 #define AR7240_AT_CTRL_ARP_EN BIT(20)
73 #define AR7240_REG_TAG_PRIORITY 0x70
75 #define AR7240_REG_SERVICE_TAG 0x74
76 #define AR7240_SERVICE_TAG_M BITM(16)
78 #define AR7240_REG_CPU_PORT 0x78
79 #define AR7240_MIRROR_PORT_S 4
80 #define AR7240_MIRROR_PORT_M BITM(4)
81 #define AR7240_CPU_PORT_EN BIT(8)
83 #define AR7240_REG_MIB_FUNCTION0 0x80
84 #define AR7240_MIB_TIMER_M BITM(16)
85 #define AR7240_MIB_AT_HALF_EN BIT(16)
86 #define AR7240_MIB_BUSY BIT(17)
87 #define AR7240_MIB_FUNC_S 24
88 #define AR7240_MIB_FUNC_M BITM(3)
89 #define AR7240_MIB_FUNC_NO_OP 0x0
90 #define AR7240_MIB_FUNC_FLUSH 0x1
91 #define AR7240_MIB_FUNC_CAPTURE 0x3
93 #define AR7240_REG_MDIO_CTRL 0x98
94 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
95 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
96 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
97 #define AR7240_MDIO_CTRL_CMD_WRITE 0
98 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
99 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
100 #define AR7240_MDIO_CTRL_BUSY BIT(31)
102 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
104 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
105 #define AR7240_PORT_STATUS_SPEED_S 0
106 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
107 #define AR7240_PORT_STATUS_SPEED_10 0
108 #define AR7240_PORT_STATUS_SPEED_100 1
109 #define AR7240_PORT_STATUS_SPEED_1000 2
110 #define AR7240_PORT_STATUS_TXMAC BIT(2)
111 #define AR7240_PORT_STATUS_RXMAC BIT(3)
112 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
113 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
114 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
115 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
116 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
117 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
119 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
120 #define AR7240_PORT_CTRL_STATE_M BITM(3)
121 #define AR7240_PORT_CTRL_STATE_DISABLED 0
122 #define AR7240_PORT_CTRL_STATE_BLOCK 1
123 #define AR7240_PORT_CTRL_STATE_LISTEN 2
124 #define AR7240_PORT_CTRL_STATE_LEARN 3
125 #define AR7240_PORT_CTRL_STATE_FORWARD 4
126 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
127 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
128 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
129 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
130 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
131 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
132 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
133 #define AR7240_PORT_CTRL_HEADER BIT(11)
134 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
135 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
136 #define AR7240_PORT_CTRL_LEARN BIT(14)
137 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
138 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
139 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
141 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
143 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
144 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
145 #define AR7240_PORT_VLAN_MODE_S 30
146 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
147 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
148 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
149 #define AR7240_PORT_VLAN_MODE_SECURE 3
152 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
154 #define AR7240_STATS_RXBROAD 0x00
155 #define AR7240_STATS_RXPAUSE 0x04
156 #define AR7240_STATS_RXMULTI 0x08
157 #define AR7240_STATS_RXFCSERR 0x0c
158 #define AR7240_STATS_RXALIGNERR 0x10
159 #define AR7240_STATS_RXRUNT 0x14
160 #define AR7240_STATS_RXFRAGMENT 0x18
161 #define AR7240_STATS_RX64BYTE 0x1c
162 #define AR7240_STATS_RX128BYTE 0x20
163 #define AR7240_STATS_RX256BYTE 0x24
164 #define AR7240_STATS_RX512BYTE 0x28
165 #define AR7240_STATS_RX1024BYTE 0x2c
166 #define AR7240_STATS_RX1518BYTE 0x30
167 #define AR7240_STATS_RXMAXBYTE 0x34
168 #define AR7240_STATS_RXTOOLONG 0x38
169 #define AR7240_STATS_RXGOODBYTE 0x3c
170 #define AR7240_STATS_RXBADBYTE 0x44
171 #define AR7240_STATS_RXOVERFLOW 0x4c
172 #define AR7240_STATS_FILTERED 0x50
173 #define AR7240_STATS_TXBROAD 0x54
174 #define AR7240_STATS_TXPAUSE 0x58
175 #define AR7240_STATS_TXMULTI 0x5c
176 #define AR7240_STATS_TXUNDERRUN 0x60
177 #define AR7240_STATS_TX64BYTE 0x64
178 #define AR7240_STATS_TX128BYTE 0x68
179 #define AR7240_STATS_TX256BYTE 0x6c
180 #define AR7240_STATS_TX512BYTE 0x70
181 #define AR7240_STATS_TX1024BYTE 0x74
182 #define AR7240_STATS_TX1518BYTE 0x78
183 #define AR7240_STATS_TXMAXBYTE 0x7c
184 #define AR7240_STATS_TXOVERSIZE 0x80
185 #define AR7240_STATS_TXBYTE 0x84
186 #define AR7240_STATS_TXCOLLISION 0x8c
187 #define AR7240_STATS_TXABORTCOL 0x90
188 #define AR7240_STATS_TXMULTICOL 0x94
189 #define AR7240_STATS_TXSINGLECOL 0x98
190 #define AR7240_STATS_TXEXCDEFER 0x9c
191 #define AR7240_STATS_TXDEFER 0xa0
192 #define AR7240_STATS_TXLATECOL 0xa4
194 #define AR7240_PORT_CPU 0
195 #define AR7240_NUM_PORTS 6
196 #define AR7240_NUM_PHYS 5
198 #define AR7240_PHY_ID1 0x004d
199 #define AR7240_PHY_ID2 0xd041
201 #define AR934X_PHY_ID1 0x004d
202 #define AR934X_PHY_ID2 0xd042
204 #define AR7240_MAX_VLANS 16
206 #define AR934X_REG_OPER_MODE0 0x04
207 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
208 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
210 #define AR934X_REG_OPER_MODE1 0x08
211 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
213 #define AR934X_REG_FLOOD_MASK 0x2c
214 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
215 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
217 #define AR934X_REG_QM_CTRL 0x3c
218 #define AR934X_QM_CTRL_ARP_EN BIT(15)
220 #define AR934X_REG_AT_CTRL 0x5c
221 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
222 #define AR934X_AT_CTRL_AGE_EN BIT(17)
223 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
225 #define AR934X_MIB_ENABLE BIT(30)
227 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
229 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
230 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
231 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
232 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
233 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
234 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
235 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
236 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
237 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
239 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
240 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
241 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
242 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
243 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
244 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
245 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
247 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
249 struct ar7240sw_port_stat
{
250 unsigned long rx_broadcast
;
251 unsigned long rx_pause
;
252 unsigned long rx_multicast
;
253 unsigned long rx_fcs_error
;
254 unsigned long rx_align_error
;
255 unsigned long rx_runt
;
256 unsigned long rx_fragments
;
257 unsigned long rx_64byte
;
258 unsigned long rx_128byte
;
259 unsigned long rx_256byte
;
260 unsigned long rx_512byte
;
261 unsigned long rx_1024byte
;
262 unsigned long rx_1518byte
;
263 unsigned long rx_maxbyte
;
264 unsigned long rx_toolong
;
265 unsigned long rx_good_byte
;
266 unsigned long rx_bad_byte
;
267 unsigned long rx_overflow
;
268 unsigned long filtered
;
270 unsigned long tx_broadcast
;
271 unsigned long tx_pause
;
272 unsigned long tx_multicast
;
273 unsigned long tx_underrun
;
274 unsigned long tx_64byte
;
275 unsigned long tx_128byte
;
276 unsigned long tx_256byte
;
277 unsigned long tx_512byte
;
278 unsigned long tx_1024byte
;
279 unsigned long tx_1518byte
;
280 unsigned long tx_maxbyte
;
281 unsigned long tx_oversize
;
282 unsigned long tx_byte
;
283 unsigned long tx_collision
;
284 unsigned long tx_abortcol
;
285 unsigned long tx_multicol
;
286 unsigned long tx_singlecol
;
287 unsigned long tx_excdefer
;
288 unsigned long tx_defer
;
289 unsigned long tx_xlatecol
;
293 struct mii_bus
*mii_bus
;
294 struct ag71xx_switch_platform_data
*swdata
;
295 struct switch_dev swdev
;
299 u16 vlan_id
[AR7240_MAX_VLANS
];
300 u8 vlan_table
[AR7240_MAX_VLANS
];
302 u16 pvid
[AR7240_NUM_PORTS
];
306 struct ar7240sw_port_stat port_stats
[AR7240_NUM_PORTS
];
309 struct ar7240sw_hw_stat
{
310 char string
[ETH_GSTRING_LEN
];
315 static DEFINE_MUTEX(reg_mutex
);
317 static inline int sw_is_ar7240(struct ar7240sw
*as
)
319 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR7240
;
322 static inline int sw_is_ar934x(struct ar7240sw
*as
)
324 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR934X
;
327 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
332 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
334 return BIT(as
->swdev
.ports
) - 1;
337 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
339 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
342 static inline u16
mk_phy_addr(u32 reg
)
344 return 0x17 & ((reg
>> 4) | 0x10);
347 static inline u16
mk_phy_reg(u32 reg
)
349 return (reg
<< 1) & 0x1e;
352 static inline u16
mk_high_addr(u32 reg
)
354 return (reg
>> 7) & 0x1ff;
357 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
364 reg
= (reg
& 0xfffffffc) >> 2;
365 phy_addr
= mk_phy_addr(reg
);
366 phy_reg
= mk_phy_reg(reg
);
368 local_irq_save(flags
);
369 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
370 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
371 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
372 local_irq_restore(flags
);
374 return (hi
<< 16) | lo
;
377 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
383 reg
= (reg
& 0xfffffffc) >> 2;
384 phy_addr
= mk_phy_addr(reg
);
385 phy_reg
= mk_phy_reg(reg
);
387 local_irq_save(flags
);
388 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
389 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
390 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
391 local_irq_restore(flags
);
394 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
398 mutex_lock(®_mutex
);
399 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
400 mutex_unlock(®_mutex
);
405 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
407 mutex_lock(®_mutex
);
408 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
409 mutex_unlock(®_mutex
);
412 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
416 mutex_lock(®_mutex
);
417 t
= __ar7240sw_reg_read(mii
, reg
);
420 __ar7240sw_reg_write(mii
, reg
, t
);
421 mutex_unlock(®_mutex
);
426 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
430 mutex_lock(®_mutex
);
431 t
= __ar7240sw_reg_read(mii
, reg
);
433 __ar7240sw_reg_write(mii
, reg
, t
);
434 mutex_unlock(®_mutex
);
437 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
442 for (i
= 0; i
< timeout
; i
++) {
445 t
= __ar7240sw_reg_read(mii
, reg
);
446 if ((t
& mask
) == val
)
449 usleep_range(1000, 2000);
455 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
460 mutex_lock(®_mutex
);
461 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
462 mutex_unlock(®_mutex
);
466 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
472 if (phy_addr
>= AR7240_NUM_PHYS
)
475 mutex_lock(®_mutex
);
476 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
477 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
478 AR7240_MDIO_CTRL_MASTER_EN
|
479 AR7240_MDIO_CTRL_BUSY
|
480 AR7240_MDIO_CTRL_CMD_READ
;
482 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
483 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
484 AR7240_MDIO_CTRL_BUSY
, 0, 5);
486 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
487 mutex_unlock(®_mutex
);
489 return val
& AR7240_MDIO_CTRL_DATA_M
;
492 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
493 unsigned reg_addr
, u16 reg_val
)
498 if (phy_addr
>= AR7240_NUM_PHYS
)
501 mutex_lock(®_mutex
);
502 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
503 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
504 AR7240_MDIO_CTRL_MASTER_EN
|
505 AR7240_MDIO_CTRL_BUSY
|
506 AR7240_MDIO_CTRL_CMD_WRITE
|
509 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
510 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
511 AR7240_MDIO_CTRL_BUSY
, 0, 5);
512 mutex_unlock(®_mutex
);
517 static int ar7240sw_capture_stats(struct ar7240sw
*as
)
519 struct mii_bus
*mii
= as
->mii_bus
;
523 write_lock(&as
->stats_lock
);
525 /* Capture the hardware statistics for all ports */
526 ar7240sw_reg_rmw(mii
, AR7240_REG_MIB_FUNCTION0
,
527 (AR7240_MIB_FUNC_M
<< AR7240_MIB_FUNC_S
),
528 (AR7240_MIB_FUNC_CAPTURE
<< AR7240_MIB_FUNC_S
));
530 /* Wait for the capturing to complete. */
531 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MIB_FUNCTION0
,
532 AR7240_MIB_BUSY
, 0, 10);
537 for (port
= 0; port
< AR7240_NUM_PORTS
; port
++) {
539 struct ar7240sw_port_stat
*stats
;
541 base
= AR7240_REG_STATS_BASE(port
);
542 stats
= &as
->port_stats
[port
];
544 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
546 stats
->rx_good_byte
+= READ_STAT(RXGOODBYTE
);
547 stats
->tx_byte
+= READ_STAT(TXBYTE
);
555 write_unlock(&as
->stats_lock
);
559 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
561 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
562 AR7240_PORT_CTRL_STATE_DISABLED
);
565 static void ar7240sw_setup(struct ar7240sw
*as
)
567 struct mii_bus
*mii
= as
->mii_bus
;
569 /* Enable CPU port, and disable mirror port */
570 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
572 (15 << AR7240_MIRROR_PORT_S
));
574 /* Setup TAG priority mapping */
575 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
577 if (sw_is_ar934x(as
)) {
578 /* Enable aging, MAC replacing */
579 ar7240sw_reg_write(mii
, AR934X_REG_AT_CTRL
,
580 0x2b /* 5 min age time */ |
581 AR934X_AT_CTRL_AGE_EN
|
582 AR934X_AT_CTRL_LEARN_CHANGE
);
583 /* Enable ARP frame acknowledge */
584 ar7240sw_reg_set(mii
, AR934X_REG_QM_CTRL
,
585 AR934X_QM_CTRL_ARP_EN
);
586 /* Enable Broadcast/Multicast frames transmitted to the CPU */
587 ar7240sw_reg_set(mii
, AR934X_REG_FLOOD_MASK
,
588 AR934X_FLOOD_MASK_BC_DP(0) |
589 AR934X_FLOOD_MASK_MC_DP(0));
592 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
,
593 AR9340_GLOBAL_CTRL_MTU_M
,
594 AR9340_GLOBAL_CTRL_MTU_M
);
596 /* Enable MIB counters */
597 ar7240sw_reg_set(mii
, AR7240_REG_MIB_FUNCTION0
,
601 /* Enable ARP frame acknowledge, aging, MAC replacing */
602 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
603 AR7240_AT_CTRL_RESERVED
|
604 0x2b /* 5 min age time */ |
605 AR7240_AT_CTRL_AGE_EN
|
606 AR7240_AT_CTRL_ARP_EN
|
607 AR7240_AT_CTRL_LEARN_CHANGE
);
608 /* Enable Broadcast frames transmitted to the CPU */
609 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
610 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
613 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
,
614 AR7240_GLOBAL_CTRL_MTU_M
,
615 AR7240_GLOBAL_CTRL_MTU_M
);
618 /* setup Service TAG */
619 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
622 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
624 ar7240sw_phy_poll_reset(struct mii_bus
*bus
)
626 const unsigned int sleep_msecs
= 20;
629 for (elapsed
= sleep_msecs
; elapsed
<= 600;
630 elapsed
+= sleep_msecs
) {
632 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
633 ret
= ar7240sw_phy_read(bus
, i
, MII_BMCR
);
636 if (ret
& BMCR_RESET
)
638 if (i
== AR7240_NUM_PHYS
- 1) {
639 usleep_range(1000, 2000);
647 static int ar7240sw_reset(struct ar7240sw
*as
)
649 struct mii_bus
*mii
= as
->mii_bus
;
653 /* Set all ports to disabled state. */
654 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
655 ar7240sw_disable_port(as
, i
);
657 /* Wait for transmit queues to drain. */
658 usleep_range(2000, 3000);
660 /* Reset the switch. */
661 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
662 AR7240_MASK_CTRL_SOFT_RESET
);
664 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
665 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
668 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
669 ar7240sw_phy_write(mii
, i
, MII_ADVERTISE
,
670 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
671 ADVERTISE_PAUSE_ASYM
);
672 ar7240sw_phy_write(mii
, i
, MII_BMCR
,
673 BMCR_RESET
| BMCR_ANENABLE
);
675 ret
= ar7240sw_phy_poll_reset(mii
);
683 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
685 struct mii_bus
*mii
= as
->mii_bus
;
689 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
690 AR7240_PORT_CTRL_SINGLE_VLAN
;
692 if (port
== AR7240_PORT_CPU
) {
693 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
694 AR7240_PORT_STATUS_SPEED_1000
|
695 AR7240_PORT_STATUS_TXFLOW
|
696 AR7240_PORT_STATUS_RXFLOW
|
697 AR7240_PORT_STATUS_TXMAC
|
698 AR7240_PORT_STATUS_RXMAC
|
699 AR7240_PORT_STATUS_DUPLEX
);
701 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
702 AR7240_PORT_STATUS_LINK_AUTO
);
705 /* Set the default VID for this port */
707 vid
= as
->vlan_id
[as
->pvid
[port
]];
708 mode
= AR7240_PORT_VLAN_MODE_SECURE
;
711 mode
= AR7240_PORT_VLAN_MODE_PORT_ONLY
;
715 if (as
->vlan_tagged
& BIT(port
))
716 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
717 AR7240_PORT_CTRL_VLAN_MODE_S
;
719 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
720 AR7240_PORT_CTRL_VLAN_MODE_S
;
722 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_KEEP
<<
723 AR7240_PORT_CTRL_VLAN_MODE_S
;
727 if (port
== AR7240_PORT_CPU
)
728 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
730 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
733 /* allow the port to talk to all other ports, but exclude its
734 * own ID to prevent frames from being reflected back to the
735 * port that they came from */
736 portmask
&= ar7240sw_port_mask_but(as
, port
);
738 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
739 if (sw_is_ar934x(as
)) {
742 vlan1
= (vid
<< AR934X_PORT_VLAN1_DEFAULT_CVID_S
);
743 vlan2
= (portmask
<< AR934X_PORT_VLAN2_PORT_VID_MEM_S
) |
744 (mode
<< AR934X_PORT_VLAN2_8021Q_MODE_S
);
745 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN1(port
), vlan1
);
746 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN2(port
), vlan2
);
750 vlan
= vid
| (mode
<< AR7240_PORT_VLAN_MODE_S
) |
751 (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
753 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
757 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
759 struct mii_bus
*mii
= as
->mii_bus
;
762 t
= (addr
[4] << 8) | addr
[5];
763 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
765 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
766 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
772 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
773 struct switch_val
*val
)
775 struct ar7240sw
*as
= sw_to_ar7240(dev
);
776 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
781 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
782 struct switch_val
*val
)
784 struct ar7240sw
*as
= sw_to_ar7240(dev
);
785 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
790 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
792 struct ar7240sw
*as
= sw_to_ar7240(dev
);
794 /* make sure no invalid PVIDs get set */
796 if (vlan
>= dev
->vlans
)
799 as
->pvid
[port
] = vlan
;
804 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
806 struct ar7240sw
*as
= sw_to_ar7240(dev
);
807 *vlan
= as
->pvid
[port
];
812 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
814 struct ar7240sw
*as
= sw_to_ar7240(dev
);
815 u8 ports
= as
->vlan_table
[val
->port_vlan
];
819 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
820 struct switch_port
*p
;
822 if (!(ports
& (1 << i
)))
825 p
= &val
->value
.ports
[val
->len
++];
827 if (as
->vlan_tagged
& (1 << i
))
828 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
836 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
838 struct ar7240sw
*as
= sw_to_ar7240(dev
);
839 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
843 for (i
= 0; i
< val
->len
; i
++) {
844 struct switch_port
*p
= &val
->value
.ports
[i
];
846 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
847 as
->vlan_tagged
|= (1 << p
->id
);
849 as
->vlan_tagged
&= ~(1 << p
->id
);
850 as
->pvid
[p
->id
] = val
->port_vlan
;
852 /* make sure that an untagged port does not
853 * appear in other vlans */
854 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
855 if (j
== val
->port_vlan
)
857 as
->vlan_table
[j
] &= ~(1 << p
->id
);
867 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
868 struct switch_val
*val
)
870 struct ar7240sw
*as
= sw_to_ar7240(dev
);
871 as
->vlan
= !!val
->value
.i
;
876 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
877 struct switch_val
*val
)
879 struct ar7240sw
*as
= sw_to_ar7240(dev
);
880 val
->value
.i
= as
->vlan
;
885 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
887 struct mii_bus
*mii
= as
->mii_bus
;
889 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
892 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
893 val
&= AR7240_VTUDATA_MEMBER
;
894 val
|= AR7240_VTUDATA_VALID
;
895 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
897 op
|= AR7240_VTU_ACTIVE
;
898 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
902 ar7240_hw_apply(struct switch_dev
*dev
)
904 struct ar7240sw
*as
= sw_to_ar7240(dev
);
905 u8 portmask
[AR7240_NUM_PORTS
];
908 /* flush all vlan translation unit entries */
909 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
911 memset(portmask
, 0, sizeof(portmask
));
913 /* calculate the port destination masks and load vlans
914 * into the vlan translation unit */
915 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
916 u8 vp
= as
->vlan_table
[j
];
921 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
924 portmask
[i
] |= vp
& ~mask
;
929 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
934 * isolate all ports, but connect them to the cpu port */
935 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
936 if (i
== AR7240_PORT_CPU
)
939 portmask
[i
] = 1 << AR7240_PORT_CPU
;
940 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
944 /* update the port destination mask registers and tag settings */
945 for (i
= 0; i
< as
->swdev
.ports
; i
++)
946 ar7240sw_setup_port(as
, i
, portmask
[i
]);
952 ar7240_reset_switch(struct switch_dev
*dev
)
954 struct ar7240sw
*as
= sw_to_ar7240(dev
);
960 ar7240_get_port_link(struct switch_dev
*dev
, int port
,
961 struct switch_port_link
*link
)
963 struct ar7240sw
*as
= sw_to_ar7240(dev
);
964 struct mii_bus
*mii
= as
->mii_bus
;
967 if (port
>= AR7240_NUM_PORTS
)
970 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
971 link
->aneg
= !!(status
& AR7240_PORT_STATUS_LINK_AUTO
);
973 link
->link
= !!(status
& AR7240_PORT_STATUS_LINK_UP
);
980 link
->duplex
= !!(status
& AR7240_PORT_STATUS_DUPLEX
);
981 link
->tx_flow
= !!(status
& AR7240_PORT_STATUS_TXFLOW
);
982 link
->rx_flow
= !!(status
& AR7240_PORT_STATUS_RXFLOW
);
983 switch (status
& AR7240_PORT_STATUS_SPEED_M
) {
984 case AR7240_PORT_STATUS_SPEED_10
:
985 link
->speed
= SWITCH_PORT_SPEED_10
;
987 case AR7240_PORT_STATUS_SPEED_100
:
988 link
->speed
= SWITCH_PORT_SPEED_100
;
990 case AR7240_PORT_STATUS_SPEED_1000
:
991 link
->speed
= SWITCH_PORT_SPEED_1000
;
999 ar7240_get_port_stats(struct switch_dev
*dev
, int port
,
1000 struct switch_port_stats
*stats
)
1002 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1004 if (port
>= AR7240_NUM_PORTS
)
1007 ar7240sw_capture_stats(as
);
1009 read_lock(&as
->stats_lock
);
1010 stats
->rx_bytes
= as
->port_stats
[port
].rx_good_byte
;
1011 stats
->tx_bytes
= as
->port_stats
[port
].tx_byte
;
1012 read_unlock(&as
->stats_lock
);
1018 ar7240_set_mirror_monitor_port(struct switch_dev
*dev
,
1019 const struct switch_attr
*attr
,
1020 struct switch_val
*val
)
1022 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1023 struct mii_bus
*mii
= as
->mii_bus
;
1025 int port
= val
->value
.i
;
1030 ar7240sw_reg_rmw(mii
, AR7240_REG_CPU_PORT
,
1031 AR7240_MIRROR_PORT_M
<< AR7240_MIRROR_PORT_S
,
1032 port
<< AR7240_MIRROR_PORT_S
);
1038 ar7240_get_mirror_monitor_port(struct switch_dev
*dev
,
1039 const struct switch_attr
*attr
,
1040 struct switch_val
*val
)
1042 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1043 struct mii_bus
*mii
= as
->mii_bus
;
1047 ret
= ar7240sw_reg_read(mii
, AR7240_REG_CPU_PORT
);
1048 val
->value
.i
= (ret
>> AR7240_MIRROR_PORT_S
) & AR7240_MIRROR_PORT_M
;
1054 ar7240_set_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1055 struct switch_val
*val
)
1057 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1058 struct mii_bus
*mii
= as
->mii_bus
;
1060 int port
= val
->port_vlan
;
1062 if (port
>= dev
->ports
)
1065 if (val
&& val
->value
.i
== 1)
1066 ar7240sw_reg_set(mii
, AR7240_REG_PORT_CTRL(port
),
1067 AR7240_PORT_CTRL_MIRROR_RX
);
1069 ar7240sw_reg_rmw(mii
, AR7240_REG_PORT_CTRL(port
),
1070 AR7240_PORT_CTRL_MIRROR_RX
, 0);
1076 ar7240_get_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1077 struct switch_val
*val
)
1079 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1080 struct mii_bus
*mii
= as
->mii_bus
;
1084 int port
= val
->port_vlan
;
1086 if (port
>= dev
->ports
)
1089 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_CTRL(port
));
1091 if ((ctrl
& AR7240_PORT_CTRL_MIRROR_RX
) == AR7240_PORT_CTRL_MIRROR_RX
)
1100 ar7240_set_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1101 struct switch_val
*val
)
1103 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1104 struct mii_bus
*mii
= as
->mii_bus
;
1106 int port
= val
->port_vlan
;
1108 if (port
>= dev
->ports
)
1111 if (val
&& val
->value
.i
== 1)
1112 ar7240sw_reg_set(mii
, AR7240_REG_PORT_CTRL(port
),
1113 AR7240_PORT_CTRL_MIRROR_TX
);
1115 ar7240sw_reg_rmw(mii
, AR7240_REG_PORT_CTRL(port
),
1116 AR7240_PORT_CTRL_MIRROR_TX
, 0);
1122 ar7240_get_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1123 struct switch_val
*val
)
1125 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1126 struct mii_bus
*mii
= as
->mii_bus
;
1130 int port
= val
->port_vlan
;
1132 if (port
>= dev
->ports
)
1135 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_CTRL(port
));
1137 if ((ctrl
& AR7240_PORT_CTRL_MIRROR_TX
) == AR7240_PORT_CTRL_MIRROR_TX
)
1145 static struct switch_attr ar7240_globals
[] = {
1147 .type
= SWITCH_TYPE_INT
,
1148 .name
= "enable_vlan",
1149 .description
= "Enable VLAN mode",
1150 .set
= ar7240_set_vlan
,
1151 .get
= ar7240_get_vlan
,
1155 .type
= SWITCH_TYPE_INT
,
1156 .name
= "mirror_monitor_port",
1157 .description
= "Mirror monitor port",
1158 .set
= ar7240_set_mirror_monitor_port
,
1159 .get
= ar7240_get_mirror_monitor_port
,
1164 static struct switch_attr ar7240_port
[] = {
1166 .type
= SWITCH_TYPE_INT
,
1167 .name
= "enable_mirror_rx",
1168 .description
= "Enable mirroring of RX packets",
1169 .set
= ar7240_set_mirror_rx
,
1170 .get
= ar7240_get_mirror_rx
,
1174 .type
= SWITCH_TYPE_INT
,
1175 .name
= "enable_mirror_tx",
1176 .description
= "Enable mirroring of TX packets",
1177 .set
= ar7240_set_mirror_tx
,
1178 .get
= ar7240_get_mirror_tx
,
1183 static struct switch_attr ar7240_vlan
[] = {
1185 .type
= SWITCH_TYPE_INT
,
1187 .description
= "VLAN ID",
1188 .set
= ar7240_set_vid
,
1189 .get
= ar7240_get_vid
,
1194 static const struct switch_dev_ops ar7240_ops
= {
1196 .attr
= ar7240_globals
,
1197 .n_attr
= ARRAY_SIZE(ar7240_globals
),
1200 .attr
= ar7240_port
,
1201 .n_attr
= ARRAY_SIZE(ar7240_port
),
1204 .attr
= ar7240_vlan
,
1205 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
1207 .get_port_pvid
= ar7240_get_pvid
,
1208 .set_port_pvid
= ar7240_set_pvid
,
1209 .get_vlan_ports
= ar7240_get_ports
,
1210 .set_vlan_ports
= ar7240_set_ports
,
1211 .apply_config
= ar7240_hw_apply
,
1212 .reset_switch
= ar7240_reset_switch
,
1213 .get_port_link
= ar7240_get_port_link
,
1214 .get_port_stats
= ar7240_get_port_stats
,
1217 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
1219 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
1220 struct mii_bus
*mii
= ag
->mii_bus
;
1221 struct ar7240sw
*as
;
1222 struct switch_dev
*swdev
;
1228 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
1229 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
1230 if ((phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) &&
1231 (phy_id1
!= AR934X_PHY_ID1
|| phy_id2
!= AR934X_PHY_ID2
)) {
1232 pr_err("%s: unknown phy id '%04x:%04x'\n",
1233 dev_name(&mii
->dev
), phy_id1
, phy_id2
);
1237 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
1242 as
->swdata
= pdata
->switch_data
;
1246 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
1247 as
->ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) &
1248 AR7240_MASK_CTRL_VERSION_M
;
1250 if (sw_is_ar7240(as
)) {
1251 swdev
->name
= "AR7240/AR9330 built-in switch";
1252 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1253 } else if (sw_is_ar934x(as
)) {
1254 swdev
->name
= "AR934X built-in switch";
1256 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
1257 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1258 AR934X_OPER_MODE0_MAC_GMII_EN
);
1259 } else if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
1260 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1261 AR934X_OPER_MODE0_PHY_MII_EN
);
1263 pr_err("%s: invalid PHY interface mode\n",
1264 dev_name(&mii
->dev
));
1268 if (as
->swdata
->phy4_mii_en
) {
1269 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE1
,
1270 AR934X_REG_OPER_MODE1_PHY4_MII_EN
);
1271 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1273 swdev
->ports
= AR7240_NUM_PORTS
;
1276 pr_err("%s: unsupported chip, ctrl=%08x\n",
1277 dev_name(&mii
->dev
), ctrl
);
1281 swdev
->cpu_port
= AR7240_PORT_CPU
;
1282 swdev
->vlans
= AR7240_MAX_VLANS
;
1283 swdev
->ops
= &ar7240_ops
;
1285 if (register_switch(&as
->swdev
, ag
->dev
) < 0)
1288 pr_info("%s: Found an %s\n", dev_name(&mii
->dev
), swdev
->name
);
1290 /* initialize defaults */
1291 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
1294 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
1303 static void link_function(struct work_struct
*work
) {
1304 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
1305 struct ar7240sw
*as
= ag
->phy_priv
;
1306 unsigned long flags
;
1311 mask
= ~as
->swdata
->phy_poll_mask
;
1312 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
1315 if (!(mask
& BIT(i
)))
1318 link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
1319 if (link
& BMSR_LSTATUS
) {
1325 spin_lock_irqsave(&ag
->lock
, flags
);
1326 if (status
!= ag
->link
) {
1328 ag71xx_link_adjust(ag
);
1330 spin_unlock_irqrestore(&ag
->lock
, flags
);
1332 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
1335 void ag71xx_ar7240_start(struct ag71xx
*ag
)
1337 struct ar7240sw
*as
= ag
->phy_priv
;
1341 ag
->speed
= SPEED_1000
;
1344 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
1345 ar7240_hw_apply(&as
->swdev
);
1347 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
1350 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
1352 cancel_delayed_work_sync(&ag
->link_work
);
1355 int ag71xx_ar7240_init(struct ag71xx
*ag
)
1357 struct ar7240sw
*as
;
1359 as
= ar7240_probe(ag
);
1366 rwlock_init(&as
->stats_lock
);
1367 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
1372 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
1374 struct ar7240sw
*as
= ag
->phy_priv
;
1379 unregister_switch(&as
->swdev
);
1381 ag
->phy_priv
= NULL
;