2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level
= -1;
28 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
29 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
36 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
37 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
42 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
43 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
46 static void ag71xx_dump_regs(struct ag71xx
*ag
)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
51 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
52 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
53 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
54 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
58 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
59 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
63 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
68 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
69 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
72 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag
->dev
->name
, label
, intr
,
76 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
77 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
78 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
79 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
80 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
81 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
89 dma_free_coherent(NULL
, ring
->size
* ring
->desc_size
,
90 ring
->descs_cpu
, ring
->descs_dma
);
93 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
)
98 ring
->desc_size
= sizeof(struct ag71xx_desc
);
99 if (ring
->desc_size
% cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring
, ring
->desc_size
,
102 roundup(ring
->desc_size
, cache_line_size()));
103 ring
->desc_size
= roundup(ring
->desc_size
, cache_line_size());
106 ring
->descs_cpu
= dma_alloc_coherent(NULL
, ring
->size
* ring
->desc_size
,
107 &ring
->descs_dma
, GFP_ATOMIC
);
108 if (!ring
->descs_cpu
) {
114 ring
->buf
= kzalloc(ring
->size
* sizeof(*ring
->buf
), GFP_KERNEL
);
120 for (i
= 0; i
< ring
->size
; i
++) {
121 int idx
= i
* ring
->desc_size
;
122 ring
->buf
[i
].desc
= (struct ag71xx_desc
*)&ring
->descs_cpu
[idx
];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring
, i
, ring
->buf
[i
].desc
);
133 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
135 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
136 struct net_device
*dev
= ag
->dev
;
137 u32 bytes_compl
= 0, pkts_compl
= 0;
139 while (ring
->curr
!= ring
->dirty
) {
140 u32 i
= ring
->dirty
% ring
->size
;
142 if (!ag71xx_desc_empty(ring
->buf
[i
].desc
)) {
143 ring
->buf
[i
].desc
->ctrl
= 0;
144 dev
->stats
.tx_errors
++;
147 if (ring
->buf
[i
].skb
) {
148 bytes_compl
+= ring
->buf
[i
].skb
->len
;
150 dev_kfree_skb_any(ring
->buf
[i
].skb
);
152 ring
->buf
[i
].skb
= NULL
;
156 /* flush descriptors */
159 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
162 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
164 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
167 for (i
= 0; i
< ring
->size
; i
++) {
168 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
169 ring
->desc_size
* ((i
+ 1) % ring
->size
));
171 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
172 ring
->buf
[i
].skb
= NULL
;
175 /* flush descriptors */
180 netdev_reset_queue(ag
->dev
);
183 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
185 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
191 for (i
= 0; i
< ring
->size
; i
++)
192 if (ring
->buf
[i
].rx_buf
) {
193 dma_unmap_single(&ag
->dev
->dev
, ring
->buf
[i
].dma_addr
,
194 AG71XX_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
195 kfree(ring
->buf
[i
].rx_buf
);
199 static int ag71xx_buffer_offset(struct ag71xx
*ag
)
201 int offset
= NET_SKB_PAD
;
204 * On AR71xx/AR91xx packets must be 4-byte aligned.
206 * When using builtin AR8216 support, hardware adds a 2-byte header,
207 * so we don't need any extra alignment in that case.
209 if (!ag71xx_get_pdata(ag
)->is_ar724x
|| ag71xx_has_ar8216(ag
))
212 return offset
+ NET_IP_ALIGN
;
215 static bool ag71xx_fill_rx_buf(struct ag71xx
*ag
, struct ag71xx_buf
*buf
,
220 data
= kmalloc(AG71XX_RX_BUF_SIZE
+
221 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
)),
227 buf
->dma_addr
= dma_map_single(&ag
->dev
->dev
, data
,
228 AG71XX_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
229 buf
->desc
->data
= (u32
) buf
->dma_addr
+ offset
;
233 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
235 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
238 int offset
= ag71xx_buffer_offset(ag
);
241 for (i
= 0; i
< ring
->size
; i
++) {
242 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
243 ring
->desc_size
* ((i
+ 1) % ring
->size
));
245 DBG("ag71xx: RX desc at %p, next is %08x\n",
247 ring
->buf
[i
].desc
->next
);
250 for (i
= 0; i
< ring
->size
; i
++) {
251 if (!ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
)) {
256 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
259 /* flush descriptors */
268 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
270 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
272 int offset
= ag71xx_buffer_offset(ag
);
275 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
278 i
= ring
->dirty
% ring
->size
;
280 if (!ring
->buf
[i
].rx_buf
&&
281 !ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
))
284 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
288 /* flush descriptors */
291 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
296 static int ag71xx_rings_init(struct ag71xx
*ag
)
300 ret
= ag71xx_ring_alloc(&ag
->tx_ring
);
304 ag71xx_ring_tx_init(ag
);
306 ret
= ag71xx_ring_alloc(&ag
->rx_ring
);
310 ret
= ag71xx_ring_rx_init(ag
);
314 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
316 ag71xx_ring_rx_clean(ag
);
317 ag71xx_ring_free(&ag
->rx_ring
);
319 ag71xx_ring_tx_clean(ag
);
320 netdev_reset_queue(ag
->dev
);
321 ag71xx_ring_free(&ag
->tx_ring
);
324 static unsigned char *ag71xx_speed_str(struct ag71xx
*ag
)
338 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
342 t
= (((u32
) mac
[5]) << 24) | (((u32
) mac
[4]) << 16)
343 | (((u32
) mac
[3]) << 8) | ((u32
) mac
[2]);
345 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
347 t
= (((u32
) mac
[1]) << 24) | (((u32
) mac
[0]) << 16);
348 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
351 static void ag71xx_dma_reset(struct ag71xx
*ag
)
356 ag71xx_dump_dma_regs(ag
);
359 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
360 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
363 * give the hardware some time to really stop all rx/tx activity
364 * clearing the descriptors too early causes random memory corruption
368 /* clear descriptor addresses */
369 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->stop_desc_dma
);
370 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->stop_desc_dma
);
372 /* clear pending RX/TX interrupts */
373 for (i
= 0; i
< 256; i
++) {
374 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
375 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
378 /* clear pending errors */
379 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
380 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
382 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
384 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
387 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
389 /* mask out reserved bits */
393 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
396 ag71xx_dump_dma_regs(ag
);
399 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
400 MAC_CFG1_SRX | MAC_CFG1_STX)
402 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
404 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
405 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
406 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
407 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
408 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
411 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
412 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
413 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
414 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
415 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
416 FIFO_CFG5_17 | FIFO_CFG5_SF)
418 static void ag71xx_hw_stop(struct ag71xx
*ag
)
420 /* disable all interrupts and stop the rx/tx engine */
421 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
422 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
423 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
426 static void ag71xx_hw_setup(struct ag71xx
*ag
)
428 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
430 /* setup MAC configuration registers */
431 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_INIT
);
433 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
434 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
436 /* setup max frame length */
437 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, AG71XX_TX_MTU_LEN
);
439 /* setup FIFO configuration registers */
440 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
441 if (pdata
->is_ar724x
) {
442 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, pdata
->fifo_cfg1
);
443 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, pdata
->fifo_cfg2
);
445 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
446 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
448 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
449 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
452 static void ag71xx_hw_init(struct ag71xx
*ag
)
454 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
455 u32 reset_mask
= pdata
->reset_bit
;
459 if (pdata
->is_ar724x
) {
460 u32 reset_phy
= reset_mask
;
462 reset_phy
&= AR71XX_RESET_GE0_PHY
| AR71XX_RESET_GE1_PHY
;
463 reset_mask
&= ~(AR71XX_RESET_GE0_PHY
| AR71XX_RESET_GE1_PHY
);
465 ath79_device_reset_set(reset_phy
);
467 ath79_device_reset_clear(reset_phy
);
471 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
474 ath79_device_reset_set(reset_mask
);
476 ath79_device_reset_clear(reset_mask
);
481 ag71xx_dma_reset(ag
);
484 static void ag71xx_fast_reset(struct ag71xx
*ag
)
486 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
487 struct net_device
*dev
= ag
->dev
;
488 u32 reset_mask
= pdata
->reset_bit
;
492 reset_mask
&= AR71XX_RESET_GE0_MAC
| AR71XX_RESET_GE1_MAC
;
494 mii_reg
= ag71xx_rr(ag
, AG71XX_REG_MII_CFG
);
495 rx_ds
= ag71xx_rr(ag
, AG71XX_REG_RX_DESC
);
496 tx_ds
= ag71xx_rr(ag
, AG71XX_REG_TX_DESC
);
498 ath79_device_reset_set(reset_mask
);
500 ath79_device_reset_clear(reset_mask
);
503 ag71xx_dma_reset(ag
);
506 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, rx_ds
);
507 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, tx_ds
);
508 ag71xx_wr(ag
, AG71XX_REG_MII_CFG
, mii_reg
);
510 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
513 static void ag71xx_hw_start(struct ag71xx
*ag
)
515 /* start RX engine */
516 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
518 /* enable interrupts */
519 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
522 void ag71xx_link_adjust(struct ag71xx
*ag
)
524 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
531 netif_carrier_off(ag
->dev
);
532 if (netif_msg_link(ag
))
533 pr_info("%s: link down\n", ag
->dev
->name
);
537 if (pdata
->is_ar724x
)
538 ag71xx_fast_reset(ag
);
540 cfg2
= ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
);
541 cfg2
&= ~(MAC_CFG2_IF_1000
| MAC_CFG2_IF_10_100
| MAC_CFG2_FDX
);
542 cfg2
|= (ag
->duplex
) ? MAC_CFG2_FDX
: 0;
544 ifctl
= ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
);
545 ifctl
&= ~(MAC_IFCTL_SPEED
);
547 fifo5
= ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
);
548 fifo5
&= ~FIFO_CFG5_BM
;
552 cfg2
|= MAC_CFG2_IF_1000
;
553 fifo5
|= FIFO_CFG5_BM
;
556 cfg2
|= MAC_CFG2_IF_10_100
;
557 ifctl
|= MAC_IFCTL_SPEED
;
560 cfg2
|= MAC_CFG2_IF_10_100
;
567 if (pdata
->is_ar91xx
)
568 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x00780fff);
569 else if (pdata
->is_ar724x
)
570 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, pdata
->fifo_cfg3
);
572 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x008001ff);
574 if (pdata
->set_speed
)
575 pdata
->set_speed(ag
->speed
);
577 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG2
, cfg2
);
578 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, fifo5
);
579 ag71xx_wr(ag
, AG71XX_REG_MAC_IFCTL
, ifctl
);
582 netif_carrier_on(ag
->dev
);
583 if (netif_msg_link(ag
))
584 pr_info("%s: link up (%sMbps/%s duplex)\n",
586 ag71xx_speed_str(ag
),
587 (DUPLEX_FULL
== ag
->duplex
) ? "Full" : "Half");
589 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
591 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
592 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
593 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
595 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
597 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
598 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
599 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
601 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
603 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
604 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
));
607 static int ag71xx_open(struct net_device
*dev
)
609 struct ag71xx
*ag
= netdev_priv(dev
);
612 ret
= ag71xx_rings_init(ag
);
616 napi_enable(&ag
->napi
);
618 netif_carrier_off(dev
);
619 ag71xx_phy_start(ag
);
621 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
622 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
624 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
626 netif_start_queue(dev
);
631 ag71xx_rings_cleanup(ag
);
635 static int ag71xx_stop(struct net_device
*dev
)
637 struct ag71xx
*ag
= netdev_priv(dev
);
640 netif_carrier_off(dev
);
643 spin_lock_irqsave(&ag
->lock
, flags
);
645 netif_stop_queue(dev
);
648 ag71xx_dma_reset(ag
);
650 napi_disable(&ag
->napi
);
651 del_timer_sync(&ag
->oom_timer
);
653 spin_unlock_irqrestore(&ag
->lock
, flags
);
655 ag71xx_rings_cleanup(ag
);
660 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
661 struct net_device
*dev
)
663 struct ag71xx
*ag
= netdev_priv(dev
);
664 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
665 struct ag71xx_desc
*desc
;
669 i
= ring
->curr
% ring
->size
;
670 desc
= ring
->buf
[i
].desc
;
672 if (!ag71xx_desc_empty(desc
))
675 if (ag71xx_has_ar8216(ag
))
676 ag71xx_add_ar8216_header(ag
, skb
);
679 DBG("%s: packet len is too small\n", ag
->dev
->name
);
683 dma_addr
= dma_map_single(&dev
->dev
, skb
->data
, skb
->len
,
686 netdev_sent_queue(dev
, skb
->len
);
687 ring
->buf
[i
].skb
= skb
;
688 ring
->buf
[i
].timestamp
= jiffies
;
690 /* setup descriptor fields */
691 desc
->data
= (u32
) dma_addr
;
692 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
694 /* flush descriptor */
698 if (ring
->curr
== (ring
->dirty
+ ring
->size
)) {
699 DBG("%s: tx queue full\n", ag
->dev
->name
);
700 netif_stop_queue(dev
);
703 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
705 /* enable TX engine */
706 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
711 dev
->stats
.tx_dropped
++;
717 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
719 struct ag71xx
*ag
= netdev_priv(dev
);
724 if (ag
->phy_dev
== NULL
)
727 spin_lock_irq(&ag
->lock
);
728 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
729 spin_unlock_irq(&ag
->lock
);
734 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
740 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
747 if (ag
->phy_dev
== NULL
)
750 return phy_mii_ioctl(ag
->phy_dev
, ifr
, cmd
);
759 static void ag71xx_oom_timer_handler(unsigned long data
)
761 struct net_device
*dev
= (struct net_device
*) data
;
762 struct ag71xx
*ag
= netdev_priv(dev
);
764 napi_schedule(&ag
->napi
);
767 static void ag71xx_tx_timeout(struct net_device
*dev
)
769 struct ag71xx
*ag
= netdev_priv(dev
);
771 if (netif_msg_tx_err(ag
))
772 pr_info("%s: tx timeout\n", ag
->dev
->name
);
774 schedule_work(&ag
->restart_work
);
777 static void ag71xx_restart_work_func(struct work_struct
*work
)
779 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
);
781 if (ag71xx_get_pdata(ag
)->is_ar724x
) {
783 ag71xx_link_adjust(ag
);
787 ag71xx_stop(ag
->dev
);
788 ag71xx_open(ag
->dev
);
791 static bool ag71xx_check_dma_stuck(struct ag71xx
*ag
, unsigned long timestamp
)
793 u32 rx_sm
, tx_sm
, rx_fd
;
795 if (likely(time_before(jiffies
, timestamp
+ HZ
/10)))
798 if (!netif_carrier_ok(ag
->dev
))
801 rx_sm
= ag71xx_rr(ag
, AG71XX_REG_RX_SM
);
802 if ((rx_sm
& 0x7) == 0x3 && ((rx_sm
>> 4) & 0x7) == 0x6)
805 tx_sm
= ag71xx_rr(ag
, AG71XX_REG_TX_SM
);
806 rx_fd
= ag71xx_rr(ag
, AG71XX_REG_FIFO_DEPTH
);
807 if (((tx_sm
>> 4) & 0x7) == 0 && ((rx_sm
& 0x7) == 0) &&
808 ((rx_sm
>> 4) & 0x7) == 0 && rx_fd
== 0)
814 static int ag71xx_tx_packets(struct ag71xx
*ag
)
816 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
817 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
821 DBG("%s: processing TX ring\n", ag
->dev
->name
);
823 while (ring
->dirty
!= ring
->curr
) {
824 unsigned int i
= ring
->dirty
% ring
->size
;
825 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
826 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
828 if (!ag71xx_desc_empty(desc
)) {
829 if (pdata
->is_ar7240
&&
830 ag71xx_check_dma_stuck(ag
, ring
->buf
[i
].timestamp
))
831 schedule_work(&ag
->restart_work
);
835 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
837 bytes_compl
+= skb
->len
;
838 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
839 ag
->dev
->stats
.tx_packets
++;
841 dev_kfree_skb_any(skb
);
842 ring
->buf
[i
].skb
= NULL
;
848 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
850 netdev_completed_queue(ag
->dev
, sent
, bytes_compl
);
851 if ((ring
->curr
- ring
->dirty
) < (ring
->size
* 3) / 4)
852 netif_wake_queue(ag
->dev
);
857 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
859 struct net_device
*dev
= ag
->dev
;
860 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
861 int offset
= ag71xx_buffer_offset(ag
);
864 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
865 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
867 while (done
< limit
) {
868 unsigned int i
= ring
->curr
% ring
->size
;
869 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
874 if (ag71xx_desc_empty(desc
))
877 if ((ring
->dirty
+ ring
->size
) == ring
->curr
) {
882 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
884 pktlen
= ag71xx_desc_pktlen(desc
);
885 pktlen
-= ETH_FCS_LEN
;
887 dma_unmap_single(&dev
->dev
, ring
->buf
[i
].dma_addr
,
888 AG71XX_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
890 dev
->last_rx
= jiffies
;
891 dev
->stats
.rx_packets
++;
892 dev
->stats
.rx_bytes
+= pktlen
;
894 skb
= build_skb(ring
->buf
[i
].rx_buf
, 0);
896 kfree(ring
->buf
[i
].rx_buf
);
900 skb_reserve(skb
, offset
);
901 skb_put(skb
, pktlen
);
903 if (ag71xx_has_ar8216(ag
))
904 err
= ag71xx_remove_ar8216_header(ag
, skb
, pktlen
);
907 dev
->stats
.rx_dropped
++;
911 skb
->ip_summed
= CHECKSUM_NONE
;
912 skb
->protocol
= eth_type_trans(skb
, dev
);
913 netif_receive_skb(skb
);
917 ring
->buf
[i
].rx_buf
= NULL
;
923 ag71xx_ring_rx_refill(ag
);
925 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
926 dev
->name
, ring
->curr
, ring
->dirty
, done
);
931 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
933 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
934 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
935 struct net_device
*dev
= ag
->dev
;
936 struct ag71xx_ring
*rx_ring
;
943 tx_done
= ag71xx_tx_packets(ag
);
945 DBG("%s: processing RX ring\n", dev
->name
);
946 rx_done
= ag71xx_rx_packets(ag
, limit
);
948 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
950 rx_ring
= &ag
->rx_ring
;
951 if (rx_ring
->buf
[rx_ring
->dirty
% rx_ring
->size
].rx_buf
== NULL
)
954 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
955 if (unlikely(status
& RX_STATUS_OF
)) {
956 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
957 dev
->stats
.rx_fifo_errors
++;
960 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
963 if (rx_done
< limit
) {
964 if (status
& RX_STATUS_PR
)
967 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
968 if (status
& TX_STATUS_PS
)
971 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
972 dev
->name
, rx_done
, tx_done
, limit
);
976 /* enable interrupts */
977 spin_lock_irqsave(&ag
->lock
, flags
);
978 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
979 spin_unlock_irqrestore(&ag
->lock
, flags
);
984 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
985 dev
->name
, rx_done
, tx_done
, limit
);
989 if (netif_msg_rx_err(ag
))
990 pr_info("%s: out of memory\n", dev
->name
);
992 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
997 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
999 struct net_device
*dev
= dev_id
;
1000 struct ag71xx
*ag
= netdev_priv(dev
);
1003 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
1004 ag71xx_dump_intr(ag
, "raw", status
);
1006 if (unlikely(!status
))
1009 if (unlikely(status
& AG71XX_INT_ERR
)) {
1010 if (status
& AG71XX_INT_TX_BE
) {
1011 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
1012 dev_err(&dev
->dev
, "TX BUS error\n");
1014 if (status
& AG71XX_INT_RX_BE
) {
1015 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
1016 dev_err(&dev
->dev
, "RX BUS error\n");
1020 if (likely(status
& AG71XX_INT_POLL
)) {
1021 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
1022 DBG("%s: enable polling mode\n", dev
->name
);
1023 napi_schedule(&ag
->napi
);
1026 ag71xx_debugfs_update_int_stats(ag
, status
);
1031 #ifdef CONFIG_NET_POLL_CONTROLLER
1033 * Polling 'interrupt' - used by things like netconsole to send skbs
1034 * without having to re-enable interrupts. It's not called while
1035 * the interrupt routine is executing.
1037 static void ag71xx_netpoll(struct net_device
*dev
)
1039 disable_irq(dev
->irq
);
1040 ag71xx_interrupt(dev
->irq
, dev
);
1041 enable_irq(dev
->irq
);
1045 static const struct net_device_ops ag71xx_netdev_ops
= {
1046 .ndo_open
= ag71xx_open
,
1047 .ndo_stop
= ag71xx_stop
,
1048 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
1049 .ndo_do_ioctl
= ag71xx_do_ioctl
,
1050 .ndo_tx_timeout
= ag71xx_tx_timeout
,
1051 .ndo_change_mtu
= eth_change_mtu
,
1052 .ndo_set_mac_address
= eth_mac_addr
,
1053 .ndo_validate_addr
= eth_validate_addr
,
1054 #ifdef CONFIG_NET_POLL_CONTROLLER
1055 .ndo_poll_controller
= ag71xx_netpoll
,
1059 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode
)
1062 case PHY_INTERFACE_MODE_MII
:
1064 case PHY_INTERFACE_MODE_GMII
:
1066 case PHY_INTERFACE_MODE_RMII
:
1068 case PHY_INTERFACE_MODE_RGMII
:
1070 case PHY_INTERFACE_MODE_SGMII
:
1080 static int ag71xx_probe(struct platform_device
*pdev
)
1082 struct net_device
*dev
;
1083 struct resource
*res
;
1085 struct ag71xx_platform_data
*pdata
;
1088 pdata
= pdev
->dev
.platform_data
;
1090 dev_err(&pdev
->dev
, "no platform data specified\n");
1095 if (pdata
->mii_bus_dev
== NULL
&& pdata
->phy_mask
) {
1096 dev_err(&pdev
->dev
, "no MII bus device specified\n");
1101 dev
= alloc_etherdev(sizeof(*ag
));
1103 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1108 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1110 ag
= netdev_priv(dev
);
1113 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
1114 AG71XX_DEFAULT_MSG_ENABLE
);
1115 spin_lock_init(&ag
->lock
);
1117 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
1119 dev_err(&pdev
->dev
, "no mac_base resource found\n");
1124 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
1125 if (!ag
->mac_base
) {
1126 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
1131 dev
->irq
= platform_get_irq(pdev
, 0);
1132 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
1136 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
1137 goto err_unmap_base
;
1140 dev
->base_addr
= (unsigned long)ag
->mac_base
;
1141 dev
->netdev_ops
= &ag71xx_netdev_ops
;
1142 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
1144 INIT_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
1146 init_timer(&ag
->oom_timer
);
1147 ag
->oom_timer
.data
= (unsigned long) dev
;
1148 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
1150 ag
->tx_ring
.size
= AG71XX_TX_RING_SIZE_DEFAULT
;
1151 ag
->rx_ring
.size
= AG71XX_RX_RING_SIZE_DEFAULT
;
1153 ag
->stop_desc
= dma_alloc_coherent(NULL
,
1154 sizeof(struct ag71xx_desc
), &ag
->stop_desc_dma
, GFP_KERNEL
);
1159 ag
->stop_desc
->data
= 0;
1160 ag
->stop_desc
->ctrl
= 0;
1161 ag
->stop_desc
->next
= (u32
) ag
->stop_desc_dma
;
1163 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
1165 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
1167 err
= register_netdev(dev
);
1169 dev_err(&pdev
->dev
, "unable to register net device\n");
1173 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1174 dev
->name
, dev
->base_addr
, dev
->irq
,
1175 ag71xx_get_phy_if_mode_name(pdata
->phy_if_mode
));
1177 ag71xx_dump_regs(ag
);
1181 ag71xx_dump_regs(ag
);
1183 err
= ag71xx_phy_connect(ag
);
1185 goto err_unregister_netdev
;
1187 err
= ag71xx_debugfs_init(ag
);
1189 goto err_phy_disconnect
;
1191 platform_set_drvdata(pdev
, dev
);
1196 ag71xx_phy_disconnect(ag
);
1197 err_unregister_netdev
:
1198 unregister_netdev(dev
);
1200 dma_free_coherent(NULL
, sizeof(struct ag71xx_desc
), ag
->stop_desc
,
1203 free_irq(dev
->irq
, dev
);
1205 iounmap(ag
->mac_base
);
1209 platform_set_drvdata(pdev
, NULL
);
1213 static int ag71xx_remove(struct platform_device
*pdev
)
1215 struct net_device
*dev
= platform_get_drvdata(pdev
);
1218 struct ag71xx
*ag
= netdev_priv(dev
);
1220 ag71xx_debugfs_exit(ag
);
1221 ag71xx_phy_disconnect(ag
);
1222 unregister_netdev(dev
);
1223 free_irq(dev
->irq
, dev
);
1224 iounmap(ag
->mac_base
);
1226 platform_set_drvdata(pdev
, NULL
);
1232 static struct platform_driver ag71xx_driver
= {
1233 .probe
= ag71xx_probe
,
1234 .remove
= ag71xx_remove
,
1236 .name
= AG71XX_DRV_NAME
,
1240 static int __init
ag71xx_module_init(void)
1244 ret
= ag71xx_debugfs_root_init();
1248 ret
= ag71xx_mdio_driver_init();
1250 goto err_debugfs_exit
;
1252 ret
= platform_driver_register(&ag71xx_driver
);
1259 ag71xx_mdio_driver_exit();
1261 ag71xx_debugfs_root_exit();
1266 static void __exit
ag71xx_module_exit(void)
1268 platform_driver_unregister(&ag71xx_driver
);
1269 ag71xx_mdio_driver_exit();
1270 ag71xx_debugfs_root_exit();
1273 module_init(ag71xx_module_init
);
1274 module_exit(ag71xx_module_exit
);
1276 MODULE_VERSION(AG71XX_DRV_VERSION
);
1277 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1278 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1279 MODULE_LICENSE("GPL v2");
1280 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);