2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level
= -1;
28 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
29 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
31 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu
)
33 return ETH_HLEN
+ VLAN_HLEN
+ mtu
+ ETH_FCS_LEN
;
36 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
38 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
40 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
41 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
42 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
44 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
46 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
47 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
48 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
51 static void ag71xx_dump_regs(struct ag71xx
*ag
)
53 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
55 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
56 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
57 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
58 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
59 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
60 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
62 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
63 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
64 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
65 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
67 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
68 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
69 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
70 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
72 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
73 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
74 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
77 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
79 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
80 ag
->dev
->name
, label
, intr
,
81 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
82 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
83 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
84 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
85 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
86 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
89 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
94 dma_free_coherent(NULL
, ring
->size
* ring
->desc_size
,
95 ring
->descs_cpu
, ring
->descs_dma
);
98 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
)
103 ring
->desc_size
= sizeof(struct ag71xx_desc
);
104 if (ring
->desc_size
% cache_line_size()) {
105 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
106 ring
, ring
->desc_size
,
107 roundup(ring
->desc_size
, cache_line_size()));
108 ring
->desc_size
= roundup(ring
->desc_size
, cache_line_size());
111 ring
->descs_cpu
= dma_alloc_coherent(NULL
, ring
->size
* ring
->desc_size
,
112 &ring
->descs_dma
, GFP_ATOMIC
);
113 if (!ring
->descs_cpu
) {
119 ring
->buf
= kzalloc(ring
->size
* sizeof(*ring
->buf
), GFP_KERNEL
);
125 for (i
= 0; i
< ring
->size
; i
++) {
126 int idx
= i
* ring
->desc_size
;
127 ring
->buf
[i
].desc
= (struct ag71xx_desc
*)&ring
->descs_cpu
[idx
];
128 DBG("ag71xx: ring %p, desc %d at %p\n",
129 ring
, i
, ring
->buf
[i
].desc
);
138 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
140 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
141 struct net_device
*dev
= ag
->dev
;
142 u32 bytes_compl
= 0, pkts_compl
= 0;
144 while (ring
->curr
!= ring
->dirty
) {
145 u32 i
= ring
->dirty
% ring
->size
;
147 if (!ag71xx_desc_empty(ring
->buf
[i
].desc
)) {
148 ring
->buf
[i
].desc
->ctrl
= 0;
149 dev
->stats
.tx_errors
++;
152 if (ring
->buf
[i
].skb
) {
153 bytes_compl
+= ring
->buf
[i
].len
;
155 dev_kfree_skb_any(ring
->buf
[i
].skb
);
157 ring
->buf
[i
].skb
= NULL
;
161 /* flush descriptors */
164 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
167 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
169 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
172 for (i
= 0; i
< ring
->size
; i
++) {
173 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
174 ring
->desc_size
* ((i
+ 1) % ring
->size
));
176 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
177 ring
->buf
[i
].skb
= NULL
;
180 /* flush descriptors */
185 netdev_reset_queue(ag
->dev
);
188 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
190 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
196 for (i
= 0; i
< ring
->size
; i
++)
197 if (ring
->buf
[i
].rx_buf
) {
198 dma_unmap_single(&ag
->dev
->dev
, ring
->buf
[i
].dma_addr
,
199 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
200 kfree(ring
->buf
[i
].rx_buf
);
204 static int ag71xx_buffer_offset(struct ag71xx
*ag
)
206 int offset
= NET_SKB_PAD
;
209 * On AR71xx/AR91xx packets must be 4-byte aligned.
211 * When using builtin AR8216 support, hardware adds a 2-byte header,
212 * so we don't need any extra alignment in that case.
214 if (!ag71xx_get_pdata(ag
)->is_ar724x
|| ag71xx_has_ar8216(ag
))
217 return offset
+ NET_IP_ALIGN
;
220 static bool ag71xx_fill_rx_buf(struct ag71xx
*ag
, struct ag71xx_buf
*buf
,
225 data
= kmalloc(ag
->rx_buf_size
+
226 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
)),
232 buf
->dma_addr
= dma_map_single(&ag
->dev
->dev
, data
, ag
->rx_buf_size
,
234 buf
->desc
->data
= (u32
) buf
->dma_addr
+ offset
;
238 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
240 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
243 int offset
= ag71xx_buffer_offset(ag
);
246 for (i
= 0; i
< ring
->size
; i
++) {
247 ring
->buf
[i
].desc
->next
= (u32
) (ring
->descs_dma
+
248 ring
->desc_size
* ((i
+ 1) % ring
->size
));
250 DBG("ag71xx: RX desc at %p, next is %08x\n",
252 ring
->buf
[i
].desc
->next
);
255 for (i
= 0; i
< ring
->size
; i
++) {
256 if (!ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
)) {
261 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
264 /* flush descriptors */
273 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
275 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
277 int offset
= ag71xx_buffer_offset(ag
);
280 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
283 i
= ring
->dirty
% ring
->size
;
285 if (!ring
->buf
[i
].rx_buf
&&
286 !ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
))
289 ring
->buf
[i
].desc
->ctrl
= DESC_EMPTY
;
293 /* flush descriptors */
296 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
301 static int ag71xx_rings_init(struct ag71xx
*ag
)
305 ret
= ag71xx_ring_alloc(&ag
->tx_ring
);
309 ag71xx_ring_tx_init(ag
);
311 ret
= ag71xx_ring_alloc(&ag
->rx_ring
);
315 ret
= ag71xx_ring_rx_init(ag
);
319 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
321 ag71xx_ring_rx_clean(ag
);
322 ag71xx_ring_free(&ag
->rx_ring
);
324 ag71xx_ring_tx_clean(ag
);
325 netdev_reset_queue(ag
->dev
);
326 ag71xx_ring_free(&ag
->tx_ring
);
329 static unsigned char *ag71xx_speed_str(struct ag71xx
*ag
)
343 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
347 t
= (((u32
) mac
[5]) << 24) | (((u32
) mac
[4]) << 16)
348 | (((u32
) mac
[3]) << 8) | ((u32
) mac
[2]);
350 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
352 t
= (((u32
) mac
[1]) << 24) | (((u32
) mac
[0]) << 16);
353 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
356 static void ag71xx_dma_reset(struct ag71xx
*ag
)
361 ag71xx_dump_dma_regs(ag
);
364 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
365 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
368 * give the hardware some time to really stop all rx/tx activity
369 * clearing the descriptors too early causes random memory corruption
373 /* clear descriptor addresses */
374 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->stop_desc_dma
);
375 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->stop_desc_dma
);
377 /* clear pending RX/TX interrupts */
378 for (i
= 0; i
< 256; i
++) {
379 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
380 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
383 /* clear pending errors */
384 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
385 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
387 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
389 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
392 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
394 /* mask out reserved bits */
398 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
401 ag71xx_dump_dma_regs(ag
);
404 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
405 MAC_CFG1_SRX | MAC_CFG1_STX)
407 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
409 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
410 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
411 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
412 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
413 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
416 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
417 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
418 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
419 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
420 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
421 FIFO_CFG5_17 | FIFO_CFG5_SF)
423 static void ag71xx_hw_stop(struct ag71xx
*ag
)
425 /* disable all interrupts and stop the rx/tx engine */
426 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
427 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
428 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
431 static void ag71xx_hw_setup(struct ag71xx
*ag
)
433 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
435 /* setup MAC configuration registers */
436 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_INIT
);
438 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
439 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
441 /* setup max frame length */
442 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, ag
->max_frame_len
);
444 /* setup FIFO configuration registers */
445 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
446 if (pdata
->is_ar724x
) {
447 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, pdata
->fifo_cfg1
);
448 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, pdata
->fifo_cfg2
);
450 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
451 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
453 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
454 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
457 static void ag71xx_hw_init(struct ag71xx
*ag
)
459 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
460 u32 reset_mask
= pdata
->reset_bit
;
464 if (pdata
->is_ar724x
) {
465 u32 reset_phy
= reset_mask
;
467 reset_phy
&= AR71XX_RESET_GE0_PHY
| AR71XX_RESET_GE1_PHY
;
468 reset_mask
&= ~(AR71XX_RESET_GE0_PHY
| AR71XX_RESET_GE1_PHY
);
470 ath79_device_reset_set(reset_phy
);
472 ath79_device_reset_clear(reset_phy
);
476 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
479 ath79_device_reset_set(reset_mask
);
481 ath79_device_reset_clear(reset_mask
);
486 ag71xx_dma_reset(ag
);
489 static void ag71xx_fast_reset(struct ag71xx
*ag
)
491 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
492 struct net_device
*dev
= ag
->dev
;
493 u32 reset_mask
= pdata
->reset_bit
;
497 reset_mask
&= AR71XX_RESET_GE0_MAC
| AR71XX_RESET_GE1_MAC
;
499 mii_reg
= ag71xx_rr(ag
, AG71XX_REG_MII_CFG
);
500 rx_ds
= ag71xx_rr(ag
, AG71XX_REG_RX_DESC
);
501 tx_ds
= ag71xx_rr(ag
, AG71XX_REG_TX_DESC
);
503 ath79_device_reset_set(reset_mask
);
505 ath79_device_reset_clear(reset_mask
);
508 ag71xx_dma_reset(ag
);
511 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, rx_ds
);
512 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, tx_ds
);
513 ag71xx_wr(ag
, AG71XX_REG_MII_CFG
, mii_reg
);
515 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
518 static void ag71xx_hw_start(struct ag71xx
*ag
)
520 /* start RX engine */
521 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
523 /* enable interrupts */
524 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
527 void ag71xx_link_adjust(struct ag71xx
*ag
)
529 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
536 netif_carrier_off(ag
->dev
);
537 if (netif_msg_link(ag
))
538 pr_info("%s: link down\n", ag
->dev
->name
);
542 if (pdata
->is_ar724x
)
543 ag71xx_fast_reset(ag
);
545 cfg2
= ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
);
546 cfg2
&= ~(MAC_CFG2_IF_1000
| MAC_CFG2_IF_10_100
| MAC_CFG2_FDX
);
547 cfg2
|= (ag
->duplex
) ? MAC_CFG2_FDX
: 0;
549 ifctl
= ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
);
550 ifctl
&= ~(MAC_IFCTL_SPEED
);
552 fifo5
= ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
);
553 fifo5
&= ~FIFO_CFG5_BM
;
557 cfg2
|= MAC_CFG2_IF_1000
;
558 fifo5
|= FIFO_CFG5_BM
;
561 cfg2
|= MAC_CFG2_IF_10_100
;
562 ifctl
|= MAC_IFCTL_SPEED
;
565 cfg2
|= MAC_CFG2_IF_10_100
;
572 if (pdata
->is_ar91xx
)
573 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x00780fff);
574 else if (pdata
->is_ar724x
)
575 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, pdata
->fifo_cfg3
);
577 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, 0x008001ff);
579 if (pdata
->set_speed
)
580 pdata
->set_speed(ag
->speed
);
582 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG2
, cfg2
);
583 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, fifo5
);
584 ag71xx_wr(ag
, AG71XX_REG_MAC_IFCTL
, ifctl
);
587 netif_carrier_on(ag
->dev
);
588 if (netif_msg_link(ag
))
589 pr_info("%s: link up (%sMbps/%s duplex)\n",
591 ag71xx_speed_str(ag
),
592 (DUPLEX_FULL
== ag
->duplex
) ? "Full" : "Half");
594 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
596 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
597 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
598 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
600 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
602 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
603 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
604 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
606 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
608 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
609 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
));
612 static int ag71xx_open(struct net_device
*dev
)
614 struct ag71xx
*ag
= netdev_priv(dev
);
617 ag
->rx_buf_size
= ag
->max_frame_len
+ NET_SKB_PAD
+ NET_IP_ALIGN
;
619 ret
= ag71xx_rings_init(ag
);
623 napi_enable(&ag
->napi
);
625 netif_carrier_off(dev
);
626 ag71xx_phy_start(ag
);
628 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
629 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
631 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
633 netif_start_queue(dev
);
638 ag71xx_rings_cleanup(ag
);
642 static int ag71xx_stop(struct net_device
*dev
)
644 struct ag71xx
*ag
= netdev_priv(dev
);
647 netif_carrier_off(dev
);
650 spin_lock_irqsave(&ag
->lock
, flags
);
652 netif_stop_queue(dev
);
655 ag71xx_dma_reset(ag
);
657 napi_disable(&ag
->napi
);
658 del_timer_sync(&ag
->oom_timer
);
660 spin_unlock_irqrestore(&ag
->lock
, flags
);
662 ag71xx_rings_cleanup(ag
);
667 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
668 struct net_device
*dev
)
670 struct ag71xx
*ag
= netdev_priv(dev
);
671 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
672 struct ag71xx_desc
*desc
;
676 i
= ring
->curr
% ring
->size
;
677 desc
= ring
->buf
[i
].desc
;
679 if (!ag71xx_desc_empty(desc
))
682 if (ag71xx_has_ar8216(ag
))
683 ag71xx_add_ar8216_header(ag
, skb
);
686 DBG("%s: packet len is too small\n", ag
->dev
->name
);
690 dma_addr
= dma_map_single(&dev
->dev
, skb
->data
, skb
->len
,
693 netdev_sent_queue(dev
, skb
->len
);
694 ring
->buf
[i
].len
= skb
->len
;
695 ring
->buf
[i
].skb
= skb
;
696 ring
->buf
[i
].timestamp
= jiffies
;
698 /* setup descriptor fields */
699 desc
->data
= (u32
) dma_addr
;
700 desc
->ctrl
= skb
->len
& ag
->desc_pktlen_mask
;
702 /* flush descriptor */
706 if (ring
->curr
== (ring
->dirty
+ ring
->size
)) {
707 DBG("%s: tx queue full\n", ag
->dev
->name
);
708 netif_stop_queue(dev
);
711 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
713 /* enable TX engine */
714 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
719 dev
->stats
.tx_dropped
++;
725 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
727 struct ag71xx
*ag
= netdev_priv(dev
);
732 if (ag
->phy_dev
== NULL
)
735 spin_lock_irq(&ag
->lock
);
736 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
737 spin_unlock_irq(&ag
->lock
);
742 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
748 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
755 if (ag
->phy_dev
== NULL
)
758 return phy_mii_ioctl(ag
->phy_dev
, ifr
, cmd
);
767 static void ag71xx_oom_timer_handler(unsigned long data
)
769 struct net_device
*dev
= (struct net_device
*) data
;
770 struct ag71xx
*ag
= netdev_priv(dev
);
772 napi_schedule(&ag
->napi
);
775 static void ag71xx_tx_timeout(struct net_device
*dev
)
777 struct ag71xx
*ag
= netdev_priv(dev
);
779 if (netif_msg_tx_err(ag
))
780 pr_info("%s: tx timeout\n", ag
->dev
->name
);
782 schedule_work(&ag
->restart_work
);
785 static void ag71xx_restart_work_func(struct work_struct
*work
)
787 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
);
789 if (ag71xx_get_pdata(ag
)->is_ar724x
) {
791 ag71xx_link_adjust(ag
);
795 ag71xx_stop(ag
->dev
);
796 ag71xx_open(ag
->dev
);
799 static bool ag71xx_check_dma_stuck(struct ag71xx
*ag
, unsigned long timestamp
)
801 u32 rx_sm
, tx_sm
, rx_fd
;
803 if (likely(time_before(jiffies
, timestamp
+ HZ
/10)))
806 if (!netif_carrier_ok(ag
->dev
))
809 rx_sm
= ag71xx_rr(ag
, AG71XX_REG_RX_SM
);
810 if ((rx_sm
& 0x7) == 0x3 && ((rx_sm
>> 4) & 0x7) == 0x6)
813 tx_sm
= ag71xx_rr(ag
, AG71XX_REG_TX_SM
);
814 rx_fd
= ag71xx_rr(ag
, AG71XX_REG_FIFO_DEPTH
);
815 if (((tx_sm
>> 4) & 0x7) == 0 && ((rx_sm
& 0x7) == 0) &&
816 ((rx_sm
>> 4) & 0x7) == 0 && rx_fd
== 0)
822 static int ag71xx_tx_packets(struct ag71xx
*ag
)
824 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
825 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
829 DBG("%s: processing TX ring\n", ag
->dev
->name
);
831 while (ring
->dirty
!= ring
->curr
) {
832 unsigned int i
= ring
->dirty
% ring
->size
;
833 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
834 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
835 int len
= ring
->buf
[i
].len
;
837 if (!ag71xx_desc_empty(desc
)) {
838 if (pdata
->is_ar7240
&&
839 ag71xx_check_dma_stuck(ag
, ring
->buf
[i
].timestamp
))
840 schedule_work(&ag
->restart_work
);
844 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
847 ag
->dev
->stats
.tx_bytes
+= len
;
848 ag
->dev
->stats
.tx_packets
++;
850 dev_kfree_skb_any(skb
);
851 ring
->buf
[i
].skb
= NULL
;
857 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
862 netdev_completed_queue(ag
->dev
, sent
, bytes_compl
);
863 if ((ring
->curr
- ring
->dirty
) < (ring
->size
* 3) / 4)
864 netif_wake_queue(ag
->dev
);
869 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
871 struct net_device
*dev
= ag
->dev
;
872 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
873 int offset
= ag71xx_buffer_offset(ag
);
874 unsigned int pktlen_mask
= ag
->desc_pktlen_mask
;
877 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
878 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
880 while (done
< limit
) {
881 unsigned int i
= ring
->curr
% ring
->size
;
882 struct ag71xx_desc
*desc
= ring
->buf
[i
].desc
;
887 if (ag71xx_desc_empty(desc
))
890 if ((ring
->dirty
+ ring
->size
) == ring
->curr
) {
895 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
897 pktlen
= desc
->ctrl
& pktlen_mask
;
898 pktlen
-= ETH_FCS_LEN
;
900 dma_unmap_single(&dev
->dev
, ring
->buf
[i
].dma_addr
,
901 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
903 dev
->stats
.rx_packets
++;
904 dev
->stats
.rx_bytes
+= pktlen
;
906 skb
= build_skb(ring
->buf
[i
].rx_buf
, 0);
908 kfree(ring
->buf
[i
].rx_buf
);
912 skb_reserve(skb
, offset
);
913 skb_put(skb
, pktlen
);
915 if (ag71xx_has_ar8216(ag
))
916 err
= ag71xx_remove_ar8216_header(ag
, skb
, pktlen
);
919 dev
->stats
.rx_dropped
++;
923 skb
->ip_summed
= CHECKSUM_NONE
;
924 skb
->protocol
= eth_type_trans(skb
, dev
);
925 netif_receive_skb(skb
);
929 ring
->buf
[i
].rx_buf
= NULL
;
935 ag71xx_ring_rx_refill(ag
);
937 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
938 dev
->name
, ring
->curr
, ring
->dirty
, done
);
943 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
945 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
946 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
947 struct net_device
*dev
= ag
->dev
;
948 struct ag71xx_ring
*rx_ring
;
955 tx_done
= ag71xx_tx_packets(ag
);
957 DBG("%s: processing RX ring\n", dev
->name
);
958 rx_done
= ag71xx_rx_packets(ag
, limit
);
960 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
962 rx_ring
= &ag
->rx_ring
;
963 if (rx_ring
->buf
[rx_ring
->dirty
% rx_ring
->size
].rx_buf
== NULL
)
966 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
967 if (unlikely(status
& RX_STATUS_OF
)) {
968 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
969 dev
->stats
.rx_fifo_errors
++;
972 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
975 if (rx_done
< limit
) {
976 if (status
& RX_STATUS_PR
)
979 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
980 if (status
& TX_STATUS_PS
)
983 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
984 dev
->name
, rx_done
, tx_done
, limit
);
988 /* enable interrupts */
989 spin_lock_irqsave(&ag
->lock
, flags
);
990 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
991 spin_unlock_irqrestore(&ag
->lock
, flags
);
996 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
997 dev
->name
, rx_done
, tx_done
, limit
);
1001 if (netif_msg_rx_err(ag
))
1002 pr_info("%s: out of memory\n", dev
->name
);
1004 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
1005 napi_complete(napi
);
1009 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
1011 struct net_device
*dev
= dev_id
;
1012 struct ag71xx
*ag
= netdev_priv(dev
);
1015 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
1016 ag71xx_dump_intr(ag
, "raw", status
);
1018 if (unlikely(!status
))
1021 if (unlikely(status
& AG71XX_INT_ERR
)) {
1022 if (status
& AG71XX_INT_TX_BE
) {
1023 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
1024 dev_err(&dev
->dev
, "TX BUS error\n");
1026 if (status
& AG71XX_INT_RX_BE
) {
1027 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
1028 dev_err(&dev
->dev
, "RX BUS error\n");
1032 if (likely(status
& AG71XX_INT_POLL
)) {
1033 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
1034 DBG("%s: enable polling mode\n", dev
->name
);
1035 napi_schedule(&ag
->napi
);
1038 ag71xx_debugfs_update_int_stats(ag
, status
);
1043 #ifdef CONFIG_NET_POLL_CONTROLLER
1045 * Polling 'interrupt' - used by things like netconsole to send skbs
1046 * without having to re-enable interrupts. It's not called while
1047 * the interrupt routine is executing.
1049 static void ag71xx_netpoll(struct net_device
*dev
)
1051 disable_irq(dev
->irq
);
1052 ag71xx_interrupt(dev
->irq
, dev
);
1053 enable_irq(dev
->irq
);
1057 static int ag71xx_change_mtu(struct net_device
*dev
, int new_mtu
)
1059 struct ag71xx
*ag
= netdev_priv(dev
);
1060 unsigned int max_frame_len
;
1062 max_frame_len
= ag71xx_max_frame_len(new_mtu
);
1063 if (new_mtu
< 68 || max_frame_len
> ag
->max_frame_len
)
1070 static const struct net_device_ops ag71xx_netdev_ops
= {
1071 .ndo_open
= ag71xx_open
,
1072 .ndo_stop
= ag71xx_stop
,
1073 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
1074 .ndo_do_ioctl
= ag71xx_do_ioctl
,
1075 .ndo_tx_timeout
= ag71xx_tx_timeout
,
1076 .ndo_change_mtu
= ag71xx_change_mtu
,
1077 .ndo_set_mac_address
= eth_mac_addr
,
1078 .ndo_validate_addr
= eth_validate_addr
,
1079 #ifdef CONFIG_NET_POLL_CONTROLLER
1080 .ndo_poll_controller
= ag71xx_netpoll
,
1084 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode
)
1087 case PHY_INTERFACE_MODE_MII
:
1089 case PHY_INTERFACE_MODE_GMII
:
1091 case PHY_INTERFACE_MODE_RMII
:
1093 case PHY_INTERFACE_MODE_RGMII
:
1095 case PHY_INTERFACE_MODE_SGMII
:
1105 static int ag71xx_probe(struct platform_device
*pdev
)
1107 struct net_device
*dev
;
1108 struct resource
*res
;
1110 struct ag71xx_platform_data
*pdata
;
1113 pdata
= pdev
->dev
.platform_data
;
1115 dev_err(&pdev
->dev
, "no platform data specified\n");
1120 if (pdata
->mii_bus_dev
== NULL
&& pdata
->phy_mask
) {
1121 dev_err(&pdev
->dev
, "no MII bus device specified\n");
1126 dev
= alloc_etherdev(sizeof(*ag
));
1128 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1133 if (!pdata
->max_frame_len
|| !pdata
->desc_pktlen_mask
)
1136 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1138 ag
= netdev_priv(dev
);
1141 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
1142 AG71XX_DEFAULT_MSG_ENABLE
);
1143 spin_lock_init(&ag
->lock
);
1145 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
1147 dev_err(&pdev
->dev
, "no mac_base resource found\n");
1152 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
1153 if (!ag
->mac_base
) {
1154 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
1159 dev
->irq
= platform_get_irq(pdev
, 0);
1160 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
1164 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
1165 goto err_unmap_base
;
1168 dev
->base_addr
= (unsigned long)ag
->mac_base
;
1169 dev
->netdev_ops
= &ag71xx_netdev_ops
;
1170 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
1172 INIT_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
1174 init_timer(&ag
->oom_timer
);
1175 ag
->oom_timer
.data
= (unsigned long) dev
;
1176 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
1178 ag
->tx_ring
.size
= AG71XX_TX_RING_SIZE_DEFAULT
;
1179 ag
->rx_ring
.size
= AG71XX_RX_RING_SIZE_DEFAULT
;
1181 ag
->max_frame_len
= pdata
->max_frame_len
;
1182 ag
->desc_pktlen_mask
= pdata
->desc_pktlen_mask
;
1184 ag
->stop_desc
= dma_alloc_coherent(NULL
,
1185 sizeof(struct ag71xx_desc
), &ag
->stop_desc_dma
, GFP_KERNEL
);
1190 ag
->stop_desc
->data
= 0;
1191 ag
->stop_desc
->ctrl
= 0;
1192 ag
->stop_desc
->next
= (u32
) ag
->stop_desc_dma
;
1194 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
1196 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
1198 ag71xx_dump_regs(ag
);
1202 ag71xx_dump_regs(ag
);
1204 err
= ag71xx_phy_connect(ag
);
1208 err
= ag71xx_debugfs_init(ag
);
1210 goto err_phy_disconnect
;
1212 platform_set_drvdata(pdev
, dev
);
1214 err
= register_netdev(dev
);
1216 dev_err(&pdev
->dev
, "unable to register net device\n");
1217 goto err_debugfs_exit
;
1220 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1221 dev
->name
, dev
->base_addr
, dev
->irq
,
1222 ag71xx_get_phy_if_mode_name(pdata
->phy_if_mode
));
1227 ag71xx_debugfs_exit(ag
);
1229 ag71xx_phy_disconnect(ag
);
1231 dma_free_coherent(NULL
, sizeof(struct ag71xx_desc
), ag
->stop_desc
,
1234 free_irq(dev
->irq
, dev
);
1236 iounmap(ag
->mac_base
);
1240 platform_set_drvdata(pdev
, NULL
);
1244 static int ag71xx_remove(struct platform_device
*pdev
)
1246 struct net_device
*dev
= platform_get_drvdata(pdev
);
1249 struct ag71xx
*ag
= netdev_priv(dev
);
1251 ag71xx_debugfs_exit(ag
);
1252 ag71xx_phy_disconnect(ag
);
1253 unregister_netdev(dev
);
1254 free_irq(dev
->irq
, dev
);
1255 iounmap(ag
->mac_base
);
1257 platform_set_drvdata(pdev
, NULL
);
1263 static struct platform_driver ag71xx_driver
= {
1264 .probe
= ag71xx_probe
,
1265 .remove
= ag71xx_remove
,
1267 .name
= AG71XX_DRV_NAME
,
1271 static int __init
ag71xx_module_init(void)
1275 ret
= ag71xx_debugfs_root_init();
1279 ret
= ag71xx_mdio_driver_init();
1281 goto err_debugfs_exit
;
1283 ret
= platform_driver_register(&ag71xx_driver
);
1290 ag71xx_mdio_driver_exit();
1292 ag71xx_debugfs_root_exit();
1297 static void __exit
ag71xx_module_exit(void)
1299 platform_driver_unregister(&ag71xx_driver
);
1300 ag71xx_mdio_driver_exit();
1301 ag71xx_debugfs_root_exit();
1304 module_init(ag71xx_module_init
);
1305 module_exit(ag71xx_module_exit
);
1307 MODULE_VERSION(AG71XX_DRV_VERSION
);
1308 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1309 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1310 MODULE_LICENSE("GPL v2");
1311 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);