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[openwrt/staging/florian.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 #ifdef DEBUG
213 struct dentry *debugfs_root;
214 #endif
215 };
216
217 #ifdef DEBUG
218 u16 g_dbg_reg;
219 #endif
220
221 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
222
223 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
224 {
225 ndelay(RTL8366_SMI_CLK_DELAY);
226 }
227
228 static void rtl8366_smi_start(struct rtl8366_smi *smi)
229 {
230 unsigned int sda = smi->pdata->gpio_sda;
231 unsigned int sck = smi->pdata->gpio_sck;
232
233 /*
234 * Set GPIO pins to output mode, with initial state:
235 * SCK = 0, SDA = 1
236 */
237 gpio_direction_output(sck, 0);
238 gpio_direction_output(sda, 1);
239 rtl8366_smi_clk_delay(smi);
240
241 /* CLK 1: 0 -> 1, 1 -> 0 */
242 gpio_set_value(sck, 1);
243 rtl8366_smi_clk_delay(smi);
244 gpio_set_value(sck, 0);
245 rtl8366_smi_clk_delay(smi);
246
247 /* CLK 2: */
248 gpio_set_value(sck, 1);
249 rtl8366_smi_clk_delay(smi);
250 gpio_set_value(sda, 0);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 1);
255 }
256
257 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
258 {
259 unsigned int sda = smi->pdata->gpio_sda;
260 unsigned int sck = smi->pdata->gpio_sck;
261
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sda, 0);
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 0);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
273
274 /* add a click */
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 0);
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 1);
279
280 /* set GPIO pins to input mode */
281 gpio_direction_input(sda);
282 gpio_direction_input(sck);
283 }
284
285 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
286 {
287 unsigned int sda = smi->pdata->gpio_sda;
288 unsigned int sck = smi->pdata->gpio_sck;
289
290 for (; len > 0; len--) {
291 rtl8366_smi_clk_delay(smi);
292
293 /* prepare data */
294 if ( data & ( 1 << (len - 1)) )
295 gpio_set_value(sda, 1);
296 else
297 gpio_set_value(sda, 0);
298 rtl8366_smi_clk_delay(smi);
299
300 /* clocking */
301 gpio_set_value(sck, 1);
302 rtl8366_smi_clk_delay(smi);
303 gpio_set_value(sck, 0);
304 }
305 }
306
307 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
308 {
309 unsigned int sda = smi->pdata->gpio_sda;
310 unsigned int sck = smi->pdata->gpio_sck;
311
312 gpio_direction_input(sda);
313
314 for (*data = 0; len > 0; len--) {
315 u32 u;
316
317 rtl8366_smi_clk_delay(smi);
318
319 /* clocking */
320 gpio_set_value(sck, 1);
321 rtl8366_smi_clk_delay(smi);
322 u = gpio_get_value(sda);
323 gpio_set_value(sck, 0);
324
325 *data |= (u << (len - 1));
326 }
327
328 gpio_direction_output(sda, 0);
329 }
330
331 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
332 {
333 int retry_cnt;
334
335 retry_cnt = 0;
336 do {
337 u32 ack;
338
339 rtl8366_smi_read_bits(smi, 1, &ack);
340 if (ack == 0)
341 break;
342
343 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
344 return -EIO;
345 } while (1);
346
347 return 0;
348 }
349
350 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
351 {
352 rtl8366_smi_write_bits(smi, data, 8);
353 return rtl8366_smi_wait_for_ack(smi);
354 }
355
356 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
357 {
358 u32 t;
359
360 /* read data */
361 rtl8366_smi_read_bits(smi, 8, &t);
362 *data = (t & 0xff);
363
364 /* send an ACK */
365 rtl8366_smi_write_bits(smi, 0x00, 1);
366
367 return 0;
368 }
369
370 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
371 {
372 u32 t;
373
374 /* read data */
375 rtl8366_smi_read_bits(smi, 8, &t);
376 *data = (t & 0xff);
377
378 /* send an ACK */
379 rtl8366_smi_write_bits(smi, 0x01, 1);
380
381 return 0;
382 }
383
384 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
385 {
386 unsigned long flags;
387 u8 lo = 0;
388 u8 hi = 0;
389 int ret;
390
391 spin_lock_irqsave(&smi->lock, flags);
392
393 rtl8366_smi_start(smi);
394
395 /* send READ command */
396 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
397 if (ret)
398 goto out;
399
400 /* set ADDR[7:0] */
401 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
402 if (ret)
403 goto out;
404
405 /* set ADDR[15:8] */
406 ret = rtl8366_smi_write_byte(smi, addr >> 8);
407 if (ret)
408 goto out;
409
410 /* read DATA[7:0] */
411 rtl8366_smi_read_byte0(smi, &lo);
412 /* read DATA[15:8] */
413 rtl8366_smi_read_byte1(smi, &hi);
414
415 *data = ((u32) lo) | (((u32) hi) << 8);
416
417 ret = 0;
418
419 out:
420 rtl8366_smi_stop(smi);
421 spin_unlock_irqrestore(&smi->lock, flags);
422
423 return ret;
424 }
425
426 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
427 {
428 unsigned long flags;
429 int ret;
430
431 spin_lock_irqsave(&smi->lock, flags);
432
433 rtl8366_smi_start(smi);
434
435 /* send WRITE command */
436 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
437 if (ret)
438 goto out;
439
440 /* set ADDR[7:0] */
441 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
442 if (ret)
443 goto out;
444
445 /* set ADDR[15:8] */
446 ret = rtl8366_smi_write_byte(smi, addr >> 8);
447 if (ret)
448 goto out;
449
450 /* write DATA[7:0] */
451 ret = rtl8366_smi_write_byte(smi, data & 0xff);
452 if (ret)
453 goto out;
454
455 /* write DATA[15:8] */
456 ret = rtl8366_smi_write_byte(smi, data >> 8);
457 if (ret)
458 goto out;
459
460 ret = 0;
461
462 out:
463 rtl8366_smi_stop(smi);
464 spin_unlock_irqrestore(&smi->lock, flags);
465
466 return ret;
467 }
468
469 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
470 u32 phy_no, u32 page, u32 addr, u32 *data)
471 {
472 u32 reg;
473 int ret;
474
475 if (phy_no > RTL8366S_PHY_NO_MAX)
476 return -EINVAL;
477
478 if (page > RTL8366S_PHY_PAGE_MAX)
479 return -EINVAL;
480
481 if (addr > RTL8366S_PHY_ADDR_MAX)
482 return -EINVAL;
483
484 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
485 RTL8366S_PHY_CTRL_READ);
486 if (ret)
487 return ret;
488
489 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
490 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
491 (addr & RTL8366S_PHY_REG_MASK);
492
493 ret = rtl8366_smi_write_reg(smi, reg, 0);
494 if (ret)
495 return ret;
496
497 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
498 if (ret)
499 return ret;
500
501 return 0;
502 }
503
504 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
505 u32 phy_no, u32 page, u32 addr, u32 data)
506 {
507 u32 reg;
508 int ret;
509
510 if (phy_no > RTL8366S_PHY_NO_MAX)
511 return -EINVAL;
512
513 if (page > RTL8366S_PHY_PAGE_MAX)
514 return -EINVAL;
515
516 if (addr > RTL8366S_PHY_ADDR_MAX)
517 return -EINVAL;
518
519 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
520 RTL8366S_PHY_CTRL_WRITE);
521 if (ret)
522 return ret;
523
524 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
525 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
526 (addr & RTL8366S_PHY_REG_MASK);
527
528 ret = rtl8366_smi_write_reg(smi, reg, data);
529 if (ret)
530 return ret;
531
532 return 0;
533 }
534
535 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
536 int port, unsigned long long *val)
537 {
538 int i;
539 int err;
540 u32 addr, data, regoffset;
541 u64 mibvalue;
542
543 /* address offset to MIBs counter */
544 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
545 2, 2, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 4, 2, 2, 2, 2, 2, 2,
547 2, 2, 2, 2, 2, 2};
548
549 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
550 return -EINVAL;
551
552 i = 0;
553 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
554
555 while (i < counter) {
556 regoffset += mibLength[i];
557 i++;
558 }
559
560 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
561
562
563 /* writing access counter address first */
564 /* then ASIC will prepare 64bits counter wait for being retrived */
565 data = 0;/* writing data will be discard by ASIC */
566 err = rtl8366_smi_write_reg(smi, addr, data);
567 if (err)
568 return err;
569
570 /* read MIB control register */
571 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
572 if (err)
573 return err;
574
575 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
576 return -EBUSY;
577
578 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
579 return -EIO;
580
581 mibvalue = 0;
582 addr = addr + mibLength[counter] - 1;
583 i = mibLength[counter];
584
585 while (i) {
586 err = rtl8366_smi_read_reg(smi, addr, &data);
587 if (err)
588 return err;
589
590 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
591
592 addr--;
593 i--;
594 }
595
596 *val = mibvalue;
597 return 0;
598 }
599
600 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
601 struct rtl8366s_vlan4kentry *vlan4k)
602 {
603 int err;
604 u32 data;
605 u16 *tableaddr;
606
607 vlan4k->vid = vid;
608
609 if (vid >= RTL8366_NUM_VIDS)
610 return -EINVAL;
611
612 tableaddr = (u16 *)vlan4k;
613
614 /* write VID */
615 data = *tableaddr;
616 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
617 if (err)
618 return err;
619
620 /* write table access control word */
621 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
622 RTL8366S_TABLE_VLAN_READ_CTRL);
623 if (err)
624 return err;
625
626 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
627 if (err)
628 return err;
629
630 *tableaddr = data;
631 tableaddr++;
632
633 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
634 &data);
635 if (err)
636 return err;
637
638 *tableaddr = data;
639 vlan4k->vid = vid;
640
641 return 0;
642 }
643
644 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
645 const struct rtl8366s_vlan4kentry *vlan4k)
646 {
647 int err;
648 u32 data;
649 u16 *tableaddr;
650
651 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
652 vlan4k->member > RTL8366_PORT_ALL ||
653 vlan4k->untag > RTL8366_PORT_ALL ||
654 vlan4k->fid > RTL8366S_FIDMAX)
655 return -EINVAL;
656
657 tableaddr = (u16 *)vlan4k;
658
659 data = *tableaddr;
660
661 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
662 if (err)
663 return err;
664
665 tableaddr++;
666
667 data = *tableaddr;
668
669 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
670
671
672 /* write table access control word */
673 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
674 RTL8366S_TABLE_VLAN_WRITE_CTRL);
675 if (err)
676 return err;
677
678 return 0;
679 }
680
681 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
682 struct rtl8366s_vlanconfig
683 *vlanmconf)
684 {
685 int err;
686 u32 addr;
687 u32 data;
688 u16 *tableaddr;
689
690 if (index >= RTL8366_NUM_VLANS)
691 return -EINVAL;
692
693 tableaddr = (u16 *)vlanmconf;
694
695 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
696
697 err = rtl8366_smi_read_reg(smi, addr, &data);
698 if (err)
699 return err;
700
701 *tableaddr = data;
702 tableaddr++;
703
704 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
705
706 err = rtl8366_smi_read_reg(smi, addr, &data);
707 if (err)
708 return err;
709
710 *tableaddr = data;
711
712 return 0;
713 }
714
715 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
716 const struct rtl8366s_vlanconfig
717 *vlanmconf)
718 {
719 int err;
720 u32 addr;
721 u32 data;
722 u16 *tableaddr;
723
724 if (index >= RTL8366_NUM_VLANS ||
725 vlanmconf->vid >= RTL8366_NUM_VIDS ||
726 vlanmconf->priority > RTL8366S_PRIORITYMAX ||
727 vlanmconf->member > RTL8366_PORT_ALL ||
728 vlanmconf->untag > RTL8366_PORT_ALL ||
729 vlanmconf->fid > RTL8366S_FIDMAX)
730 return -EINVAL;
731
732 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
733
734
735 tableaddr = (u16 *)vlanmconf;
736 data = *tableaddr;
737
738 err = rtl8366_smi_write_reg(smi, addr, data);
739 if (err)
740 return err;
741
742 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
743
744 tableaddr++;
745 data = *tableaddr;
746
747 err = rtl8366_smi_write_reg(smi, addr, data);
748 if (err)
749 return err;
750
751 return 0;
752 }
753
754 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
755 int *val)
756 {
757 int err;
758 u32 addr;
759 u32 data;
760
761 /* bits mapping to port vlan control register of port n */
762 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
763 0xF000, 0x000F, 0x00F0 };
764 /* bits offset to port vlan control register of port n */
765 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
766 /* address offset to port vlan control register of port n */
767 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
768
769 if (port >= RTL8366_NUM_PORTS)
770 return -EINVAL;
771
772 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
773
774 err = rtl8366_smi_read_reg(smi, addr, &data);
775 if (err)
776 return err;
777
778 *val = (data & bits[port]) >> bitoffset[port];
779
780 return 0;
781
782 }
783
784 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
785 int *val)
786 {
787 int err;
788 int index;
789 struct rtl8366s_vlanconfig vlanMC;
790
791 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
792
793 err = rtl8366_get_port_vlan_index(smi, port, &index);
794 if (err)
795 return err;
796
797 err = rtl8366s_get_vlan_member_config(smi, index, &vlanMC);
798 if (err)
799 return err;
800
801 *val = vlanMC.vid;
802 return 0;
803 }
804
805 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
806 int index)
807 {
808 int err;
809 u32 addr;
810 u32 data;
811 u32 vlan_data;
812 u32 bits;
813
814 /* bits mapping to port vlan control register of port n */
815 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
816 0xF000, 0x000F, 0x00F0 };
817 /* bits offset to port vlan control register of port n */
818 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
819 /* address offset to port vlan control register of port n */
820 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
821
822 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
823 return -EINVAL;
824
825 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
826
827 bits = bitmasks[port];
828
829 data = (index << bitOff[port]) & bits;
830
831 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
832 if (err)
833 return err;
834
835 vlan_data &= ~(vlan_data & bits);
836 vlan_data |= data;
837
838 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
839 if (err)
840 return err;
841
842 return 0;
843 }
844
845 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
846 int val)
847 {
848 int i;
849 struct rtl8366s_vlanconfig vlanMC;
850 struct rtl8366s_vlan4kentry vlan4K;
851
852 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
853 return -EINVAL;
854
855
856
857 /* Updating the 4K entry; lookup it and change the port member set */
858 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
859 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4K);
860 vlan4K.member |= ((1 << port) | RTL8366_PORT_CPU);
861 vlan4K.untag = RTL8366_PORT_ALL_BUT_CPU;
862 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
863
864 /* For the 16 entries more work needs to be done. First see if such
865 VID is already there and change it */
866 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
867 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
868 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
869
870 /* Try to find an existing vid and update port member set */
871 if (val == vlanMC.vid) {
872 vlanMC.member |= ((1 << port) | RTL8366_PORT_CPU);
873 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
874
875 /* Now update PVID register settings */
876 rtl8366_set_port_vlan_index(smi, port, i);
877
878 return 0;
879 }
880 }
881
882 /* PVID could not be found from vlan table. Replace unused (one that
883 has no member ports) with new one */
884 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
885 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
886 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
887
888 /* See if this vlan member configuration is unused. It is
889 unused if member set contains no ports or CPU port only */
890 if (!vlanMC.member || vlanMC.member == RTL8366_PORT_CPU) {
891 vlanMC.vid = val;
892 vlanMC.priority = 0;
893 vlanMC.untag = RTL8366_PORT_ALL_BUT_CPU;
894 vlanMC.member = ((1 << port) | RTL8366_PORT_CPU);
895 vlanMC.fid = 0;
896
897 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
898
899 /* Now update PVID register settings */
900 rtl8366_set_port_vlan_index(smi, port, i);
901
902 return 0;
903 }
904 }
905
906 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
907 "use\n");
908 return -EINVAL;
909 }
910
911
912 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
913 {
914 u32 data = 0;
915 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
916
917 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
918 if (enable)
919 data |= RTL8366_CHIP_CTRL_VLAN;
920
921 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
922 }
923
924 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
925 {
926 u32 data = 0;
927 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
928
929 data &= ~(data & 1);
930 if (enable)
931 data |= 1;
932
933 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
934 }
935
936 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
937 {
938 int i;
939 struct rtl8366s_vlan4kentry vlan4K;
940 struct rtl8366s_vlanconfig vlanMC;
941
942 /* clear 16 VLAN member configuration */
943 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
944 vlanMC.vid = 0;
945 vlanMC.priority = 0;
946 vlanMC.member = 0;
947 vlanMC.untag = 0;
948 vlanMC.fid = 0;
949 if (rtl8366s_set_vlan_member_config(smi, i, &vlanMC) != 0)
950 return -EIO;
951 }
952
953 /* Set a default VLAN with vid 1 to 4K table for all ports */
954 vlan4K.vid = 1;
955 vlan4K.member = RTL8366_PORT_ALL;
956 vlan4K.untag = RTL8366_PORT_ALL;
957 vlan4K.fid = 0;
958 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4K) != 0)
959 return -EIO;
960
961 /* Set all ports PVID to default VLAN */
962 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
963 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
964 return -EIO;
965 }
966
967 return 0;
968 }
969
970 #ifdef DEBUG
971 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
972 {
973 file->private_data = inode->i_private;
974 return 0;
975 }
976
977 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
978 char __user *user_buf,
979 size_t count, loff_t *ppos)
980 {
981 char buf[4096];
982 int i, j, len = 0;
983 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
984
985 len += snprintf(buf + len, sizeof(buf) - len, "MIB Counters:\n");
986 len += snprintf(buf + len, sizeof(buf) - len, "Counter"
987 " "
988 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
989 "Port 4\n");
990
991 for (i = 0; i < 33; ++i) {
992
993 len += snprintf(buf + len, sizeof(buf) - len, "%d:%s ",
994 i, MIBCOUNTERS[i]);
995 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
996 unsigned long long counter = 0;
997
998 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
999 len += snprintf(buf + len, sizeof(buf) - len,
1000 "[%llu]", counter);
1001 else
1002 len += snprintf(buf + len, sizeof(buf) - len,
1003 "[error]");
1004
1005 if (j != RTL8366_NUM_PORTS - 1) {
1006 if (counter < 100000)
1007 len += snprintf(buf + len,
1008 sizeof(buf) - len,
1009 "\t");
1010
1011 len += snprintf(buf + len, sizeof(buf) - len,
1012 "\t");
1013 }
1014 }
1015 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1016 }
1017
1018 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1019
1020 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1021 }
1022
1023 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1024 char __user *user_buf,
1025 size_t count, loff_t *ppos)
1026 {
1027 char buf[4096];
1028 int i, j, len = 0;
1029 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1030
1031 len += snprintf(buf + len, sizeof(buf) - len, "VLAN Member Config:\n");
1032 len += snprintf(buf + len, sizeof(buf) - len,
1033 "\t id \t vid \t prio \t member \t untag \t fid "
1034 "\tports\n");
1035
1036 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1037 struct rtl8366s_vlanconfig vlanMC;
1038 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1039 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
1040
1041 len += snprintf(buf + len, sizeof(buf) - len,
1042 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1043 "\t", i, vlanMC.vid, vlanMC.priority,
1044 vlanMC.member, vlanMC.untag, vlanMC.fid);
1045
1046 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1047 int index = 0;
1048 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1049 if (index == i)
1050 len += snprintf(buf + len,
1051 sizeof(buf) - len,
1052 "%d", j);
1053 }
1054 }
1055 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1056 }
1057
1058 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1059 }
1060
1061 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1062 char __user *user_buf,
1063 size_t count, loff_t *ppos)
1064 {
1065 u32 t, reg = g_dbg_reg;
1066 int err, len = 0;
1067 char buf[512];
1068 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1069
1070 memset(buf, '\0', sizeof(buf));
1071
1072 err = rtl8366_smi_read_reg(smi, reg, &t);
1073 if (err) {
1074 len += snprintf(buf, sizeof(buf),
1075 "Read failed (reg: 0x%04x)\n", reg);
1076 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1077 }
1078
1079 len += snprintf(buf, sizeof(buf), "reg = 0x%04x, val = 0x%04x\n",
1080 reg, t);
1081
1082 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1083 }
1084
1085 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1086 const char __user *user_buf,
1087 size_t count, loff_t *ppos)
1088 {
1089 unsigned long data;
1090 u32 reg = g_dbg_reg;
1091 int err;
1092 char buf[50];
1093 size_t len;
1094 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1095
1096 len = min(count, sizeof(buf) - 1);
1097 if (copy_from_user(buf, user_buf, len)) {
1098 dev_err(&smi->pdev->dev, "copy from user failed\n");
1099 return -EFAULT;
1100 }
1101
1102 buf[len] = '\0';
1103 if (len > 0 && buf[len - 1] == '\n')
1104 buf[len - 1] = '\0';
1105
1106
1107 if (strict_strtoul(buf, 16, &data)) {
1108 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1109 } else {
1110 err = rtl8366_smi_write_reg(smi, reg, data);
1111 if (err) {
1112 dev_err(&smi->pdev->dev,
1113 "writing reg 0x%04x val 0x%04lx failed\n",
1114 reg, data);
1115 }
1116 }
1117
1118 return count;
1119 }
1120
1121 static const struct file_operations fops_rtl8366_regs = {
1122 .read = rtl8366_read_debugfs_reg,
1123 .write = rtl8366_write_debugfs_reg,
1124 .open = rtl8366_debugfs_open,
1125 .owner = THIS_MODULE
1126 };
1127
1128 static const struct file_operations fops_rtl8366_vlan = {
1129 .read = rtl8366_read_debugfs_vlan,
1130 .open = rtl8366_debugfs_open,
1131 .owner = THIS_MODULE
1132 };
1133
1134 static const struct file_operations fops_rtl8366_mibs = {
1135 .read = rtl8366_read_debugfs_mibs,
1136 .open = rtl8366_debugfs_open,
1137 .owner = THIS_MODULE
1138 };
1139
1140 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1141 {
1142 struct dentry *node;
1143 struct dentry *root;
1144
1145 if (!smi->debugfs_root)
1146 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1147
1148 if (!smi->debugfs_root) {
1149 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1150 return;
1151 }
1152 root = smi->debugfs_root;
1153
1154 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1155 if (!node) {
1156 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1157 return;
1158 }
1159
1160 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1161 &fops_rtl8366_regs);
1162 if (!node) {
1163 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1164 return;
1165 }
1166
1167 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1168 &fops_rtl8366_vlan);
1169 if (!node) {
1170 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1171 "failed\n");
1172 return;
1173 }
1174
1175 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1176 &fops_rtl8366_mibs);
1177 if (!node) {
1178 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1179 "xfailed\n");
1180 return;
1181 }
1182 }
1183
1184 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1185 {
1186 if (smi->debugfs_root) {
1187 debugfs_remove_recursive(smi->debugfs_root);
1188 smi->debugfs_root = NULL;
1189 }
1190 }
1191
1192 #else
1193 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1194 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1195 #endif
1196
1197 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1198 const struct switch_attr *attr,
1199 struct switch_val *val)
1200 {
1201 u32 data = 0;
1202 struct rtl8366_smi *smi = to_rtl8366(dev);
1203
1204 if (val->value.i == 1) {
1205 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1206 data |= (1 << 2);
1207 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1208 }
1209
1210 return 0;
1211 }
1212
1213 static int rtl8366_get_vlan(struct switch_dev *dev,
1214 const struct switch_attr *attr,
1215 struct switch_val *val)
1216 {
1217 u32 data;
1218 struct rtl8366_smi *smi = to_rtl8366(dev);
1219
1220 if (attr->ofs == 1) {
1221 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1222
1223 if (data & RTL8366_CHIP_CTRL_VLAN)
1224 val->value.i = 1;
1225 else
1226 val->value.i = 0;
1227 } else if (attr->ofs == 2) {
1228 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1229
1230 if (data & 0x0001)
1231 val->value.i = 1;
1232 else
1233 val->value.i = 0;
1234 }
1235
1236 return 0;
1237 }
1238
1239 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1240 const struct switch_attr *attr,
1241 struct switch_val *val)
1242 {
1243 u32 data;
1244 struct rtl8366_smi *smi = to_rtl8366(dev);
1245 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1246
1247 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1248
1249 return 0;
1250 }
1251
1252 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1253 const struct switch_attr *attr,
1254 struct switch_val *val)
1255 {
1256 u32 data;
1257 struct rtl8366_smi *smi = to_rtl8366(dev);
1258
1259 if (val->value.i >= 6)
1260 return -EINVAL;
1261
1262 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1263
1264 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1265 data |= val->value.i;
1266
1267 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1268
1269 return 0;
1270 }
1271
1272 static int rtl8366_set_vlan(struct switch_dev *dev,
1273 const struct switch_attr *attr,
1274 struct switch_val *val)
1275 {
1276 struct rtl8366_smi *smi = to_rtl8366(dev);
1277
1278 if (attr->ofs == 1)
1279 return rtl8366_vlan_set_vlan(smi, val->value.i);
1280 else
1281 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1282 }
1283
1284 static int rtl8366_init_vlan(struct switch_dev *dev,
1285 const struct switch_attr *attr,
1286 struct switch_val *val)
1287 {
1288 struct rtl8366_smi *smi = to_rtl8366(dev);
1289 return rtl8366s_reset_vlan(smi);
1290 }
1291
1292 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1293 const struct switch_attr *attr,
1294 struct switch_val *val)
1295 {
1296 char buf[1024];
1297 u32 len = 0, data = 0;
1298 int speed, duplex, link, txpause, rxpause, nway;
1299 struct rtl8366_smi *smi = to_rtl8366(dev);
1300
1301 if (val->port_vlan >= RTL8366_NUM_PORTS)
1302 return -EINVAL;
1303
1304 memset(buf, '\0', sizeof(buf));
1305 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1306 (val->port_vlan >> 1),
1307 &data);
1308
1309 if (val->port_vlan & 0x1)
1310 data = data >> 8;
1311
1312 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1313 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1314 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1315 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1316 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1317 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1318
1319 len += snprintf(buf + len, sizeof(buf) - len, "Port %d: ",
1320 val->port_vlan);
1321
1322 if (link)
1323 len += snprintf(buf + len, sizeof(buf) - len,
1324 "Link UP, Speed: ");
1325 else
1326 len += snprintf(buf + len, sizeof(buf) - len,
1327 "Link DOWN, Speed: ");
1328
1329 if (speed == 0)
1330 len += snprintf(buf + len, sizeof(buf) - len, "10Base-TX ");
1331 else if (speed == 1)
1332 len += snprintf(buf + len, sizeof(buf) - len, "100Base-TX ");
1333 else if (speed == 2)
1334 len += snprintf(buf + len, sizeof(buf) - len, "1000Base-TX ");
1335
1336 if (duplex)
1337 len += snprintf(buf + len, sizeof(buf) - len, "Full-Duplex, ");
1338 else
1339 len += snprintf(buf + len, sizeof(buf) - len, "Half-Duplex, ");
1340
1341 if (txpause)
1342 len += snprintf(buf + len, sizeof(buf) - len, "TX-Pause ");
1343 if (rxpause)
1344 len += snprintf(buf + len, sizeof(buf) - len, "RX-Pause ");
1345 if (nway)
1346 len += snprintf(buf + len, sizeof(buf) - len, "nway ");
1347
1348 val->value.s = buf;
1349 val->len = len;
1350
1351 return 0;
1352 }
1353
1354 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1355 const struct switch_attr *attr,
1356 struct switch_val *val)
1357 {
1358 int i;
1359 char buf[1024];
1360 u32 len = 0;
1361 struct rtl8366s_vlanconfig vlanMC;
1362 struct rtl8366s_vlan4kentry vlan4K;
1363 struct rtl8366_smi *smi = to_rtl8366(dev);
1364
1365 if (val->port_vlan >= RTL8366_NUM_PORTS)
1366 return -EINVAL;
1367
1368 memset(buf, '\0', sizeof(buf));
1369 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1370 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
1371
1372 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1373 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1374
1375 len += snprintf(buf + len, sizeof(buf) - len, "VLAN %d: Ports: ",
1376 val->port_vlan);
1377
1378 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1379 int index = 0;
1380 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1381 index == val->port_vlan)
1382 len += snprintf(buf + len, sizeof(buf) - len, "%d", i);
1383 }
1384 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1385
1386 len += snprintf(buf + len, sizeof(buf) - len,
1387 "\t\t vid \t prio \t member \t untag \t fid\n");
1388 len += snprintf(buf + len, sizeof(buf) - len, "\tMC:\t");
1389 len += snprintf(buf + len, sizeof(buf) - len,
1390 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1391 vlanMC.vid, vlanMC.priority, vlanMC.member,
1392 vlanMC.untag, vlanMC.fid);
1393 len += snprintf(buf + len, sizeof(buf) - len, "\t4K:\t");
1394 len += snprintf(buf + len, sizeof(buf) - len,
1395 "%d \t \t 0x%04x \t 0x%04x \t %d",
1396 vlan4K.vid, vlan4K.member, vlan4K.untag, vlan4K.fid);
1397
1398 val->value.s = buf;
1399 val->len = len;
1400
1401 return 0;
1402 }
1403
1404 static int rtl8366_set_port_led(struct switch_dev *dev,
1405 const struct switch_attr *attr,
1406 struct switch_val *val)
1407 {
1408 u32 data = 0;
1409 struct rtl8366_smi *smi = to_rtl8366(dev);
1410 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1411 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1412 return -EINVAL;
1413
1414 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1415 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1416 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1417 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1418 } else {
1419 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1420 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1421 (val->value.i << (val->port_vlan * 4));
1422 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1423 }
1424
1425 return 0;
1426 }
1427
1428 static int rtl8366_get_port_led(struct switch_dev *dev,
1429 const struct switch_attr *attr,
1430 struct switch_val *val)
1431 {
1432 u32 data = 0;
1433 struct rtl8366_smi *smi = to_rtl8366(dev);
1434 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1435 return -EINVAL;
1436
1437 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1438 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1439
1440 return 0;
1441 }
1442
1443 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1444 const struct switch_attr *attr,
1445 struct switch_val *val)
1446 {
1447 u32 data = 0;
1448 struct rtl8366_smi *smi = to_rtl8366(dev);
1449 if (val->port_vlan >= RTL8366_NUM_PORTS)
1450 return -EINVAL;
1451
1452 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1453 data |= (1 << (val->port_vlan + 3));
1454 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1455
1456 return 0;
1457 }
1458
1459 static int rtl8366_get_port_mib(struct switch_dev *dev,
1460 const struct switch_attr *attr,
1461 struct switch_val *val)
1462 {
1463 char buf[2048];
1464 int i, len = 0;
1465 unsigned long long counter = 0;
1466 struct rtl8366_smi *smi = to_rtl8366(dev);
1467 if (val->port_vlan >= RTL8366_NUM_PORTS)
1468 return -EINVAL;
1469
1470 len += snprintf(buf + len, sizeof(buf) - len, "Port %d MIB counters\n",
1471 val->port_vlan);
1472 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1473
1474 len += snprintf(buf + len, sizeof(buf) - len,
1475 "%d:%s\t", i, MIBCOUNTERS[i]);
1476 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1477 len += snprintf(buf + len, sizeof(buf) - len,
1478 "[%llu]\n", counter);
1479 else
1480 len += snprintf(buf + len, sizeof(buf) - len,
1481 "[error]\n");
1482 }
1483
1484 val->value.s = buf;
1485 val->len = len;
1486 return 0;
1487 }
1488
1489 static int rtl8366_set_member(struct switch_dev *dev,
1490 const struct switch_attr *attr,
1491 struct switch_val *val)
1492 {
1493 struct rtl8366s_vlanconfig vlanMC;
1494 struct rtl8366s_vlan4kentry vlan4K;
1495 struct rtl8366_smi *smi = to_rtl8366(dev);
1496 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1497 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
1498
1499 if (val->port_vlan >= RTL8366_NUM_VLANS)
1500 return -EINVAL;
1501
1502 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1503
1504 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1505
1506 vlan4K.member = vlanMC.member = val->value.i;
1507 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1508 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1509
1510 return 0;
1511 }
1512
1513 static int rtl8366_get_member(struct switch_dev *dev,
1514 const struct switch_attr *attr,
1515 struct switch_val *val)
1516 {
1517 struct rtl8366s_vlanconfig vlanMC;
1518 struct rtl8366s_vlan4kentry vlan4K;
1519 struct rtl8366_smi *smi = to_rtl8366(dev);
1520 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1521 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
1522
1523 if (val->port_vlan >= RTL8366_NUM_VLANS)
1524 return -EINVAL;
1525
1526 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1527
1528 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1529
1530 val->value.i = vlanMC.member;
1531
1532 return 0;
1533 }
1534
1535 static int rtl8366_set_untag(struct switch_dev *dev,
1536 const struct switch_attr *attr,
1537 struct switch_val *val)
1538 {
1539 struct rtl8366s_vlanconfig vlanMC;
1540 struct rtl8366s_vlan4kentry vlan4K;
1541 struct rtl8366_smi *smi = to_rtl8366(dev);
1542 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1543 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
1544
1545 if (val->port_vlan >= RTL8366_NUM_VLANS)
1546 return -EINVAL;
1547
1548 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1549 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1550
1551 vlan4K.untag = vlanMC.untag = val->value.i;
1552 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1553 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1554
1555 return 0;
1556 }
1557
1558 static int rtl8366_get_untag(struct switch_dev *dev,
1559 const struct switch_attr *attr,
1560 struct switch_val *val)
1561 {
1562 struct rtl8366s_vlanconfig vlanMC;
1563 struct rtl8366s_vlan4kentry vlan4K;
1564 struct rtl8366_smi *smi = to_rtl8366(dev);
1565 memset(&vlanMC, '\0', sizeof(struct rtl8366s_vlanconfig));
1566 memset(&vlan4K, '\0', sizeof(struct rtl8366s_vlan4kentry));
1567
1568 if (val->port_vlan >= RTL8366_NUM_VLANS)
1569 return -EINVAL;
1570
1571 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1572 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1573
1574
1575 val->value.i = vlanMC.untag;
1576
1577 return 0;
1578 }
1579
1580 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1581 {
1582 struct rtl8366_smi *smi = to_rtl8366(dev);
1583 return rtl8366_get_vlan_port_pvid(smi, port, val);
1584 }
1585
1586 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1587 {
1588 struct rtl8366_smi *smi = to_rtl8366(dev);
1589 return rtl8366_set_vlan_port_pvid(smi, port, val);
1590 }
1591
1592 static int rtl8366_reset_switch(struct switch_dev *dev)
1593 {
1594 struct rtl8366_smi *smi = to_rtl8366(dev);
1595 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1596 RTL8366_CHIP_CTRL_RESET_HW);
1597 return 0;
1598 }
1599
1600 static struct switch_attr rtl8366_globals[] = {
1601 {
1602 .type = SWITCH_TYPE_INT,
1603 .name = "enable_vlan",
1604 .description = "Enable VLAN mode",
1605 .set = rtl8366_set_vlan,
1606 .get = rtl8366_get_vlan,
1607 .max = 1,
1608 .ofs = 1
1609 },
1610 {
1611 .type = SWITCH_TYPE_INT,
1612 .name = "enable_vlan4k",
1613 .description = "Enable VLAN 4K mode",
1614 .set = rtl8366_set_vlan,
1615 .get = rtl8366_get_vlan,
1616 .max = 1,
1617 .ofs = 2
1618 },
1619 {
1620 .type = SWITCH_TYPE_INT,
1621 .name = "init_vlan",
1622 .description = "Initialize VLAN tables to defaults",
1623 .set = rtl8366_init_vlan,
1624 .get = NULL,
1625 .max = 1
1626 },
1627
1628 {
1629 .type = SWITCH_TYPE_INT,
1630 .name = "reset_mibs",
1631 .description = "Reset all MIB counters",
1632 .set = rtl8366_global_reset_mibs,
1633 .get = NULL,
1634 .max = 1
1635 },
1636 {
1637 .type = SWITCH_TYPE_INT,
1638 .name = "blinkrate",
1639 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1640 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1641 .set = rtl8366_global_set_blinkrate,
1642 .get = rtl8366_global_get_blinkrate,
1643 .max = 5
1644 },
1645 };
1646
1647 static struct switch_attr rtl8366_port[] = {
1648 {
1649 .type = SWITCH_TYPE_STRING,
1650 .name = "link",
1651 .description = "Get port link information",
1652 .max = 1,
1653 .set = NULL,
1654 .get = rtl8366_attr_get_port_link
1655 },
1656 {
1657 .type = SWITCH_TYPE_INT,
1658 .name = "reset_mib",
1659 .description = "Reset single port MIB counters",
1660 .max = 1,
1661 .set = rtl8366_reset_port_mibs,
1662 .get = NULL
1663 },
1664 {
1665 .type = SWITCH_TYPE_STRING,
1666 .name = "mib",
1667 .description = "Get MIB counters for port",
1668 .max = 33,
1669 .set = NULL,
1670 .get = rtl8366_get_port_mib
1671 },
1672 {
1673 .type = SWITCH_TYPE_INT,
1674 .name = "led",
1675 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1676 .max = 15,
1677 .set = rtl8366_set_port_led,
1678 .get = rtl8366_get_port_led
1679 },
1680 };
1681
1682 static struct switch_attr rtl8366_vlan[] = {
1683 {
1684 .type = SWITCH_TYPE_INT,
1685 .name = "untag",
1686 .description = "Get/Set VLAN untag port set (bitmask)",
1687 .set = rtl8366_set_untag,
1688 .get = rtl8366_get_untag,
1689 .max = 63,
1690 },
1691 {
1692 .type = SWITCH_TYPE_INT,
1693 .name = "member",
1694 .description = "Get/Set VLAN member port set (bitmask)",
1695 .set = rtl8366_set_member,
1696 .get = rtl8366_get_member,
1697 .max = 63,
1698 },
1699 {
1700 .type = SWITCH_TYPE_STRING,
1701 .name = "info",
1702 .description = "Get vlan information",
1703 .max = 1,
1704 .set = NULL,
1705 .get = rtl8366_attr_get_vlan_info
1706 },
1707 };
1708
1709
1710 /* template */
1711 static struct switch_dev rtldev = {
1712 .name = "RTL8366S",
1713 .cpu_port = RTL8366_PORT_NUM_CPU,
1714 .ports = RTL8366_NUM_PORTS,
1715 .vlans = RTL8366_NUM_VLANS,
1716 .attr_global = {
1717 .attr = rtl8366_globals,
1718 .n_attr = ARRAY_SIZE(rtl8366_globals),
1719 },
1720 .attr_port = {
1721 .attr = rtl8366_port,
1722 .n_attr = ARRAY_SIZE(rtl8366_port),
1723 },
1724 .attr_vlan = {
1725 .attr = rtl8366_vlan,
1726 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1727 },
1728
1729 .get_port_pvid = rtl8366_get_port_pvid,
1730 .set_port_pvid = rtl8366_set_port_pvid,
1731 .reset_switch = rtl8366_reset_switch,
1732 };
1733
1734 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1735 {
1736 struct rtl8366_smi *smi = bus->priv;
1737 u32 val = 0;
1738 int err;
1739
1740 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1741 if (err)
1742 return 0xffff;
1743
1744 return val;
1745 }
1746
1747 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1748 u16 val)
1749 {
1750 struct rtl8366_smi *smi = bus->priv;
1751 u32 t;
1752 int err;
1753
1754 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1755 /* flush write */
1756 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1757
1758 return err;
1759 }
1760
1761 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1762 {
1763 int ret;
1764 int i;
1765
1766 smi->mii_bus = mdiobus_alloc();
1767 if (smi->mii_bus == NULL) {
1768 ret = -ENOMEM;
1769 goto err;
1770 }
1771
1772 spin_lock_init(&smi->lock);
1773 smi->mii_bus->priv = (void *) smi;
1774 smi->mii_bus->name = "rtl8366-smi";
1775 smi->mii_bus->read = rtl8366_smi_mii_read;
1776 smi->mii_bus->write = rtl8366_smi_mii_write;
1777 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1778 dev_name(&smi->pdev->dev));
1779 smi->mii_bus->parent = &smi->pdev->dev;
1780 smi->mii_bus->phy_mask = ~(0x1f);
1781 smi->mii_bus->irq = smi->mii_irq;
1782 for (i = 0; i < PHY_MAX_ADDR; i++)
1783 smi->mii_irq[i] = PHY_POLL;
1784
1785 ret = mdiobus_register(smi->mii_bus);
1786 if (ret)
1787 goto err_free;
1788
1789 return 0;
1790
1791 err_free:
1792 mdiobus_free(smi->mii_bus);
1793 err:
1794 return ret;
1795 }
1796
1797 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1798 {
1799 mdiobus_unregister(smi->mii_bus);
1800 mdiobus_free(smi->mii_bus);
1801 }
1802
1803 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1804 {
1805 u32 chip_id = 0;
1806 u32 chip_ver = 0;
1807 int ret;
1808
1809 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1810 if (ret) {
1811 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1812 return ret;
1813 }
1814
1815 switch (chip_id) {
1816 case RTL8366S_CHIP_ID_8366:
1817 break;
1818 default:
1819 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1820 return -ENODEV;
1821 }
1822
1823 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1824 &chip_ver);
1825 if (ret) {
1826 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1827 return ret;
1828 }
1829
1830 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1831 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1832
1833 rtl8366_debugfs_init(smi);
1834
1835 return 0;
1836 }
1837
1838 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1839 {
1840 static int rtl8366_smi_version_printed;
1841 struct rtl8366_smi_platform_data *pdata;
1842 struct rtl8366_smi *smi;
1843 int err;
1844
1845 if (!rtl8366_smi_version_printed++)
1846 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1847 " version " RTL8366_SMI_DRIVER_VER"\n");
1848
1849 pdata = pdev->dev.platform_data;
1850 if (!pdata) {
1851 dev_err(&pdev->dev, "no platform data specified\n");
1852 err = -EINVAL;
1853 goto err_out;
1854 }
1855
1856 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1857 if (!smi) {
1858 dev_err(&pdev->dev, "no memory for private data\n");
1859 err = -ENOMEM;
1860 goto err_out;
1861 }
1862
1863 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1864 if (err) {
1865 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1866 pdata->gpio_sda, err);
1867 goto err_free_smi;
1868 }
1869
1870 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1871 if (err) {
1872 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1873 pdata->gpio_sck, err);
1874 goto err_free_sda;
1875 }
1876
1877 smi->pdev = pdev;
1878 smi->pdata = pdata;
1879 spin_lock_init(&smi->lock);
1880
1881 platform_set_drvdata(pdev, smi);
1882
1883 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1884 pdata->gpio_sda, pdata->gpio_sck);
1885
1886 err = rtl8366_smi_setup(smi);
1887 if (err)
1888 goto err_clear_drvdata;
1889
1890 err = rtl8366_smi_mii_init(smi);
1891 if (err)
1892 goto err_clear_drvdata;
1893
1894 return 0;
1895
1896 err_clear_drvdata:
1897 platform_set_drvdata(pdev, NULL);
1898 gpio_free(pdata->gpio_sck);
1899 err_free_sda:
1900 gpio_free(pdata->gpio_sda);
1901 err_free_smi:
1902 kfree(smi);
1903 err_out:
1904 return err;
1905 }
1906
1907 int rtl8366_phy_config_init(struct phy_device *phydev)
1908 {
1909 int err;
1910 struct net_device *netdev = phydev->attached_dev;
1911 struct rtl8366_smi *smi = phydev->bus->priv;
1912 struct switch_dev *dev = &smi->dev;
1913
1914 /* Only init the switch for the primary PHY */
1915 if (phydev->addr != 4) {
1916 printk(KERN_INFO "Discarding address: %d\n", phydev->addr);
1917 return 0;
1918 }
1919
1920 memcpy(&smi->dev, &rtldev, sizeof(struct switch_dev));
1921 dev->priv = smi;
1922 dev->netdev = netdev;
1923
1924 err = register_switch(dev, netdev);
1925 if (err < 0) {
1926 printk(KERN_INFO "Switch registration failed\n");
1927 return err;
1928 }
1929
1930 return 0;
1931 }
1932
1933 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1934 {
1935 return 0;
1936 }
1937
1938 static struct phy_driver rtl8366_smi_phy_driver = {
1939 .phy_id = 0x001cc960,
1940 .name = "Realtek RTL8366",
1941 .phy_id_mask = 0x1ffffff0,
1942 .features = PHY_GBIT_FEATURES,
1943 .config_aneg = rtl8366_phy_config_aneg,
1944 .config_init = rtl8366_phy_config_init,
1945 .read_status = genphy_read_status,
1946 .driver = {
1947 .owner = THIS_MODULE,
1948 },
1949 };
1950
1951 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1952 {
1953 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1954
1955 if (smi) {
1956 struct rtl8366_smi_platform_data *pdata;
1957
1958 pdata = pdev->dev.platform_data;
1959
1960 rtl8366_debugfs_remove(smi);
1961 phy_driver_unregister(&rtl8366_smi_phy_driver);
1962 rtl8366_smi_mii_cleanup(smi);
1963 platform_set_drvdata(pdev, NULL);
1964 gpio_free(pdata->gpio_sck);
1965 gpio_free(pdata->gpio_sda);
1966 kfree(smi);
1967 }
1968
1969 return 0;
1970 }
1971
1972 static struct platform_driver rtl8366_smi_driver = {
1973 .driver = {
1974 .name = RTL8366_SMI_DRIVER_NAME,
1975 .owner = THIS_MODULE,
1976 },
1977 .probe = rtl8366_smi_probe,
1978 .remove = __devexit_p(rtl8366_smi_remove),
1979 };
1980
1981 static int __init rtl8366_smi_init(void)
1982 {
1983 int ret;
1984 ret = platform_driver_register(&rtl8366_smi_driver);
1985 if (ret)
1986 return ret;
1987
1988 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1989 if (ret)
1990 goto err_platform_unregister;
1991
1992 return 0;
1993
1994 err_platform_unregister:
1995 platform_driver_unregister(&rtl8366_smi_driver);
1996 return ret;
1997 }
1998 module_init(rtl8366_smi_init);
1999
2000 static void __exit rtl8366_smi_exit(void)
2001 {
2002 phy_driver_unregister(&rtl8366_smi_phy_driver);
2003 platform_driver_unregister(&rtl8366_smi_driver);
2004 }
2005 module_exit(rtl8366_smi_exit);
2006
2007 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
2008 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
2009 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2010 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2011 MODULE_LICENSE("GPL v2");
2012 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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