target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch

   1 --- a/arch/mips/ath79/clock.c
   2 +++ b/arch/mips/ath79/clock.c
   3 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
   4         clk_add_alias("uart", NULL, "ref", NULL);
   5  }
   6
   7 +static void __init qca956x_clocks_init(void)
   8 +{
   9 +       unsigned long ref_rate;
  10 +       unsigned long cpu_rate;
  11 +       unsigned long ddr_rate;
  12 +       unsigned long ahb_rate;
  13 +       u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
  14 +       u32 cpu_pll, ddr_pll;
  15 +       u32 bootstrap;
  16 +
  17 +       bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  18 +       if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  19 +               ref_rate = 40 * 1000 * 1000;
  20 +       else
  21 +               ref_rate = 25 * 1000 * 1000;
  22 +
  23 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
  24 +       out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  25 +                 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  26 +       ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  27 +                 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  28 +
  29 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
  30 +       nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  31 +              QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  32 +       hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  33 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  34 +       lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  35 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  36 +
  37 +       cpu_pll = nint * ref_rate / ref_div;
  38 +       cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  39 +       cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  40 +       cpu_pll /= (1 << out_div);
  41 +
  42 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
  43 +       out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  44 +                 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  45 +       ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  46 +                 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  47 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
  48 +       nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  49 +              QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  50 +       hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  51 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  52 +       lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  53 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  54 +
  55 +       ddr_pll = nint * ref_rate / ref_div;
  56 +       ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  57 +       ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  58 +       ddr_pll /= (1 << out_div);
  59 +
  60 +       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
  61 +
  62 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  63 +                 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  64 +
  65 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  66 +               cpu_rate = ref_rate;
  67 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
  68 +               cpu_rate = ddr_pll / (postdiv + 1);
  69 +       else
  70 +               cpu_rate = cpu_pll / (postdiv + 1);
  71 +
  72 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  73 +                 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  74 +
  75 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  76 +               ddr_rate = ref_rate;
  77 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
  78 +               ddr_rate = cpu_pll / (postdiv + 1);
  79 +       else
  80 +               ddr_rate = ddr_pll / (postdiv + 1);
  81 +
  82 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  83 +                 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  84 +
  85 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  86 +               ahb_rate = ref_rate;
  87 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  88 +               ahb_rate = ddr_pll / (postdiv + 1);
  89 +       else
  90 +               ahb_rate = cpu_pll / (postdiv + 1);
  91 +
  92 +       ath79_add_sys_clkdev("ref", ref_rate);
  93 +       ath79_add_sys_clkdev("cpu", cpu_rate);
  94 +       ath79_add_sys_clkdev("ddr", ddr_rate);
  95 +       ath79_add_sys_clkdev("ahb", ahb_rate);
  96 +
  97 +       clk_add_alias("wdt", NULL, "ref", NULL);
  98 +       clk_add_alias("uart", NULL, "ref", NULL);
  99 +}
 100 +
 101  void __init ath79_clocks_init(void)
 102  {
 103         if (soc_is_ar71xx())
 104 @@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
 105                 qca953x_clocks_init();
 106         else if (soc_is_qca955x())
 107                 qca955x_clocks_init();
 108 +       else if (soc_is_qca956x())
 109 +               qca956x_clocks_init();
 110         else
 111                 BUG();
 112  }
 113 --- a/arch/mips/ath79/common.c
 114 +++ b/arch/mips/ath79/common.c
 115 @@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
 116                 reg = QCA953X_RESET_REG_RESET_MODULE;
 117         else if (soc_is_qca955x())
 118                 reg = QCA955X_RESET_REG_RESET_MODULE;
 119 +       else if (soc_is_qca956x())
 120 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 121         else
 122                 panic("Reset register not defined for this SOC");
 123
 124 @@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
 125                 reg = QCA953X_RESET_REG_RESET_MODULE;
 126         else if (soc_is_qca955x())
 127                 reg = QCA955X_RESET_REG_RESET_MODULE;
 128 +       else if (soc_is_qca956x())
 129 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 130         else
 131                 panic("Reset register not defined for this SOC");
 132
 133 --- a/arch/mips/ath79/dev-common.c
 134 +++ b/arch/mips/ath79/dev-common.c
 135 @@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
 136             soc_is_ar913x() ||
 137             soc_is_ar934x() ||
 138             soc_is_qca953x() ||
 139 -           soc_is_qca955x()) {
 140 +           soc_is_qca955x() ||
 141 +           soc_is_qca956x()) {
 142                 ath79_uart_data[0].uartclk = uart_clk_rate;
 143                 platform_device_register(&ath79_uart_device);
 144         } else if (soc_is_ar933x()) {
 145 --- a/arch/mips/ath79/dev-usb.c
 146 +++ b/arch/mips/ath79/dev-usb.c
 147 @@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
 148                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 149  }
 150
 151 +static void __init qca956x_usb_setup(void)
 152 +{
 153 +       ath79_usb_register("ehci-platform", 0,
 154 +                          QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
 155 +                          ATH79_IP3_IRQ(0),
 156 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 157 +
 158 +       ath79_usb_register("ehci-platform", 1,
 159 +                          QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
 160 +                          ATH79_IP3_IRQ(1),
 161 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 162 +}
 163 +
 164  void __init ath79_register_usb(void)
 165  {
 166         if (soc_is_ar71xx())
 167 @@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
 168                 qca953x_usb_setup();
 169         else if (soc_is_qca955x())
 170                 qca955x_usb_setup();
 171 +       else if (soc_is_qca9561())
 172 +               qca956x_usb_setup();
 173         else
 174                 BUG();
 175  }
 176 --- a/arch/mips/ath79/dev-wmac.c
 177 +++ b/arch/mips/ath79/dev-wmac.c
 178 @@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
 179                 ath79_wmac_data.is_clk_25mhz = true;
 180  }
 181
 182 +static void qca956x_wmac_setup(void)
 183 +{
 184 +       u32 t;
 185 +
 186 +       ath79_wmac_device.name = "qca956x_wmac";
 187 +
 188 +       ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
 189 +       ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
 190 +       ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
 191 +       ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
 192 +
 193 +       t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
 194 +       if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
 195 +               ath79_wmac_data.is_clk_25mhz = false;
 196 +       else
 197 +               ath79_wmac_data.is_clk_25mhz = true;
 198 +}
 199 +
 200  static bool __init
 201  ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
 202  {
 203 @@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
 204                 qca953x_wmac_setup();
 205         else if (soc_is_qca955x())
 206                 qca955x_wmac_setup();
 207 +       else if (soc_is_qca956x())
 208 +               qca956x_wmac_setup();
 209         else
 210                 BUG();
 211
 212 --- a/arch/mips/ath79/early_printk.c
 213 +++ b/arch/mips/ath79/early_printk.c
 214 @@ -120,6 +120,8 @@ static void prom_putchar_init(void)
 215         case REV_ID_MAJOR_QCA9533_V2:
 216         case REV_ID_MAJOR_QCA9556:
 217         case REV_ID_MAJOR_QCA9558:
 218 +       case REV_ID_MAJOR_TP9343:
 219 +       case REV_ID_MAJOR_QCA9561:
 220                 _prom_putchar = prom_putchar_ar71xx;
 221                 break;
 222
 223 --- a/arch/mips/ath79/gpio.c
 224 +++ b/arch/mips/ath79/gpio.c
 225 @@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
 226             soc_is_ar913x() ||
 227             soc_is_ar933x())
 228                 reg = AR71XX_GPIO_REG_FUNC;
 229 -       else if (soc_is_ar934x() || soc_is_qca953x())
 230 +       else if (soc_is_ar934x() ||
 231 +                soc_is_qca953x() || soc_is_qca956x())
 232                 reg = AR934X_GPIO_REG_FUNC;
 233         else
 234                 BUG();
 235 @@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
 236                 ath79_gpio_count = QCA953X_GPIO_COUNT;
 237         else if (soc_is_qca955x())
 238                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 239 +       else if (soc_is_qca956x())
 240 +               ath79_gpio_count = QCA956X_GPIO_COUNT;
 241         else
 242                 BUG();
 243
 244         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 245         ath79_gpio_chip.ngpio = ath79_gpio_count;
 246 -       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 247 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
 248 +           soc_is_qca956x()) {
 249                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 250                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 251         }
 252 --- a/arch/mips/ath79/irq.c
 253 +++ b/arch/mips/ath79/irq.c
 254 @@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
 255                  soc_is_ar933x() ||
 256                  soc_is_ar934x() ||
 257                  soc_is_qca953x() ||
 258 -                soc_is_qca955x())
 259 +                soc_is_qca955x() ||
 260 +                soc_is_qca956x())
 261                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 262         else
 263                 BUG();
 264 @@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
 265         irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 266  }
 267
 268 +static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 269 +{
 270 +       u32 status;
 271 +
 272 +       disable_irq_nosync(irq);
 273 +
 274 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 275 +       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 276 +
 277 +       if (status == 0) {
 278 +               spurious_interrupt();
 279 +               goto enable;
 280 +       }
 281 +
 282 +       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 283 +               /* TODO: flush DDR? */
 284 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 285 +       }
 286 +
 287 +       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 288 +               /* TODO: flsuh DDR? */
 289 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 290 +       }
 291 +
 292 +enable:
 293 +       enable_irq(irq);
 294 +}
 295 +
 296 +static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 297 +{
 298 +       u32 status;
 299 +
 300 +       disable_irq_nosync(irq);
 301 +
 302 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 303 +       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 304 +                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 305 +
 306 +       if (status == 0) {
 307 +               spurious_interrupt();
 308 +               goto enable;
 309 +       }
 310 +
 311 +       if (status & QCA956X_EXT_INT_USB1) {
 312 +               /* TODO: flush DDR? */
 313 +               generic_handle_irq(ATH79_IP3_IRQ(0));
 314 +       }
 315 +
 316 +       if (status & QCA956X_EXT_INT_USB2) {
 317 +               /* TODO: flush DDR? */
 318 +               generic_handle_irq(ATH79_IP3_IRQ(1));
 319 +       }
 320 +
 321 +       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 322 +               /* TODO: flush DDR? */
 323 +               generic_handle_irq(ATH79_IP3_IRQ(2));
 324 +       }
 325 +
 326 +enable:
 327 +       enable_irq(irq);
 328 +}
 329 +
 330 +static void qca956x_enable_timer_cb(void) {
 331 +       u32 misc;
 332 +
 333 +       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 334 +       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 335 +       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 336 +}
 337 +
 338 +static void qca956x_irq_init(void)
 339 +{
 340 +       int i;
 341 +
 342 +       for (i = ATH79_IP2_IRQ_BASE;
 343 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 344 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 345 +
 346 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 347 +
 348 +       for (i = ATH79_IP3_IRQ_BASE;
 349 +            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 350 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 351 +
 352 +       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 353 +
 354 +       /* QCA956x timer init workaround has to be applied right before setting
 355 +        * up the clock. Else, there will be no jiffies */
 356 +       late_time_init = &qca956x_enable_timer_cb;
 357 +}
 358 +
 359  asmlinkage void plat_irq_dispatch(void)
 360  {
 361         unsigned long pending;
 362 @@ -397,6 +489,9 @@ void __init arch_init_irq(void)
 363         } else if (soc_is_qca955x()) {
 364                 ath79_ip2_handler = ath79_default_ip2_handler;
 365                 ath79_ip3_handler = ath79_default_ip3_handler;
 366 +       } else if (soc_is_qca956x()) {
 367 +               ath79_ip2_handler = ath79_default_ip2_handler;
 368 +               ath79_ip3_handler = ath79_default_ip3_handler;
 369         } else {
 370                 BUG();
 371         }
 372 @@ -411,4 +506,6 @@ void __init arch_init_irq(void)
 373                 qca953x_irq_init();
 374         else if (soc_is_qca955x())
 375                 qca955x_irq_init();
 376 +       else if (soc_is_qca956x())
 377 +               qca956x_irq_init();
 378  }
 379 --- a/arch/mips/ath79/Kconfig
 380 +++ b/arch/mips/ath79/Kconfig
 381 @@ -1286,6 +1286,12 @@ config SOC_QCA955X
 382         select PCI_AR724X if PCI
 383         def_bool n
 384
 385 +config SOC_QCA956X
 386 +       select USB_ARCH_HAS_EHCI
 387 +       select HW_HAS_PCI
 388 +       select PCI_AR724X if PCI
 389 +       def_bool n
 390 +
 391  config ATH79_DEV_M25P80
 392         select ATH79_DEV_SPI
 393         def_bool n
 394 @@ -1323,7 +1329,7 @@ config ATH79_DEV_USB
 395         def_bool n
 396
 397  config ATH79_DEV_WMAC
 398 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
 399 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
 400         def_bool n
 401
 402  config ATH79_NVRAM
 403 --- a/arch/mips/ath79/pci.c
 404 +++ b/arch/mips/ath79/pci.c
 405 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
 406         },
 407  };
 408
 409 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
 410 +       {
 411 +               .bus    = 0,
 412 +               .slot   = 0,
 413 +               .pin    = 1,
 414 +               .irq    = ATH79_PCI_IRQ(0),
 415 +       },
 416 +       {
 417 +               .bus    = 1,
 418 +               .slot   = 0,
 419 +               .pin    = 1,
 420 +               .irq    = ATH79_PCI_IRQ(1),
 421 +       },
 422 +};
 423 +
 424  int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 425  {
 426         int irq = -1;
 427 @@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
 428                 } else if (soc_is_qca955x()) {
 429                         ath79_pci_irq_map = qca955x_pci_irq_map;
 430                         ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
 431 +               } else if (soc_is_qca9561()) {
 432 +                       ath79_pci_irq_map = qca956x_pci_irq_map;
 433 +                       ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
 434                 } else {
 435                         pr_crit("pci %s: invalid irq map\n",
 436                                 pci_name((struct pci_dev *) dev));
 437 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
 438                                                  QCA955X_PCI_MEM_SIZE,
 439                                                  1,
 440                                                  ATH79_IP3_IRQ(2));
 441 +       } else if (soc_is_qca9561()) {
 442 +               pdev = ath79_register_pci_ar724x(0,
 443 +                                                QCA956X_PCI_CFG_BASE1,
 444 +                                                QCA956X_PCI_CTRL_BASE1,
 445 +                                                QCA956X_PCI_CRP_BASE1,
 446 +                                                QCA956X_PCI_MEM_BASE1,
 447 +                                                QCA956X_PCI_MEM_SIZE,
 448 +                                                1,
 449 +                                                ATH79_IP3_IRQ(2));
 450         } else {
 451                 /* No PCI support */
 452                 return -ENODEV;
 453 --- a/arch/mips/ath79/setup.c
 454 +++ b/arch/mips/ath79/setup.c
 455 @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
 456                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 457                 break;
 458
 459 +       case REV_ID_MAJOR_TP9343:
 460 +               ath79_soc = ATH79_SOC_TP9343;
 461 +               chip = "9343";
 462 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 463 +               break;
 464 +
 465 +       case REV_ID_MAJOR_QCA9561:
 466 +               ath79_soc = ATH79_SOC_QCA9561;
 467 +               chip = "9561";
 468 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 469 +               break;
 470 +
 471         default:
 472                 panic("ath79: unknown SoC, id:0x%08x", id);
 473         }
 474 @@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
 475         if (ver == 1)
 476                 ath79_soc_rev = rev;
 477
 478 -       if (soc_is_qca953x() || soc_is_qca955x())
 479 +       if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
 480                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 481                         chip, ver, rev);
 482 +       else if (soc_is_tp9343())
 483 +               sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
 484 +                       chip, rev);
 485         else
 486                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 487         pr_info("SoC: %s\n", ath79_sys_type);
 488 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 489 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 490 @@ -143,6 +143,23 @@
 491  #define QCA955X_NFC_BASE       0x1b800200
 492  #define QCA955X_NFC_SIZE       0xb8
 493
 494 +#define QCA956X_PCI_MEM_BASE1  0x12000000
 495 +#define QCA956X_PCI_MEM_SIZE   0x02000000
 496 +#define QCA956X_PCI_CFG_BASE1  0x16000000
 497 +#define QCA956X_PCI_CFG_SIZE   0x1000
 498 +#define QCA956X_PCI_CRP_BASE1  (AR71XX_APB_BASE + 0x00250000)
 499 +#define QCA956X_PCI_CRP_SIZE   0x1000
 500 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
 501 +#define QCA956X_PCI_CTRL_SIZE  0x100
 502 +
 503 +#define QCA956X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 504 +#define QCA956X_WMAC_SIZE      0x20000
 505 +#define QCA956X_EHCI0_BASE     0x1b000000
 506 +#define QCA956X_EHCI1_BASE     0x1b400000
 507 +#define QCA956X_EHCI_SIZE      0x200
 508 +#define QCA956X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
 509 +#define QCA956X_GMAC_SIZE      0x64
 510 +
 511  #define AR9300_OTP_BASE                0x14000
 512  #define AR9300_OTP_STATUS      0x15f18
 513  #define AR9300_OTP_STATUS_TYPE         0x7
 514 @@ -375,6 +392,49 @@
 515  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 516  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 517
 518 +#define QCA956X_PLL_CPU_CONFIG_REG                     0x00
 519 +#define QCA956X_PLL_CPU_CONFIG1_REG                    0x04
 520 +#define QCA956X_PLL_DDR_CONFIG_REG                     0x08
 521 +#define QCA956X_PLL_DDR_CONFIG1_REG                    0x0c
 522 +#define QCA956X_PLL_CLK_CTRL_REG                       0x10
 523 +
 524 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT            12
 525 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK             0x1f
 526 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT            19
 527 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK             0x7
 528 +
 529 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT          0
 530 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK           0x1f
 531 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT          5
 532 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK           0x3fff
 533 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT             18
 534 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK              0x1ff
 535 +
 536 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT            16
 537 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK             0x1f
 538 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT            23
 539 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK             0x7
 540 +
 541 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT          0
 542 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK           0x1f
 543 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT          5
 544 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK           0x3fff
 545 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT             18
 546 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK              0x1ff
 547 +
 548 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 549 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 550 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 551 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 552 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 553 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 554 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 555 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 556 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 557 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL    BIT(20)
 558 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL    BIT(21)
 559 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 560 +
 561  /*
 562   * USB_CONFIG block
 563   */
 564 @@ -422,6 +482,11 @@
 565  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 566  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 567
 568 +#define QCA956X_RESET_REG_RESET_MODULE         0x1c
 569 +#define QCA956X_RESET_REG_BOOTSTRAP            0xb0
 570 +#define QCA956X_RESET_REG_EXT_INT_STATUS       0xac
 571 +
 572 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
 573  #define MISC_INT_ETHSW                 BIT(12)
 574  #define MISC_INT_TIMER4                        BIT(10)
 575  #define MISC_INT_TIMER3                        BIT(9)
 576 @@ -596,6 +661,8 @@
 577
 578  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 579
 580 +#define QCA956X_BOOTSTRAP_REF_CLK_40   BIT(2)
 581 +
 582  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 583  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
 584  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
 585 @@ -663,6 +730,37 @@
 586          QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
 587          QCA955X_EXT_INT_PCIE_RC2_INT3)
 588
 589 +#define QCA956X_EXT_INT_WMAC_MISC              BIT(0)
 590 +#define QCA956X_EXT_INT_WMAC_TX                        BIT(1)
 591 +#define QCA956X_EXT_INT_WMAC_RXLP              BIT(2)
 592 +#define QCA956X_EXT_INT_WMAC_RXHP              BIT(3)
 593 +#define QCA956X_EXT_INT_PCIE_RC1               BIT(4)
 594 +#define QCA956X_EXT_INT_PCIE_RC1_INT0          BIT(5)
 595 +#define QCA956X_EXT_INT_PCIE_RC1_INT1          BIT(6)
 596 +#define QCA956X_EXT_INT_PCIE_RC1_INT2          BIT(7)
 597 +#define QCA956X_EXT_INT_PCIE_RC1_INT3          BIT(8)
 598 +#define QCA956X_EXT_INT_PCIE_RC2               BIT(12)
 599 +#define QCA956X_EXT_INT_PCIE_RC2_INT0          BIT(13)
 600 +#define QCA956X_EXT_INT_PCIE_RC2_INT1          BIT(14)
 601 +#define QCA956X_EXT_INT_PCIE_RC2_INT2          BIT(15)
 602 +#define QCA956X_EXT_INT_PCIE_RC2_INT3          BIT(16)
 603 +#define QCA956X_EXT_INT_USB1                   BIT(24)
 604 +#define QCA956X_EXT_INT_USB2                   BIT(28)
 605 +
 606 +#define QCA956X_EXT_INT_WMAC_ALL \
 607 +       (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
 608 +        QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
 609 +
 610 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
 611 +       (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
 612 +        QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
 613 +        QCA956X_EXT_INT_PCIE_RC1_INT3)
 614 +
 615 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
 616 +       (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
 617 +        QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
 618 +        QCA956X_EXT_INT_PCIE_RC2_INT3)
 619 +
 620  #define REV_ID_MAJOR_MASK              0xfff0
 621  #define REV_ID_MAJOR_AR71XX            0x00a0
 622  #define REV_ID_MAJOR_AR913X            0x00b0
 623 @@ -678,6 +776,8 @@
 624  #define REV_ID_MAJOR_QCA9533_V2                0x0160
 625  #define REV_ID_MAJOR_QCA9556           0x0130
 626  #define REV_ID_MAJOR_QCA9558           0x1130
 627 +#define REV_ID_MAJOR_TP9343            0x0150
 628 +#define REV_ID_MAJOR_QCA9561           0x1150
 629
 630  #define AR71XX_REV_ID_MINOR_MASK       0x3
 631  #define AR71XX_REV_ID_MINOR_AR7130     0x0
 632 @@ -702,6 +802,8 @@
 633
 634  #define QCA955X_REV_ID_REVISION_MASK   0xf
 635
 636 +#define QCA956X_REV_ID_REVISION_MASK   0xf
 637 +
 638  /*
 639   * SPI block
 640   */
 641 @@ -766,6 +868,19 @@
 642  #define QCA953X_GPIO_OUT_MUX_LED_LINK4         44
 643  #define QCA953X_GPIO_OUT_MUX_LED_LINK5         45
 644
 645 +#define QCA956X_GPIO_REG_OUT_FUNC0     0x2c
 646 +#define QCA956X_GPIO_REG_OUT_FUNC1     0x30
 647 +#define QCA956X_GPIO_REG_OUT_FUNC2     0x34
 648 +#define QCA956X_GPIO_REG_OUT_FUNC3     0x38
 649 +#define QCA956X_GPIO_REG_OUT_FUNC4     0x3c
 650 +#define QCA956X_GPIO_REG_OUT_FUNC5     0x40
 651 +#define QCA956X_GPIO_REG_IN_ENABLE0    0x44
 652 +#define QCA956X_GPIO_REG_IN_ENABLE3    0x50
 653 +#define QCA956X_GPIO_REG_FUNC          0x6c
 654 +
 655 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO   32
 656 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC   33
 657 +
 658  #define AR71XX_GPIO_COUNT              16
 659  #define AR7240_GPIO_COUNT              18
 660  #define AR7241_GPIO_COUNT              20
 661 @@ -774,6 +889,7 @@
 662  #define AR934X_GPIO_COUNT              23
 663  #define QCA953X_GPIO_COUNT             18
 664  #define QCA955X_GPIO_COUNT             24
 665 +#define QCA956X_GPIO_COUNT             23
 666
 667  /*
 668   * SRIF block
 669 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 670 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 671 @@ -35,6 +35,8 @@ enum ath79_soc_type {
 672         ATH79_SOC_QCA9533,
 673         ATH79_SOC_QCA9556,
 674         ATH79_SOC_QCA9558,
 675 +       ATH79_SOC_TP9343,
 676 +       ATH79_SOC_QCA9561,
 677  };
 678
 679  extern enum ath79_soc_type ath79_soc;
 680 @@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
 681         return soc_is_qca9556() || soc_is_qca9558();
 682  }
 683
 684 +static inline int soc_is_tp9343(void)
 685 +{
 686 +       return ath79_soc == ATH79_SOC_TP9343;
 687 +}
 688 +
 689 +static inline int soc_is_qca9561(void)
 690 +{
 691 +       return ath79_soc == ATH79_SOC_QCA9561;
 692 +}
 693 +
 694 +static inline int soc_is_qca956x(void)
 695 +{
 696 +       return soc_is_tp9343() || soc_is_qca9561();
 697 +}
 698 +
 699  extern void __iomem *ath79_ddr_base;
 700  extern void __iomem *ath79_gpio_base;
 701  extern void __iomem *ath79_pll_base;