1 --- a/arch/mips/ath79/mach-ap136.c
2 +++ b/arch/mips/ath79/mach-ap136.c
5 - * Qualcomm Atheros AP136 reference board support
6 + * Atheros AP136 reference board support
8 * Copyright (c) 2012 Qualcomm Atheros
9 * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
14 -#include <linux/pci.h>
15 -#include <linux/ath9k_platform.h>
16 +#include <linux/platform_device.h>
17 +#include <linux/ar8216_platform.h>
19 -#include "machtypes.h"
20 +#include <asm/mach-ath79/ar71xx_regs.h>
23 +#include "dev-ap9x-pci.h"
24 #include "dev-gpio-buttons.h"
26 #include "dev-leds-gpio.h"
28 +#include "dev-m25p80.h"
32 +#include "machtypes.h"
34 -#define AP136_GPIO_LED_STATUS_RED 14
35 -#define AP136_GPIO_LED_STATUS_GREEN 19
36 #define AP136_GPIO_LED_USB 4
37 -#define AP136_GPIO_LED_WLAN_2G 13
38 #define AP136_GPIO_LED_WLAN_5G 12
39 +#define AP136_GPIO_LED_WLAN_2G 13
40 +#define AP136_GPIO_LED_STATUS_RED 14
41 #define AP136_GPIO_LED_WPS_RED 15
42 +#define AP136_GPIO_LED_STATUS_GREEN 19
43 #define AP136_GPIO_LED_WPS_GREEN 20
45 #define AP136_GPIO_BTN_WPS 16
47 #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
48 #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
50 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
51 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
52 +#define AP136_MAC0_OFFSET 0
53 +#define AP136_MAC1_OFFSET 6
54 +#define AP136_WMAC_CALDATA_OFFSET 0x1000
55 +#define AP136_PCIE_CALDATA_OFFSET 0x5000
57 static struct gpio_led ap136_leds_gpio[] __initdata = {
59 @@ -98,63 +104,103 @@ static struct gpio_keys_button ap136_gpi
63 -static struct ath79_spi_controller_data ap136_spi0_data = {
64 - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
66 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
67 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
69 +static struct ar8327_platform_data ap136_ar8327_data = {
70 + .pad0_cfg = &ap136_ar8327_pad0_cfg,
71 + .pad6_cfg = &ap136_ar8327_pad6_cfg,
74 + .speed = AR8327_PORT_SPEED_1000,
81 + .speed = AR8327_PORT_SPEED_1000,
88 -static struct spi_board_info ap136_spi_info[] = {
89 +static struct mdio_board_info ap136_mdio0_info[] = {
93 - .max_speed_hz = 25000000,
94 - .modalias = "mx25l6405d",
95 - .controller_data = &ap136_spi0_data,
97 + .bus_id = "ag71xx-mdio.0",
99 + .platform_data = &ap136_ar8327_data,
103 -static struct ath79_spi_platform_data ap136_spi_data = {
105 - .num_chipselect = 1,
107 +static void __init ap136_gmac_setup(void)
109 + void __iomem *base;
113 -static struct ath9k_platform_data ap136_ath9k_data;
114 + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
116 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
118 - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
119 - dev->dev.platform_data = &ap136_ath9k_data;
120 + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
124 + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
125 + t |= QCA955X_ETH_CFG_RGMII_EN;
127 -static void __init ap136_pci_init(u8 *eeprom)
129 - memcpy(ap136_ath9k_data.eeprom_data, eeprom,
130 - sizeof(ap136_ath9k_data.eeprom_data));
131 + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
133 - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
134 - ath79_register_pci();
138 -static inline void ap136_pci_init(void) {}
139 -#endif /* CONFIG_PCI */
141 static void __init ap136_setup(void)
143 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
145 + ath79_register_m25p80(NULL);
147 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
149 ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
150 ARRAY_SIZE(ap136_gpio_keys),
152 - ath79_register_spi(&ap136_spi_data, ap136_spi_info,
153 - ARRAY_SIZE(ap136_spi_info));
155 ath79_register_usb();
156 - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
157 - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
158 + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
159 + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
161 + ap136_gmac_setup();
163 + ath79_register_mdio(0, 0x0);
165 + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
167 + mdiobus_register_board_info(ap136_mdio0_info,
168 + ARRAY_SIZE(ap136_mdio0_info));
170 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
171 + ap136_ar8327_pad0_cfg.txclk_delay_en = true;
172 + ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
173 + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
174 + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
176 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
177 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
178 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
180 + /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
181 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
182 + ath79_eth0_data.phy_mask = BIT(0);
183 + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
184 + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
186 + ath79_register_eth(0);
188 + /* GMAC1 is connected to GMAC6 of the AR8327 switch via SGMII */
189 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
190 + ath79_eth1_data.speed = SPEED_1000;
191 + ath79_eth1_data.duplex = DUPLEX_FULL;
192 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
194 + ath79_register_eth(1);
197 MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",