target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -21,6 +21,10 @@
   4  #include <linux/bitops.h>
   5
   6  #define AR71XX_APB_BASE                0x18000000
   7 +#define AR71XX_GE0_BASE                0x19000000
   8 +#define AR71XX_GE0_SIZE                0x10000
   9 +#define AR71XX_GE1_BASE                0x1a000000
  10 +#define AR71XX_GE1_SIZE                0x10000
  11  #define AR71XX_EHCI_BASE       0x1b000000
  12  #define AR71XX_EHCI_SIZE       0x1000
  13  #define AR71XX_OHCI_BASE       0x1c000000
  14 @@ -40,6 +44,8 @@
  15  #define AR71XX_PLL_SIZE                0x100
  16  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
  17  #define AR71XX_RESET_SIZE      0x100
  18 +#define AR71XX_MII_BASE                (AR71XX_APB_BASE + 0x00070000)
  19 +#define AR71XX_MII_SIZE                0x100
  20
  21  #define AR71XX_PCI_MEM_BASE    0x10000000
  22  #define AR71XX_PCI_MEM_SIZE    0x07000000
  23 @@ -82,15 +88,21 @@
  24
  25  #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
  26  #define AR933X_UART_SIZE       0x14
  27 +#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  28 +#define AR933X_GMAC_SIZE       0x04
  29  #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  30  #define AR933X_WMAC_SIZE       0x20000
  31  #define AR933X_EHCI_BASE       0x1b000000
  32  #define AR933X_EHCI_SIZE       0x1000
  33
  34 +#define AR934X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  35 +#define AR934X_GMAC_SIZE       0x14
  36  #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  37  #define AR934X_WMAC_SIZE       0x20000
  38  #define AR934X_EHCI_BASE       0x1b000000
  39  #define AR934X_EHCI_SIZE       0x200
  40 +#define AR934X_NFC_BASE                0x1b000200
  41 +#define AR934X_NFC_SIZE                0xb8
  42  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
  43  #define AR934X_SRIF_SIZE       0x1000
  44
  45 @@ -112,6 +124,10 @@
  46  #define QCA955X_EHCI0_BASE     0x1b000000
  47  #define QCA955X_EHCI1_BASE     0x1b400000
  48  #define QCA955X_EHCI_SIZE      0x200
  49 +#define QCA955X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
  50 +#define QCA955X_GMAC_SIZE      0x40
  51 +#define QCA955X_NFC_BASE       0x1b800200
  52 +#define QCA955X_NFC_SIZE       0xb8
  53
  54  #define AR9300_OTP_BASE                0x14000
  55  #define AR9300_OTP_STATUS      0x15f18
  56 @@ -175,6 +191,9 @@
  57  #define AR71XX_AHB_DIV_SHIFT           20
  58  #define AR71XX_AHB_DIV_MASK            0x7
  59
  60 +#define AR71XX_ETH0_PLL_SHIFT          17
  61 +#define AR71XX_ETH1_PLL_SHIFT          19
  62 +
  63  #define AR724X_PLL_REG_CPU_CONFIG      0x00
  64  #define AR724X_PLL_REG_PCIE_CONFIG     0x18
  65
  66 @@ -187,6 +206,8 @@
  67  #define AR724X_DDR_DIV_SHIFT           22
  68  #define AR724X_DDR_DIV_MASK            0x3
  69
  70 +#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2c
  71 +
  72  #define AR913X_PLL_REG_CPU_CONFIG      0x00
  73  #define AR913X_PLL_REG_ETH_CONFIG      0x04
  74  #define AR913X_PLL_REG_ETH0_INT_CLOCK  0x14
  75 @@ -199,6 +220,9 @@
  76  #define AR913X_AHB_DIV_SHIFT           19
  77  #define AR913X_AHB_DIV_MASK            0x1
  78
  79 +#define AR913X_ETH0_PLL_SHIFT          20
  80 +#define AR913X_ETH1_PLL_SHIFT          22
  81 +
  82  #define AR933X_PLL_CPU_CONFIG_REG      0x00
  83  #define AR933X_PLL_CLOCK_CTRL_REG      0x08
  84
  85 @@ -220,6 +244,8 @@
  86  #define AR934X_PLL_CPU_CONFIG_REG              0x00
  87  #define AR934X_PLL_DDR_CONFIG_REG              0x04
  88  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                0x08
  89 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG    0x24
  90 +#define AR934X_PLL_ETH_XMII_CONTROL_REG                0x2c
  91
  92  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
  93  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
  94 @@ -252,9 +278,13 @@
  95  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  96  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  97
  98 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
  99 +
 100  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 101  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 102  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 103 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG       0x28
 104 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG      0x48
 105
 106  #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 107  #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 108 @@ -378,16 +408,83 @@
 109  #define AR913X_RESET_USB_HOST          BIT(5)
 110  #define AR913X_RESET_USB_PHY           BIT(4)
 111
 112 +#define AR933X_RESET_GE1_MDIO          BIT(23)
 113 +#define AR933X_RESET_GE0_MDIO          BIT(22)
 114 +#define AR933X_RESET_GE1_MAC           BIT(13)
 115  #define AR933X_RESET_WMAC              BIT(11)
 116 +#define AR933X_RESET_GE0_MAC           BIT(9)
 117  #define AR933X_RESET_USB_HOST          BIT(5)
 118  #define AR933X_RESET_USB_PHY           BIT(4)
 119  #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 120
 121 +#define AR934X_RESET_HOST              BIT(31)
 122 +#define AR934X_RESET_SLIC              BIT(30)
 123 +#define AR934X_RESET_HDMA              BIT(29)
 124 +#define AR934X_RESET_EXTERNAL          BIT(28)
 125 +#define AR934X_RESET_RTC               BIT(27)
 126 +#define AR934X_RESET_PCIE_EP_INT       BIT(26)
 127 +#define AR934X_RESET_CHKSUM_ACC                BIT(25)
 128 +#define AR934X_RESET_FULL_CHIP         BIT(24)
 129 +#define AR934X_RESET_GE1_MDIO          BIT(23)
 130 +#define AR934X_RESET_GE0_MDIO          BIT(22)
 131 +#define AR934X_RESET_CPU_NMI           BIT(21)
 132 +#define AR934X_RESET_CPU_COLD          BIT(20)
 133 +#define AR934X_RESET_HOST_RESET_INT    BIT(19)
 134 +#define AR934X_RESET_PCIE_EP           BIT(18)
 135 +#define AR934X_RESET_UART1             BIT(17)
 136 +#define AR934X_RESET_DDR               BIT(16)
 137 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 138 +#define AR934X_RESET_NANDF             BIT(14)
 139 +#define AR934X_RESET_GE1_MAC           BIT(13)
 140 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
 141  #define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
 142 +#define AR934X_RESET_HOST_DMA_INT      BIT(10)
 143 +#define AR934X_RESET_GE0_MAC           BIT(9)
 144 +#define AR934X_RESET_ETH_SWITCH                BIT(8)
 145 +#define AR934X_RESET_PCIE_PHY          BIT(7)
 146 +#define AR934X_RESET_PCIE              BIT(6)
 147  #define AR934X_RESET_USB_HOST          BIT(5)
 148  #define AR934X_RESET_USB_PHY           BIT(4)
 149  #define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
 150 +#define AR934X_RESET_LUT               BIT(2)
 151 +#define AR934X_RESET_MBOX              BIT(1)
 152 +#define AR934X_RESET_I2S               BIT(0)
 153 +
 154 +#define QCA955X_RESET_HOST             BIT(31)
 155 +#define QCA955X_RESET_SLIC             BIT(30)
 156 +#define QCA955X_RESET_HDMA             BIT(29)
 157 +#define QCA955X_RESET_EXTERNAL         BIT(28)
 158 +#define QCA955X_RESET_RTC              BIT(27)
 159 +#define QCA955X_RESET_PCIE_EP_INT      BIT(26)
 160 +#define QCA955X_RESET_CHKSUM_ACC       BIT(25)
 161 +#define QCA955X_RESET_FULL_CHIP                BIT(24)
 162 +#define QCA955X_RESET_GE1_MDIO         BIT(23)
 163 +#define QCA955X_RESET_GE0_MDIO         BIT(22)
 164 +#define QCA955X_RESET_CPU_NMI          BIT(21)
 165 +#define QCA955X_RESET_CPU_COLD         BIT(20)
 166 +#define QCA955X_RESET_HOST_RESET_INT   BIT(19)
 167 +#define QCA955X_RESET_PCIE_EP          BIT(18)
 168 +#define QCA955X_RESET_UART1            BIT(17)
 169 +#define QCA955X_RESET_DDR              BIT(16)
 170 +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 171 +#define QCA955X_RESET_NANDF            BIT(14)
 172 +#define QCA955X_RESET_GE1_MAC          BIT(13)
 173 +#define QCA955X_RESET_SGMII_ANALOG     BIT(12)
 174 +#define QCA955X_RESET_USB_PHY_ANALOG   BIT(11)
 175 +#define QCA955X_RESET_HOST_DMA_INT     BIT(10)
 176 +#define QCA955X_RESET_GE0_MAC          BIT(9)
 177 +#define QCA955X_RESET_SGMII            BIT(8)
 178 +#define QCA955X_RESET_PCIE_PHY         BIT(7)
 179 +#define QCA955X_RESET_PCIE             BIT(6)
 180 +#define QCA955X_RESET_USB_HOST         BIT(5)
 181 +#define QCA955X_RESET_USB_PHY          BIT(4)
 182 +#define QCA955X_RESET_USBSUS_OVERRIDE  BIT(3)
 183 +#define QCA955X_RESET_LUT              BIT(2)
 184 +#define QCA955X_RESET_MBOX             BIT(1)
 185 +#define QCA955X_RESET_I2S              BIT(0)
 186
 187 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
 188 +#define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
 189  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
 190
 191  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
 192 @@ -529,6 +626,12 @@
 193  #define AR71XX_GPIO_REG_INT_ENABLE     0x24
 194  #define AR71XX_GPIO_REG_FUNC           0x28
 195
 196 +#define AR934X_GPIO_REG_OUT_FUNC0      0x2c
 197 +#define AR934X_GPIO_REG_OUT_FUNC1      0x30
 198 +#define AR934X_GPIO_REG_OUT_FUNC2      0x34
 199 +#define AR934X_GPIO_REG_OUT_FUNC3      0x38
 200 +#define AR934X_GPIO_REG_OUT_FUNC4      0x3c
 201 +#define AR934X_GPIO_REG_OUT_FUNC5      0x40
 202  #define AR934X_GPIO_REG_FUNC           0x6c
 203
 204  #define AR71XX_GPIO_COUNT              16
 205 @@ -560,4 +663,133 @@
 206  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
 207  #define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
 208
 209 +#define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 210 +#define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 211 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 212 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN            BIT(12)
 213 +#define AR71XX_GPIO_FUNC_UART_EN               BIT(8)
 214 +#define AR71XX_GPIO_FUNC_USB_OC_EN             BIT(4)
 215 +#define AR71XX_GPIO_FUNC_USB_CLK_EN            BIT(0)
 216 +
 217 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                BIT(19)
 218 +#define AR724X_GPIO_FUNC_SPI_EN                        BIT(18)
 219 +#define AR724X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 220 +#define AR724X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 221 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN           BIT(12)
 222 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN           BIT(11)
 223 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN           BIT(10)
 224 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN           BIT(9)
 225 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN           BIT(8)
 226 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 227 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 228 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 229 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 230 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 231 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 232 +#define AR724X_GPIO_FUNC_UART_EN               BIT(1)
 233 +#define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 234 +
 235 +#define AR913X_GPIO_FUNC_WMAC_LED_EN           BIT(22)
 236 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                BIT(21)
 237 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN          BIT(20)
 238 +#define AR913X_GPIO_FUNC_I2S_MCKEN             BIT(19)
 239 +#define AR913X_GPIO_FUNC_I2S1_EN               BIT(18)
 240 +#define AR913X_GPIO_FUNC_I2S0_EN               BIT(17)
 241 +#define AR913X_GPIO_FUNC_SLIC_EN               BIT(16)
 242 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                BIT(9)
 243 +#define AR913X_GPIO_FUNC_UART_EN               BIT(8)
 244 +#define AR913X_GPIO_FUNC_USB_CLK_EN            BIT(4)
 245 +
 246 +#define AR933X_GPIO_FUNC_SPDIF2TCK             BIT(31)
 247 +#define AR933X_GPIO_FUNC_SPDIF_EN              BIT(30)
 248 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN         BIT(29)
 249 +#define AR933X_GPIO_FUNC_I2S_MCK_EN            BIT(27)
 250 +#define AR933X_GPIO_FUNC_I2SO_EN               BIT(26)
 251 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL   BIT(25)
 252 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL   BIT(24)
 253 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT    BIT(23)
 254 +#define AR933X_GPIO_FUNC_SPI_EN                        BIT(18)
 255 +#define AR933X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 256 +#define AR933X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 257 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 258 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 259 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 260 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 261 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 262 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 263 +#define AR933X_GPIO_FUNC_UART_EN               BIT(1)
 264 +#define AR933X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 265 +
 266 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 267 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 268 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 269 +
 270 +#define AR934X_GPIO_OUT_GPIO           0x00
 271 +
 272 +/*
 273 + * MII_CTRL block
 274 + */
 275 +#define AR71XX_MII_REG_MII0_CTRL       0x00
 276 +#define AR71XX_MII_REG_MII1_CTRL       0x04
 277 +
 278 +#define AR71XX_MII_CTRL_IF_MASK                3
 279 +#define AR71XX_MII_CTRL_SPEED_SHIFT    4
 280 +#define AR71XX_MII_CTRL_SPEED_MASK     3
 281 +#define AR71XX_MII_CTRL_SPEED_10       0
 282 +#define AR71XX_MII_CTRL_SPEED_100      1
 283 +#define AR71XX_MII_CTRL_SPEED_1000     2
 284 +
 285 +#define AR71XX_MII0_CTRL_IF_GMII       0
 286 +#define AR71XX_MII0_CTRL_IF_MII                1
 287 +#define AR71XX_MII0_CTRL_IF_RGMII      2
 288 +#define AR71XX_MII0_CTRL_IF_RMII       3
 289 +
 290 +#define AR71XX_MII1_CTRL_IF_RGMII      0
 291 +#define AR71XX_MII1_CTRL_IF_RMII       1
 292 +
 293 +/*
 294 + * AR933X GMAC interface
 295 + */
 296 +#define AR933X_GMAC_REG_ETH_CFG                0x00
 297 +
 298 +#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
 299 +#define AR933X_ETH_CFG_MII_GE0         BIT(1)
 300 +#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
 301 +#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
 302 +#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
 303 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
 304 +#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 305 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
 306 +#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
 307 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
 308 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
 309 +
 310 +/*
 311 + * AR934X GMAC Interface
 312 + */
 313 +#define AR934X_GMAC_REG_ETH_CFG                0x00
 314 +
 315 +#define AR934X_ETH_CFG_RGMII_GMAC0     BIT(0)
 316 +#define AR934X_ETH_CFG_MII_GMAC0       BIT(1)
 317 +#define AR934X_ETH_CFG_GMII_GMAC0      BIT(2)
 318 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER        BIT(3)
 319 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
 320 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN        BIT(5)
 321 +#define AR934X_ETH_CFG_SW_ONLY_MODE    BIT(6)
 322 +#define AR934X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 323 +#define AR934X_ETH_CFG_SW_APB_ACCESS   BIT(9)
 324 +#define AR934X_ETH_CFG_RMII_GMAC0      BIT(10)
 325 +#define AR933X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
 326 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 327 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
 328 +
 329 +/*
 330 + * QCA955X GMAC Interface
 331 + */
 332 +
 333 +#define QCA955X_GMAC_REG_ETH_CFG       0x00
 334 +
 335 +#define QCA955X_ETH_CFG_RGMII_EN       BIT(0)
 336 +#define QCA955X_ETH_CFG_GE0_SGMII      BIT(6)
 337 +
 338  #endif /* __ASM_MACH_AR71XX_REGS_H */