1 --- a/arch/mips/ath79/mach-ap136.c
2 +++ b/arch/mips/ath79/mach-ap136.c
5 - * Qualcomm Atheros AP136 reference board support
6 + * Atheros AP136 reference board support
8 * Copyright (c) 2012 Qualcomm Atheros
9 * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
14 -#include <linux/pci.h>
15 -#include <linux/ath9k_platform.h>
16 +#include <linux/platform_device.h>
17 +#include <linux/ar8216_platform.h>
19 -#include "machtypes.h"
20 +#include <asm/mach-ath79/ar71xx_regs.h>
23 +#include "dev-ap9x-pci.h"
24 #include "dev-gpio-buttons.h"
26 #include "dev-leds-gpio.h"
28 +#include "dev-m25p80.h"
33 +#include "machtypes.h"
35 -#define AP136_GPIO_LED_STATUS_RED 14
36 -#define AP136_GPIO_LED_STATUS_GREEN 19
37 #define AP136_GPIO_LED_USB 4
38 -#define AP136_GPIO_LED_WLAN_2G 13
39 #define AP136_GPIO_LED_WLAN_5G 12
40 +#define AP136_GPIO_LED_WLAN_2G 13
41 +#define AP136_GPIO_LED_STATUS_RED 14
42 #define AP136_GPIO_LED_WPS_RED 15
43 +#define AP136_GPIO_LED_STATUS_GREEN 19
44 #define AP136_GPIO_LED_WPS_GREEN 20
46 #define AP136_GPIO_BTN_WPS 16
48 #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
49 #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
51 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
52 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
53 +#define AP136_MAC0_OFFSET 0
54 +#define AP136_MAC1_OFFSET 6
55 +#define AP136_WMAC_CALDATA_OFFSET 0x1000
56 +#define AP136_PCIE_CALDATA_OFFSET 0x5000
58 static struct gpio_led ap136_leds_gpio[] __initdata = {
60 @@ -98,64 +105,158 @@ static struct gpio_keys_button ap136_gpi
64 -static struct ath79_spi_controller_data ap136_spi0_data = {
65 - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
67 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
68 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
70 +static struct ar8327_platform_data ap136_ar8327_data = {
71 + .pad0_cfg = &ap136_ar8327_pad0_cfg,
72 + .pad6_cfg = &ap136_ar8327_pad6_cfg,
75 + .speed = AR8327_PORT_SPEED_1000,
82 + .speed = AR8327_PORT_SPEED_1000,
89 -static struct spi_board_info ap136_spi_info[] = {
90 +static struct mdio_board_info ap136_mdio0_info[] = {
94 - .max_speed_hz = 25000000,
95 - .modalias = "mx25l6405d",
96 - .controller_data = &ap136_spi0_data,
98 + .bus_id = "ag71xx-mdio.0",
100 + .platform_data = &ap136_ar8327_data,
104 -static struct ath79_spi_platform_data ap136_spi_data = {
106 - .num_chipselect = 1,
108 +static void __init ap136_gmac_setup(void)
110 + void __iomem *base;
114 -static struct ath9k_platform_data ap136_ath9k_data;
115 + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
117 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
119 - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
120 - dev->dev.platform_data = &ap136_ath9k_data;
121 + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
125 + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
126 + t |= QCA955X_ETH_CFG_RGMII_EN;
128 -static void __init ap136_pci_init(u8 *eeprom)
130 - memcpy(ap136_ath9k_data.eeprom_data, eeprom,
131 - sizeof(ap136_ath9k_data.eeprom_data));
132 + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
134 - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
135 - ath79_register_pci();
139 -static inline void ap136_pci_init(void) {}
140 -#endif /* CONFIG_PCI */
142 -static void __init ap136_setup(void)
143 +static void __init ap136_common_setup(void)
145 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
147 + ath79_register_m25p80(NULL);
149 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
151 ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
152 ARRAY_SIZE(ap136_gpio_keys),
154 - ath79_register_spi(&ap136_spi_data, ap136_spi_info,
155 - ARRAY_SIZE(ap136_spi_info));
157 ath79_register_usb();
158 - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
159 - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
160 + ath79_register_nfc();
162 + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
163 + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
165 + ap136_gmac_setup();
167 + ath79_register_mdio(0, 0x0);
169 + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
171 + mdiobus_register_board_info(ap136_mdio0_info,
172 + ARRAY_SIZE(ap136_mdio0_info));
174 + /* GMAC0 is connected to the RMGII interface */
175 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
176 + ath79_eth0_data.phy_mask = BIT(0);
177 + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
179 + ath79_register_eth(0);
181 + /* GMAC1 is connected tot eh SGMII interface */
182 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
183 + ath79_eth1_data.speed = SPEED_1000;
184 + ath79_eth1_data.duplex = DUPLEX_FULL;
186 + ath79_register_eth(1);
189 +static void __init ap136_010_setup(void)
191 + /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
192 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
193 + ap136_ar8327_pad0_cfg.txclk_delay_en = true;
194 + ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
195 + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
196 + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
198 + /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
199 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
200 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
201 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
203 + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
204 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
206 + ap136_common_setup();
209 +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
210 + "Atheros AP136-010 reference board",
213 +static void __init ap136_020_setup(void)
215 + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
216 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
217 + ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
219 + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
220 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
221 + ap136_ar8327_pad6_cfg.txclk_delay_en = true;
222 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
223 + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
224 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
226 + ath79_eth0_pll_data.pll_1000 = 0x56000000;
227 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
229 + ap136_common_setup();
232 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
233 + "Atheros AP136-020 reference board",
237 + * AP135-020 is similar to AP136-020, any future AP135 specific init
238 + * code can be added here.
240 +static void __init ap135_020_setup(void)
242 + ap136_leds_gpio[0].name = "ap135:green:status";
243 + ap136_leds_gpio[1].name = "ap135:red:status";
244 + ap136_leds_gpio[2].name = "ap135:green:wps";
245 + ap136_leds_gpio[3].name = "ap135:red:wps";
246 + ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
247 + ap136_leds_gpio[5].name = "ap135:red:usb";
252 -MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
254 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
255 + "Atheros AP135-020 reference board",
257 --- a/arch/mips/ath79/machtypes.h
258 +++ b/arch/mips/ath79/machtypes.h
259 @@ -18,7 +18,9 @@ enum ath79_mach_type {
260 ATH79_MACH_GENERIC = 0,
261 ATH79_MACH_AP121, /* Atheros AP121 reference board */
262 ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
263 - ATH79_MACH_AP136, /* Atheros AP136 reference board */
264 + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */
265 + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
266 + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */
267 ATH79_MACH_AP81, /* Atheros AP81 reference board */
268 ATH79_MACH_DB120, /* Atheros DB120 reference board */
269 ATH79_MACH_PB44, /* Atheros PB44 reference board */
270 --- a/arch/mips/ath79/Kconfig
271 +++ b/arch/mips/ath79/Kconfig
272 @@ -16,16 +16,17 @@ config ATH79_MACH_AP121
273 Atheros AP121 reference board.
275 config ATH79_MACH_AP136
276 - bool "Atheros AP136 reference board"
277 + bool "Atheros AP136/AP135 reference board"
279 select ATH79_DEV_GPIO_BUTTONS
280 select ATH79_DEV_LEDS_GPIO
281 + select ATH79_DEV_NFC
284 select ATH79_DEV_WMAC
286 Say 'Y' here if you want your kernel to support the
287 - Atheros AP136 reference board.
288 + Atheros AP136 or AP135 reference boards.
290 config ATH79_MACH_AP81
291 bool "Atheros AP81 reference board"