1 From 2e6a41e0be6a09ed839e3afbe1fb413a015d8870 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Tue, 29 Jan 2013 08:19:12 +0000
4 Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs
6 commit 8838becdf5f7261d7f5dfbbe957fe9b9ed188aec upstream.
8 GPIO function selection is not working on the AR934x
9 SoCs because the offset of the function selection
10 register is different on those.
12 Add a helper routine which returns the correct
13 register address based on the SoC type, and use
14 that in the 'ath79_gpio_function_*' routines.
16 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
17 Patchwork: http://patchwork.linux-mips.org/patch/4870/
18 Signed-off-by: John Crispin <blogic@openwrt.org>
20 arch/mips/ath79/gpio.c | 38 ++++++++++++++++--------
21 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
22 2 files changed, 28 insertions(+), 12 deletions(-)
24 --- a/arch/mips/ath79/gpio.c
25 +++ b/arch/mips/ath79/gpio.c
26 @@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip
30 +static void __iomem *ath79_gpio_get_function_reg(void)
34 + if (soc_is_ar71xx() ||
38 + reg = AR71XX_GPIO_REG_FUNC;
39 + else if (soc_is_ar934x())
40 + reg = AR934X_GPIO_REG_FUNC;
44 + return ath79_gpio_base + reg;
47 void ath79_gpio_function_enable(u32 mask)
49 - void __iomem *base = ath79_gpio_base;
50 + void __iomem *reg = ath79_gpio_get_function_reg();
53 spin_lock_irqsave(&ath79_gpio_lock, flags);
55 - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
56 - base + AR71XX_GPIO_REG_FUNC);
57 + __raw_writel(__raw_readl(reg) | mask, reg);
59 - __raw_readl(base + AR71XX_GPIO_REG_FUNC);
62 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
65 void ath79_gpio_function_disable(u32 mask)
67 - void __iomem *base = ath79_gpio_base;
68 + void __iomem *reg = ath79_gpio_get_function_reg();
71 spin_lock_irqsave(&ath79_gpio_lock, flags);
73 - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
74 - base + AR71XX_GPIO_REG_FUNC);
75 + __raw_writel(__raw_readl(reg) & ~mask, reg);
77 - __raw_readl(base + AR71XX_GPIO_REG_FUNC);
80 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
83 void ath79_gpio_function_setup(u32 set, u32 clear)
85 - void __iomem *base = ath79_gpio_base;
86 + void __iomem *reg = ath79_gpio_get_function_reg();
89 spin_lock_irqsave(&ath79_gpio_lock, flags);
91 - __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
92 - base + AR71XX_GPIO_REG_FUNC);
93 + __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
95 - __raw_readl(base + AR71XX_GPIO_REG_FUNC);
98 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
100 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
101 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
103 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
104 #define AR71XX_GPIO_REG_FUNC 0x28
106 +#define AR934X_GPIO_REG_FUNC 0x6c
108 #define AR71XX_GPIO_COUNT 16
109 #define AR7240_GPIO_COUNT 18
110 #define AR7241_GPIO_COUNT 20