1 --- a/arch/mips/ath79/mach-ap136.c
2 +++ b/arch/mips/ath79/mach-ap136.c
7 -#include <linux/pci.h>
8 -#include <linux/ath9k_platform.h>
9 +#include <linux/platform_device.h>
10 +#include <linux/ar8216_platform.h>
12 -#include "machtypes.h"
13 +#include <asm/mach-ath79/ar71xx_regs.h>
16 +#include "dev-ap9x-pci.h"
17 #include "dev-gpio-buttons.h"
19 #include "dev-leds-gpio.h"
21 +#include "dev-m25p80.h"
26 +#include "machtypes.h"
28 -#define AP136_GPIO_LED_STATUS_RED 14
29 -#define AP136_GPIO_LED_STATUS_GREEN 19
30 #define AP136_GPIO_LED_USB 4
31 -#define AP136_GPIO_LED_WLAN_2G 13
32 #define AP136_GPIO_LED_WLAN_5G 12
33 +#define AP136_GPIO_LED_WLAN_2G 13
34 +#define AP136_GPIO_LED_STATUS_RED 14
35 #define AP136_GPIO_LED_WPS_RED 15
36 +#define AP136_GPIO_LED_STATUS_GREEN 19
37 #define AP136_GPIO_LED_WPS_GREEN 20
39 #define AP136_GPIO_BTN_WPS 16
41 #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
42 #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
44 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
45 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
46 +#define AP136_MAC0_OFFSET 0
47 +#define AP136_MAC1_OFFSET 6
48 +#define AP136_WMAC_CALDATA_OFFSET 0x1000
49 +#define AP136_PCIE_CALDATA_OFFSET 0x5000
51 static struct gpio_led ap136_leds_gpio[] __initdata = {
53 - .name = "qca:green:status",
54 + .name = "ap136:green:status",
55 .gpio = AP136_GPIO_LED_STATUS_GREEN,
59 - .name = "qca:red:status",
60 + .name = "ap136:red:status",
61 .gpio = AP136_GPIO_LED_STATUS_RED,
65 - .name = "qca:green:wps",
66 + .name = "ap136:green:wps",
67 .gpio = AP136_GPIO_LED_WPS_GREEN,
71 - .name = "qca:red:wps",
72 + .name = "ap136:red:wps",
73 .gpio = AP136_GPIO_LED_WPS_RED,
77 - .name = "qca:red:wlan-2g",
78 + .name = "ap136:red:wlan-2g",
79 .gpio = AP136_GPIO_LED_WLAN_2G,
83 - .name = "qca:red:usb",
84 + .name = "ap136:red:usb",
85 .gpio = AP136_GPIO_LED_USB,
88 @@ -98,65 +105,158 @@ static struct gpio_keys_button ap136_gpi
92 -static struct ath79_spi_controller_data ap136_spi0_data = {
93 - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
95 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
96 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
98 +static struct ar8327_platform_data ap136_ar8327_data = {
99 + .pad0_cfg = &ap136_ar8327_pad0_cfg,
100 + .pad6_cfg = &ap136_ar8327_pad6_cfg,
103 + .speed = AR8327_PORT_SPEED_1000,
110 + .speed = AR8327_PORT_SPEED_1000,
117 -static struct spi_board_info ap136_spi_info[] = {
118 +static struct mdio_board_info ap136_mdio0_info[] = {
122 - .max_speed_hz = 25000000,
123 - .modalias = "mx25l6405d",
124 - .controller_data = &ap136_spi0_data,
126 + .bus_id = "ag71xx-mdio.0",
128 + .platform_data = &ap136_ar8327_data,
132 -static struct ath79_spi_platform_data ap136_spi_data = {
134 - .num_chipselect = 1,
136 +static void __init ap136_gmac_setup(void)
138 + void __iomem *base;
142 -static struct ath9k_platform_data ap136_ath9k_data;
143 + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
145 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
147 - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
148 - dev->dev.platform_data = &ap136_ath9k_data;
149 + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
153 + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
154 + t |= QCA955X_ETH_CFG_RGMII_EN;
156 -static void __init ap136_pci_init(u8 *eeprom)
158 - memcpy(ap136_ath9k_data.eeprom_data, eeprom,
159 - sizeof(ap136_ath9k_data.eeprom_data));
160 + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
162 - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
163 - ath79_register_pci();
167 -static inline void ap136_pci_init(void) {}
168 -#endif /* CONFIG_PCI */
170 -static void __init ap136_setup(void)
171 +static void __init ap136_common_setup(void)
173 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
175 + ath79_register_m25p80(NULL);
177 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
179 ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
180 ARRAY_SIZE(ap136_gpio_keys),
182 - ath79_register_spi(&ap136_spi_data, ap136_spi_info,
183 - ARRAY_SIZE(ap136_spi_info));
185 ath79_register_usb();
186 - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
187 - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
188 + ath79_register_nfc();
190 + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
191 + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
193 + ap136_gmac_setup();
195 + ath79_register_mdio(0, 0x0);
197 + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
199 + mdiobus_register_board_info(ap136_mdio0_info,
200 + ARRAY_SIZE(ap136_mdio0_info));
202 + /* GMAC0 is connected to the RMGII interface */
203 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
204 + ath79_eth0_data.phy_mask = BIT(0);
205 + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
207 + ath79_register_eth(0);
209 + /* GMAC1 is connected tot eh SGMII interface */
210 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
211 + ath79_eth1_data.speed = SPEED_1000;
212 + ath79_eth1_data.duplex = DUPLEX_FULL;
214 + ath79_register_eth(1);
217 +static void __init ap136_010_setup(void)
219 + /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
220 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
221 + ap136_ar8327_pad0_cfg.txclk_delay_en = true;
222 + ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
223 + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
224 + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
226 + /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
227 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
228 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
229 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
231 + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
232 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
234 + ap136_common_setup();
237 MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
238 "Atheros AP136-010 reference board",
242 +static void __init ap136_020_setup(void)
244 + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
245 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
246 + ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
248 + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
249 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
250 + ap136_ar8327_pad6_cfg.txclk_delay_en = true;
251 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
252 + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
253 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
255 + ath79_eth0_pll_data.pll_1000 = 0x56000000;
256 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
258 + ap136_common_setup();
261 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
262 + "Atheros AP136-020 reference board",
266 + * AP135-020 is similar to AP136-020, any future AP135 specific init
267 + * code can be added here.
269 +static void __init ap135_020_setup(void)
271 + ap136_leds_gpio[0].name = "ap135:green:status";
272 + ap136_leds_gpio[1].name = "ap135:red:status";
273 + ap136_leds_gpio[2].name = "ap135:green:wps";
274 + ap136_leds_gpio[3].name = "ap135:red:wps";
275 + ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
276 + ap136_leds_gpio[5].name = "ap135:red:usb";
281 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
282 + "Atheros AP135-020 reference board",
284 --- a/arch/mips/ath79/machtypes.h
285 +++ b/arch/mips/ath79/machtypes.h
286 @@ -18,7 +18,9 @@ enum ath79_mach_type {
287 ATH79_MACH_GENERIC = 0,
288 ATH79_MACH_AP121, /* Atheros AP121 reference board */
289 ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
290 + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */
291 ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
292 + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */
293 ATH79_MACH_AP81, /* Atheros AP81 reference board */
294 ATH79_MACH_DB120, /* Atheros DB120 reference board */
295 ATH79_MACH_PB44, /* Atheros PB44 reference board */
296 --- a/arch/mips/ath79/Kconfig
297 +++ b/arch/mips/ath79/Kconfig
298 @@ -16,16 +16,17 @@ config ATH79_MACH_AP121
299 Atheros AP121 reference board.
301 config ATH79_MACH_AP136
302 - bool "Atheros AP136 reference board"
303 + bool "Atheros AP136/AP135 reference board"
305 select ATH79_DEV_GPIO_BUTTONS
306 select ATH79_DEV_LEDS_GPIO
307 + select ATH79_DEV_NFC
310 select ATH79_DEV_WMAC
312 Say 'Y' here if you want your kernel to support the
313 - Atheros AP136 reference board.
314 + Atheros AP136 or AP135 reference boards.
316 config ATH79_MACH_AP81
317 bool "Atheros AP81 reference board"