1 --- a/arch/mips/ath79/Kconfig
2 +++ b/arch/mips/ath79/Kconfig
3 @@ -114,6 +114,12 @@ config SOC_QCA955X
4 select PCI_AR724X if PCI
8 + select USB_ARCH_HAS_EHCI
10 + select PCI_AR724X if PCI
13 config ATH79_DEV_M25P80
16 @@ -148,7 +154,7 @@ config ATH79_DEV_USB
20 - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
21 + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
25 --- a/arch/mips/ath79/clock.c
26 +++ b/arch/mips/ath79/clock.c
27 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
28 clk_add_alias("uart", NULL, "ref", NULL);
31 +static void __init qca956x_clocks_init(void)
33 + unsigned long ref_rate;
34 + unsigned long cpu_rate;
35 + unsigned long ddr_rate;
36 + unsigned long ahb_rate;
37 + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
38 + u32 cpu_pll, ddr_pll;
41 + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
42 + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
43 + ref_rate = 40 * 1000 * 1000;
45 + ref_rate = 25 * 1000 * 1000;
47 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
48 + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
49 + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
50 + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
51 + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
53 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
54 + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
55 + QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
56 + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
57 + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
58 + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
59 + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
61 + cpu_pll = nint * ref_rate / ref_div;
62 + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
63 + cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
64 + cpu_pll /= (1 << out_div);
66 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
67 + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
68 + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
69 + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
70 + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
71 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
72 + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
73 + QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
74 + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
75 + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
76 + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
77 + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
79 + ddr_pll = nint * ref_rate / ref_div;
80 + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
81 + ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
82 + ddr_pll /= (1 << out_div);
84 + clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
86 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
87 + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
89 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
90 + cpu_rate = ref_rate;
91 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
92 + cpu_rate = ddr_pll / (postdiv + 1);
94 + cpu_rate = cpu_pll / (postdiv + 1);
96 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
97 + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
99 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
100 + ddr_rate = ref_rate;
101 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
102 + ddr_rate = cpu_pll / (postdiv + 1);
104 + ddr_rate = ddr_pll / (postdiv + 1);
106 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
107 + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
109 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
110 + ahb_rate = ref_rate;
111 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
112 + ahb_rate = ddr_pll / (postdiv + 1);
114 + ahb_rate = cpu_pll / (postdiv + 1);
116 + ath79_add_sys_clkdev("ref", ref_rate);
117 + ath79_add_sys_clkdev("cpu", cpu_rate);
118 + ath79_add_sys_clkdev("ddr", ddr_rate);
119 + ath79_add_sys_clkdev("ahb", ahb_rate);
121 + clk_add_alias("wdt", NULL, "ref", NULL);
122 + clk_add_alias("uart", NULL, "ref", NULL);
125 void __init ath79_clocks_init(void)
128 @@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
129 qca953x_clocks_init();
130 else if (soc_is_qca955x())
131 qca955x_clocks_init();
132 + else if (soc_is_qca956x() || soc_is_tp9343())
133 + qca956x_clocks_init();
137 --- a/arch/mips/ath79/common.c
138 +++ b/arch/mips/ath79/common.c
139 @@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
140 reg = QCA953X_RESET_REG_RESET_MODULE;
141 else if (soc_is_qca955x())
142 reg = QCA955X_RESET_REG_RESET_MODULE;
143 + else if (soc_is_qca956x() || soc_is_tp9343())
144 + reg = QCA956X_RESET_REG_RESET_MODULE;
146 panic("Reset register not defined for this SOC");
148 @@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
149 reg = QCA953X_RESET_REG_RESET_MODULE;
150 else if (soc_is_qca955x())
151 reg = QCA955X_RESET_REG_RESET_MODULE;
152 + else if (soc_is_qca956x() || soc_is_tp9343())
153 + reg = QCA956X_RESET_REG_RESET_MODULE;
155 panic("Reset register not defined for this SOC");
157 @@ -133,6 +137,8 @@ u32 ath79_device_reset_get(u32 mask)
158 reg = AR933X_RESET_REG_RESET_MODULE;
159 else if (soc_is_ar934x())
160 reg = AR934X_RESET_REG_RESET_MODULE;
161 + else if (soc_is_qca956x() || soc_is_tp9343())
162 + reg = QCA956X_RESET_REG_RESET_MODULE;
166 --- a/arch/mips/ath79/dev-common.c
167 +++ b/arch/mips/ath79/dev-common.c
168 @@ -94,7 +94,9 @@ void __init ath79_register_uart(void)
172 - soc_is_qca955x()) {
173 + soc_is_qca955x() ||
174 + soc_is_qca956x() ||
176 ath79_uart_data[0].uartclk = uart_clk_rate;
177 platform_device_register(&ath79_uart_device);
178 } else if (soc_is_ar933x()) {
179 --- a/arch/mips/ath79/dev-usb.c
180 +++ b/arch/mips/ath79/dev-usb.c
181 @@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
182 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
185 +static void __init qca956x_usb_setup(void)
187 + ath79_usb_register("ehci-platform", 0,
188 + QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
190 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
192 + ath79_usb_register("ehci-platform", 1,
193 + QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
195 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
198 void __init ath79_register_usb(void)
201 @@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
203 else if (soc_is_qca955x())
205 + else if (soc_is_qca956x())
206 + qca956x_usb_setup();
210 --- a/arch/mips/ath79/dev-wmac.c
211 +++ b/arch/mips/ath79/dev-wmac.c
212 @@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
213 ath79_wmac_data.is_clk_25mhz = true;
216 +static void qca956x_wmac_setup(void)
220 + ath79_wmac_device.name = "qca956x_wmac";
222 + ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
223 + ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
224 + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
225 + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
227 + t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
228 + if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
229 + ath79_wmac_data.is_clk_25mhz = false;
231 + ath79_wmac_data.is_clk_25mhz = true;
233 + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
237 ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
239 @@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
240 qca953x_wmac_setup();
241 else if (soc_is_qca955x())
242 qca955x_wmac_setup();
243 + else if (soc_is_qca956x() || soc_is_tp9343())
244 + qca956x_wmac_setup();
248 --- a/arch/mips/ath79/early_printk.c
249 +++ b/arch/mips/ath79/early_printk.c
250 @@ -118,6 +118,8 @@ static void prom_putchar_init(void)
251 case REV_ID_MAJOR_QCA9533_V2:
252 case REV_ID_MAJOR_QCA9556:
253 case REV_ID_MAJOR_QCA9558:
254 + case REV_ID_MAJOR_TP9343:
255 + case REV_ID_MAJOR_QCA956X:
256 _prom_putchar = prom_putchar_ar71xx;
259 --- a/arch/mips/ath79/gpio.c
260 +++ b/arch/mips/ath79/gpio.c
261 @@ -148,7 +148,10 @@ static void __iomem *ath79_gpio_get_func
264 reg = AR71XX_GPIO_REG_FUNC;
265 - else if (soc_is_ar934x() || soc_is_qca953x())
266 + else if (soc_is_ar934x() ||
267 + soc_is_qca953x() ||
268 + soc_is_qca956x() ||
270 reg = AR934X_GPIO_REG_FUNC;
273 @@ -187,7 +190,7 @@ void __init ath79_gpio_output_select(uns
277 - BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
278 + BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
280 if (gpio >= AR934X_GPIO_COUNT)
282 @@ -228,12 +231,15 @@ void __init ath79_gpio_init(void)
283 ath79_gpio_count = QCA953X_GPIO_COUNT;
284 else if (soc_is_qca955x())
285 ath79_gpio_count = QCA955X_GPIO_COUNT;
286 + else if (soc_is_qca956x() || soc_is_tp9343())
287 + ath79_gpio_count = QCA956X_GPIO_COUNT;
291 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
292 ath79_gpio_chip.ngpio = ath79_gpio_count;
293 - if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
294 + if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
295 + soc_is_qca956x() || soc_is_tp9343()) {
296 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
297 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
299 --- a/arch/mips/ath79/irq.c
300 +++ b/arch/mips/ath79/irq.c
301 @@ -107,7 +107,9 @@ static void __init ath79_misc_irq_init(v
306 + soc_is_qca955x() ||
307 + soc_is_qca956x() ||
309 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
312 @@ -268,6 +270,97 @@ static void qca955x_irq_init(void)
313 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
316 +static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
320 + disable_irq_nosync(irq);
322 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
323 + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
326 + spurious_interrupt();
330 + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
331 + /* TODO: flush DDR? */
332 + generic_handle_irq(ATH79_IP2_IRQ(0));
335 + if (status & QCA956X_EXT_INT_WMAC_ALL) {
336 + /* TODO: flsuh DDR? */
337 + generic_handle_irq(ATH79_IP2_IRQ(1));
344 +static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
348 + disable_irq_nosync(irq);
350 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
351 + status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
352 + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
355 + spurious_interrupt();
359 + if (status & QCA956X_EXT_INT_USB1) {
360 + /* TODO: flush DDR? */
361 + generic_handle_irq(ATH79_IP3_IRQ(0));
364 + if (status & QCA956X_EXT_INT_USB2) {
365 + /* TODO: flush DDR? */
366 + generic_handle_irq(ATH79_IP3_IRQ(1));
369 + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
370 + /* TODO: flush DDR? */
371 + generic_handle_irq(ATH79_IP3_IRQ(2));
378 +static void qca956x_enable_timer_cb(void) {
381 + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
382 + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
383 + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
386 +static void qca956x_irq_init(void)
390 + for (i = ATH79_IP2_IRQ_BASE;
391 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
392 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
394 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
396 + for (i = ATH79_IP3_IRQ_BASE;
397 + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
398 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
400 + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
402 + /* QCA956x timer init workaround has to be applied right before setting
403 + * up the clock. Else, there will be no jiffies */
404 + late_time_init = &qca956x_enable_timer_cb;
407 asmlinkage void plat_irq_dispatch(void)
409 unsigned long pending;
410 @@ -397,6 +490,9 @@ void __init arch_init_irq(void)
411 } else if (soc_is_qca955x()) {
412 ath79_ip2_handler = ath79_default_ip2_handler;
413 ath79_ip3_handler = ath79_default_ip3_handler;
414 + } else if (soc_is_qca956x() || soc_is_tp9343()) {
415 + ath79_ip2_handler = ath79_default_ip2_handler;
416 + ath79_ip3_handler = ath79_default_ip3_handler;
420 @@ -410,4 +506,6 @@ void __init arch_init_irq(void)
422 else if (soc_is_qca955x())
424 + else if (soc_is_qca956x() || soc_is_tp9343())
425 + qca956x_irq_init();
427 --- a/arch/mips/ath79/pci.c
428 +++ b/arch/mips/ath79/pci.c
429 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
433 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
438 + .irq = ATH79_PCI_IRQ(0),
444 + .irq = ATH79_PCI_IRQ(1),
448 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
451 @@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
452 } else if (soc_is_qca955x()) {
453 ath79_pci_irq_map = qca955x_pci_irq_map;
454 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
455 + } else if (soc_is_qca956x()) {
456 + ath79_pci_irq_map = qca956x_pci_irq_map;
457 + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
459 pr_crit("pci %s: invalid irq map\n",
460 pci_name((struct pci_dev *) dev));
461 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
462 QCA955X_PCI_MEM_SIZE,
465 + } else if (soc_is_qca956x()) {
466 + pdev = ath79_register_pci_ar724x(0,
467 + QCA956X_PCI_CFG_BASE1,
468 + QCA956X_PCI_CTRL_BASE1,
469 + QCA956X_PCI_CRP_BASE1,
470 + QCA956X_PCI_MEM_BASE1,
471 + QCA956X_PCI_MEM_SIZE,
477 --- a/arch/mips/ath79/setup.c
478 +++ b/arch/mips/ath79/setup.c
479 @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
480 rev = id & QCA955X_REV_ID_REVISION_MASK;
483 + case REV_ID_MAJOR_QCA956X:
484 + ath79_soc = ATH79_SOC_QCA956X;
486 + rev = id & QCA956X_REV_ID_REVISION_MASK;
489 + case REV_ID_MAJOR_TP9343:
490 + ath79_soc = ATH79_SOC_TP9343;
492 + rev = id & QCA956X_REV_ID_REVISION_MASK;
496 panic("ath79: unknown SoC, id:0x%08x", id);
498 @@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
502 - if (soc_is_qca953x() || soc_is_qca955x())
503 + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
504 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
506 + else if (soc_is_tp9343())
507 + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
510 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
511 pr_info("SoC: %s\n", ath79_sys_type);
512 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
513 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
515 #define QCA955X_NFC_BASE 0x1b800200
516 #define QCA955X_NFC_SIZE 0xb8
518 +#define QCA956X_PCI_MEM_BASE1 0x12000000
519 +#define QCA956X_PCI_MEM_SIZE 0x02000000
520 +#define QCA956X_PCI_CFG_BASE1 0x16000000
521 +#define QCA956X_PCI_CFG_SIZE 0x1000
522 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
523 +#define QCA956X_PCI_CRP_SIZE 0x1000
524 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
525 +#define QCA956X_PCI_CTRL_SIZE 0x100
527 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
528 +#define QCA956X_WMAC_SIZE 0x20000
529 +#define QCA956X_EHCI0_BASE 0x1b000000
530 +#define QCA956X_EHCI1_BASE 0x1b400000
531 +#define QCA956X_EHCI_SIZE 0x200
532 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
533 +#define QCA956X_GMAC_SIZE 0x64
535 #define AR9300_OTP_BASE 0x14000
536 #define AR9300_OTP_STATUS 0x15f18
537 #define AR9300_OTP_STATUS_TYPE 0x7
539 #define AR9300_OTP_READ_DATA 0x15f1c
544 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
545 +#define QCA956X_DAM_RESET_SIZE 0x4
546 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
551 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
553 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
554 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
556 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
557 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
558 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
559 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
560 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
562 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
563 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
564 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
565 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
567 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
568 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
569 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
570 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
571 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
572 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
574 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
575 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
576 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
577 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
579 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
580 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
581 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
582 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
583 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
584 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
586 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
587 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
588 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
589 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
590 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
591 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
592 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
593 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
594 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
595 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
596 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
597 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
603 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
604 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
606 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
607 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
608 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
610 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
611 #define MISC_INT_ETHSW BIT(12)
612 #define MISC_INT_TIMER4 BIT(10)
613 #define MISC_INT_TIMER3 BIT(9)
616 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
618 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
620 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
621 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
622 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
624 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
625 QCA955X_EXT_INT_PCIE_RC2_INT3)
627 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
628 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
629 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
630 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
631 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
632 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
633 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
634 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
635 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
636 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
637 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
638 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
639 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
640 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
641 +#define QCA956X_EXT_INT_USB1 BIT(24)
642 +#define QCA956X_EXT_INT_USB2 BIT(28)
644 +#define QCA956X_EXT_INT_WMAC_ALL \
645 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
646 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
648 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
649 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
650 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
651 + QCA956X_EXT_INT_PCIE_RC1_INT3)
653 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
654 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
655 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
656 + QCA956X_EXT_INT_PCIE_RC2_INT3)
658 #define REV_ID_MAJOR_MASK 0xfff0
659 #define REV_ID_MAJOR_AR71XX 0x00a0
660 #define REV_ID_MAJOR_AR913X 0x00b0
662 #define REV_ID_MAJOR_QCA9533_V2 0x0160
663 #define REV_ID_MAJOR_QCA9556 0x0130
664 #define REV_ID_MAJOR_QCA9558 0x1130
665 +#define REV_ID_MAJOR_TP9343 0x0150
666 +#define REV_ID_MAJOR_QCA956X 0x1150
668 #define AR71XX_REV_ID_MINOR_MASK 0x3
669 #define AR71XX_REV_ID_MINOR_AR7130 0x0
672 #define QCA955X_REV_ID_REVISION_MASK 0xf
674 +#define QCA956X_REV_ID_REVISION_MASK 0xf
680 #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
681 #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
683 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
684 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
685 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
686 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
687 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
688 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
689 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
690 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
691 +#define QCA956X_GPIO_REG_FUNC 0x6c
693 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
694 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
696 #define AR71XX_GPIO_COUNT 16
697 #define AR7240_GPIO_COUNT 18
698 #define AR7241_GPIO_COUNT 20
700 #define AR934X_GPIO_COUNT 23
701 #define QCA953X_GPIO_COUNT 18
702 #define QCA955X_GPIO_COUNT 24
703 +#define QCA956X_GPIO_COUNT 23
707 --- a/arch/mips/include/asm/mach-ath79/ath79.h
708 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
709 @@ -35,6 +35,8 @@ enum ath79_soc_type {
717 extern enum ath79_soc_type ath79_soc;
718 @@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
719 return soc_is_qca9556() || soc_is_qca9558();
722 +static inline int soc_is_tp9343(void)
724 + return ath79_soc == ATH79_SOC_TP9343;
727 +static inline int soc_is_qca9561(void)
729 + return ath79_soc == ATH79_SOC_QCA956X;
732 +static inline int soc_is_qca9563(void)
734 + return ath79_soc == ATH79_SOC_QCA956X;
737 +static inline int soc_is_qca956x(void)
739 + return soc_is_qca9561() || soc_is_qca9563();
742 extern void __iomem *ath79_ddr_base;
743 extern void __iomem *ath79_gpio_base;
744 extern void __iomem *ath79_pll_base;