1 --- a/drivers/spi/spi-ath79.c
2 +++ b/drivers/spi/spi-ath79.c
3 @@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
4 /* save CTRL register */
5 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
6 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
8 - /* TODO: setup speed? */
9 - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
12 static void ath79_spi_disable(struct ath79_spi *sp)
13 @@ -205,6 +202,38 @@ static u32 ath79_spi_txrx_mode0(struct s
14 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
17 +static bool ath79_spi_flash_read_supported(struct spi_device *spi)
19 + if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
25 +static int ath79_spi_read_flash_data(struct spi_device *spi,
26 + struct spi_flash_read_message *msg)
28 + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
30 + if (msg->addr_width > 3)
33 + /* disable GPIO mode */
34 + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
36 + memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
38 + /* enable GPIO mode */
39 + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
41 + /* restore IOC register */
42 + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
44 + msg->retlen = msg->len;
49 static int ath79_spi_probe(struct platform_device *pdev)
51 struct spi_master *master;
52 @@ -234,6 +263,8 @@ static int ath79_spi_probe(struct platfo
53 master->num_chipselect = pdata->num_chipselect;
54 master->cs_gpios = pdata->cs_gpios;
56 + master->spi_flash_read = ath79_spi_read_flash_data;
57 + master->flash_read_supported = ath79_spi_flash_read_supported;
59 sp->bitbang.master = master;
60 sp->bitbang.chipselect = ath79_spi_chipselect;