1 --- a/arch/mips/ath79/irq.c
2 +++ b/arch/mips/ath79/irq.c
7 +static struct irq_chip ip2_chip;
8 +static struct irq_chip ip3_chip;
10 static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
13 @@ -50,8 +53,7 @@ static void ar934x_ip2_irq_init(void)
15 for (i = ATH79_IP2_IRQ_BASE;
16 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
17 - irq_set_chip_and_handler(i, &dummy_irq_chip,
19 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
21 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
23 @@ -79,7 +81,7 @@ static void qca953x_irq_init(void)
25 for (i = ATH79_IP2_IRQ_BASE;
26 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
27 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
28 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
30 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
32 @@ -143,15 +145,13 @@ static void qca955x_irq_init(void)
34 for (i = ATH79_IP2_IRQ_BASE;
35 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
36 - irq_set_chip_and_handler(i, &dummy_irq_chip,
38 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
40 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
42 for (i = ATH79_IP3_IRQ_BASE;
43 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
44 - irq_set_chip_and_handler(i, &dummy_irq_chip,
46 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
48 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
50 @@ -222,13 +222,13 @@ static void qca956x_irq_init(void)
52 for (i = ATH79_IP2_IRQ_BASE;
53 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
54 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
55 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
57 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
59 for (i = ATH79_IP3_IRQ_BASE;
60 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
61 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
62 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
64 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
66 @@ -237,12 +237,40 @@ static void qca956x_irq_init(void)
67 late_time_init = &qca956x_enable_timer_cb;
70 +static void ath79_ip2_disable(struct irq_data *data)
72 + disable_irq(ATH79_CPU_IRQ(2));
75 +static void ath79_ip2_enable(struct irq_data *data)
77 + enable_irq(ATH79_CPU_IRQ(2));
80 +static void ath79_ip3_disable(struct irq_data *data)
82 + disable_irq(ATH79_CPU_IRQ(3));
85 +static void ath79_ip3_enable(struct irq_data *data)
87 + enable_irq(ATH79_CPU_IRQ(3));
90 void __init arch_init_irq(void)
92 unsigned irq_wb_chan2 = -1;
93 unsigned irq_wb_chan3 = -1;
96 + ip2_chip = dummy_irq_chip;
97 + ip2_chip.irq_disable = ath79_ip2_disable;
98 + ip2_chip.irq_enable = ath79_ip2_enable;
100 + ip3_chip = dummy_irq_chip;
101 + ip3_chip.irq_disable = ath79_ip3_disable;
102 + ip3_chip.irq_enable = ath79_ip3_enable;
104 if (mips_machtype == ATH79_MACH_GENERIC_OF) {