target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_eth.h

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *   Ethernet register definition
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb.
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #ifndef __IDT_ETH_H__
  40 #define __IDT_ETH_H__
  41
  42
  43 enum
  44 {
  45         ETH0_PhysicalAddress    = 0x18060000,
  46         ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
  47
  48         ETH0_VirtualAddress     = 0xb8060000,
  49         ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
  50 } ;
  51
  52 typedef struct
  53 {
  54         u32 ethintfc            ;
  55         u32 ethfifott           ;
  56         u32 etharc              ;
  57         u32 ethhash0            ;
  58         u32 ethhash1            ;
  59         u32 ethu0 [4]           ;       // Reserved.
  60         u32 ethpfs              ;
  61         u32 ethmcp              ;
  62         u32 eth_u1 [10]         ;       // Reserved.
  63         u32 ethspare            ;
  64         u32 eth_u2 [42]         ;       // Reserved.
  65         u32 ethsal0             ;
  66         u32 ethsah0             ;
  67         u32 ethsal1             ;
  68         u32 ethsah1             ;
  69         u32 ethsal2             ;
  70         u32 ethsah2             ;
  71         u32 ethsal3             ;
  72         u32 ethsah3             ;
  73         u32 ethrbc              ;
  74         u32 ethrpc              ;
  75         u32 ethrupc             ;
  76         u32 ethrfc              ;
  77         u32 ethtbc              ;
  78         u32 ethgpf              ;
  79         u32 eth_u9 [50]         ;       // Reserved.
  80         u32 ethmac1             ;
  81         u32 ethmac2             ;
  82         u32 ethipgt             ;
  83         u32 ethipgr             ;
  84         u32 ethclrt             ;
  85         u32 ethmaxf             ;
  86         u32 eth_u10             ;       // Reserved.
  87         u32 ethmtest            ;
  88         u32 miimcfg             ;
  89         u32 miimcmd             ;
  90         u32 miimaddr            ;
  91         u32 miimwtd             ;
  92         u32 miimrdd             ;
  93         u32 miimind             ;
  94         u32 eth_u11             ;       // Reserved.
  95         u32 eth_u12             ;       // Reserved.
  96         u32 ethcfsa0            ;
  97         u32 ethcfsa1            ;
  98         u32 ethcfsa2            ;
  99 } volatile *ETH_t;
 100
 101 enum
 102 {
 103         ETHINTFC_en_b           = 0,
 104         ETHINTFC_en_m           = 0x00000001,
 105         ETHINTFC_its_b          = 1,
 106         ETHINTFC_its_m          = 0x00000002,
 107         ETHINTFC_rip_b          = 2,
 108         ETHINTFC_rip_m          = 0x00000004,
 109         ETHINTFC_jam_b          = 3,
 110         ETHINTFC_jam_m          = 0x00000008,
 111         ETHINTFC_ovr_b          = 4,
 112         ETHINTFC_ovr_m          = 0x00000010,
 113         ETHINTFC_und_b          = 5,
 114         ETHINTFC_und_m          = 0x00000020,
 115
 116         ETHFIFOTT_tth_b         = 0,
 117         ETHFIFOTT_tth_m         = 0x0000007f,
 118
 119         ETHARC_pro_b            = 0,
 120         ETHARC_pro_m            = 0x00000001,
 121         ETHARC_am_b             = 1,
 122         ETHARC_am_m             = 0x00000002,
 123         ETHARC_afm_b            = 2,
 124         ETHARC_afm_m            = 0x00000004,
 125         ETHARC_ab_b             = 3,
 126         ETHARC_ab_m             = 0x00000008,
 127
 128         ETHSAL_byte5_b          = 0,
 129         ETHSAL_byte5_m          = 0x000000ff,
 130         ETHSAL_byte4_b          = 8,
 131         ETHSAL_byte4_m          = 0x0000ff00,
 132         ETHSAL_byte3_b          = 16,
 133         ETHSAL_byte3_m          = 0x00ff0000,
 134         ETHSAL_byte2_b          = 24,
 135         ETHSAL_byte2_m          = 0xff000000,
 136
 137         ETHSAH_byte1_b          = 0,
 138         ETHSAH_byte1_m          = 0x000000ff,
 139         ETHSAH_byte0_b          = 8,
 140         ETHSAH_byte0_m          = 0x0000ff00,
 141
 142         ETHGPF_ptv_b            = 0,
 143         ETHGPF_ptv_m            = 0x0000ffff,
 144
 145         ETHPFS_pfd_b            = 0,
 146         ETHPFS_pfd_m            = 0x00000001,
 147
 148         ETHCFSA0_cfsa4_b        = 0,
 149         ETHCFSA0_cfsa4_m        = 0x000000ff,
 150         ETHCFSA0_cfsa5_b        = 8,
 151         ETHCFSA0_cfsa5_m        = 0x0000ff00,
 152
 153         ETHCFSA1_cfsa2_b        = 0,
 154         ETHCFSA1_cfsa2_m        = 0x000000ff,
 155         ETHCFSA1_cfsa3_b        = 8,
 156         ETHCFSA1_cfsa3_m        = 0x0000ff00,
 157
 158         ETHCFSA2_cfsa0_b        = 0,
 159         ETHCFSA2_cfsa0_m        = 0x000000ff,
 160         ETHCFSA2_cfsa1_b        = 8,
 161         ETHCFSA2_cfsa1_m        = 0x0000ff00,
 162
 163         ETHMAC1_re_b            = 0,
 164         ETHMAC1_re_m            = 0x00000001,
 165         ETHMAC1_paf_b           = 1,
 166         ETHMAC1_paf_m           = 0x00000002,
 167         ETHMAC1_rfc_b           = 2,
 168         ETHMAC1_rfc_m           = 0x00000004,
 169         ETHMAC1_tfc_b           = 3,
 170         ETHMAC1_tfc_m           = 0x00000008,
 171         ETHMAC1_lb_b            = 4,
 172         ETHMAC1_lb_m            = 0x00000010,
 173         ETHMAC1_mr_b            = 31,
 174         ETHMAC1_mr_m            = 0x80000000,
 175
 176         ETHMAC2_fd_b            = 0,
 177         ETHMAC2_fd_m            = 0x00000001,
 178         ETHMAC2_flc_b           = 1,
 179         ETHMAC2_flc_m           = 0x00000002,
 180         ETHMAC2_hfe_b           = 2,
 181         ETHMAC2_hfe_m           = 0x00000004,
 182         ETHMAC2_dc_b            = 3,
 183         ETHMAC2_dc_m            = 0x00000008,
 184         ETHMAC2_cen_b           = 4,
 185         ETHMAC2_cen_m           = 0x00000010,
 186         ETHMAC2_pe_b            = 5,
 187         ETHMAC2_pe_m            = 0x00000020,
 188         ETHMAC2_vpe_b           = 6,
 189         ETHMAC2_vpe_m           = 0x00000040,
 190         ETHMAC2_ape_b           = 7,
 191         ETHMAC2_ape_m           = 0x00000080,
 192         ETHMAC2_ppe_b           = 8,
 193         ETHMAC2_ppe_m           = 0x00000100,
 194         ETHMAC2_lpe_b           = 9,
 195         ETHMAC2_lpe_m           = 0x00000200,
 196         ETHMAC2_nb_b            = 12,
 197         ETHMAC2_nb_m            = 0x00001000,
 198         ETHMAC2_bp_b            = 13,
 199         ETHMAC2_bp_m            = 0x00002000,
 200         ETHMAC2_ed_b            = 14,
 201         ETHMAC2_ed_m            = 0x00004000,
 202
 203         ETHIPGT_ipgt_b          = 0,
 204         ETHIPGT_ipgt_m          = 0x0000007f,
 205
 206         ETHIPGR_ipgr2_b         = 0,
 207         ETHIPGR_ipgr2_m         = 0x0000007f,
 208         ETHIPGR_ipgr1_b         = 8,
 209         ETHIPGR_ipgr1_m         = 0x00007f00,
 210
 211         ETHCLRT_maxret_b        = 0,
 212         ETHCLRT_maxret_m        = 0x0000000f,
 213         ETHCLRT_colwin_b        = 8,
 214         ETHCLRT_colwin_m        = 0x00003f00,
 215
 216         ETHMAXF_maxf_b          = 0,
 217         ETHMAXF_maxf_m          = 0x0000ffff,
 218
 219         ETHMTEST_tb_b           = 2,
 220         ETHMTEST_tb_m           = 0x00000004,
 221
 222         ETHMCP_div_b            = 0,
 223         ETHMCP_div_m            = 0x000000ff,
 224
 225         MIIMCFG_rsv_b           = 0,
 226         MIIMCFG_rsv_m           = 0x0000000c,
 227
 228         MIIMCMD_rd_b            = 0,
 229         MIIMCMD_rd_m            = 0x00000001,
 230         MIIMCMD_scn_b           = 1,
 231         MIIMCMD_scn_m           = 0x00000002,
 232
 233         MIIMADDR_regaddr_b      = 0,
 234         MIIMADDR_regaddr_m      = 0x0000001f,
 235         MIIMADDR_phyaddr_b      = 8,
 236         MIIMADDR_phyaddr_m      = 0x00001f00,
 237
 238         MIIMWTD_wdata_b         = 0,
 239         MIIMWTD_wdata_m         = 0x0000ffff,
 240
 241         MIIMRDD_rdata_b         = 0,
 242         MIIMRDD_rdata_m         = 0x0000ffff,
 243
 244         MIIMIND_bsy_b           = 0,
 245         MIIMIND_bsy_m           = 0x00000001,
 246         MIIMIND_scn_b           = 1,
 247         MIIMIND_scn_m           = 0x00000002,
 248         MIIMIND_nv_b            = 2,
 249         MIIMIND_nv_m            = 0x00000004,
 250
 251 } ;
 252
 253 /*
 254  * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
 255  */
 256 enum
 257 {
 258         ETHRX_fd_b              = 0,
 259         ETHRX_fd_m              = 0x00000001,
 260         ETHRX_ld_b              = 1,
 261         ETHRX_ld_m              = 0x00000002,
 262         ETHRX_rok_b             = 2,
 263         ETHRX_rok_m             = 0x00000004,
 264         ETHRX_fm_b              = 3,
 265         ETHRX_fm_m              = 0x00000008,
 266         ETHRX_mp_b              = 4,
 267         ETHRX_mp_m              = 0x00000010,
 268         ETHRX_bp_b              = 5,
 269         ETHRX_bp_m              = 0x00000020,
 270         ETHRX_vlt_b             = 6,
 271         ETHRX_vlt_m             = 0x00000040,
 272         ETHRX_cf_b              = 7,
 273         ETHRX_cf_m              = 0x00000080,
 274         ETHRX_ovr_b             = 8,
 275         ETHRX_ovr_m             = 0x00000100,
 276         ETHRX_crc_b             = 9,
 277         ETHRX_crc_m             = 0x00000200,
 278         ETHRX_cv_b              = 10,
 279         ETHRX_cv_m              = 0x00000400,
 280         ETHRX_db_b              = 11,
 281         ETHRX_db_m              = 0x00000800,
 282         ETHRX_le_b              = 12,
 283         ETHRX_le_m              = 0x00001000,
 284         ETHRX_lor_b             = 13,
 285         ETHRX_lor_m             = 0x00002000,
 286         ETHRX_ces_b             = 14,
 287         ETHRX_ces_m             = 0x00004000,
 288         ETHRX_length_b          = 16,
 289         ETHRX_length_m          = 0xffff0000,
 290
 291         ETHTX_fd_b              = 0,
 292         ETHTX_fd_m              = 0x00000001,
 293         ETHTX_ld_b              = 1,
 294         ETHTX_ld_m              = 0x00000002,
 295         ETHTX_oen_b             = 2,
 296         ETHTX_oen_m             = 0x00000004,
 297         ETHTX_pen_b             = 3,
 298         ETHTX_pen_m             = 0x00000008,
 299         ETHTX_cen_b             = 4,
 300         ETHTX_cen_m             = 0x00000010,
 301         ETHTX_hen_b             = 5,
 302         ETHTX_hen_m             = 0x00000020,
 303         ETHTX_tok_b             = 6,
 304         ETHTX_tok_m             = 0x00000040,
 305         ETHTX_mp_b              = 7,
 306         ETHTX_mp_m              = 0x00000080,
 307         ETHTX_bp_b              = 8,
 308         ETHTX_bp_m              = 0x00000100,
 309         ETHTX_und_b             = 9,
 310         ETHTX_und_m             = 0x00000200,
 311         ETHTX_of_b              = 10,
 312         ETHTX_of_m              = 0x00000400,
 313         ETHTX_ed_b              = 11,
 314         ETHTX_ed_m              = 0x00000800,
 315         ETHTX_ec_b              = 12,
 316         ETHTX_ec_m              = 0x00001000,
 317         ETHTX_lc_b              = 13,
 318         ETHTX_lc_m              = 0x00002000,
 319         ETHTX_td_b              = 14,
 320         ETHTX_td_m              = 0x00004000,
 321         ETHTX_crc_b             = 15,
 322         ETHTX_crc_m             = 0x00008000,
 323         ETHTX_le_b              = 16,
 324         ETHTX_le_m              = 0x00010000,
 325         ETHTX_cc_b              = 17,
 326         ETHTX_cc_m              = 0x001E0000,
 327 } ;
 328
 329 #endif  // __IDT_ETH_H__
 330
 331
 332
 333