target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_rst.h

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *   Reset register definitions.
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb.
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #ifndef __IDT_RST_H__
  40 #define __IDT_RST_H__
  41
  42 enum
  43 {
  44         RST0_PhysicalAddress    = 0x18000000,
  45         RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
  46
  47         RST0_VirtualAddress     = 0xb8000000,
  48         RST_VirtualAddress      = RST0_VirtualAddress,          // Default
  49 } ;
  50
  51 typedef struct RST_s
  52 {
  53         u32     filler [0x0006] ;
  54         u32     sysid ;
  55         u32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
  56         u32     reset ;
  57         u32     bcv ;
  58         u32     cea ;
  59 } volatile * RST_t ;
  60
  61 enum
  62 {
  63         SYSID_rev_b             = 0,
  64         SYSID_rev_m             = 0x000000ff,
  65         SYSID_imp_b             = 8,
  66         SYSID_imp_m             = 0x000fff00,
  67         SYSID_vendor_b          = 8,
  68         SYSID_vendor_m          = 0xfff00000,
  69
  70         BCV_pll_b               = 0,
  71         BCV_pll_m               = 0x0000000f,
  72                 BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
  73                 BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
  74                 BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
  75                 BCV_pll_SlowMul5_v      = 0x3,  // PCLK=5*CLK.
  76                 BCV_pll_Mul5_v          = 0x4,  // PCLK=5*CLK.
  77                 BCV_pll_SlowMul6_v      = 0x5,  // PCLK=6*CLK.
  78                 BCV_pll_Mul6_v          = 0x6,  // PCLK=6*CLK.
  79                 BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
  80                 BCV_pll_Mul10_v         = 0x8,  // PCLK=10*CLK.
  81                 BCV_pll_Res9_v          = 0x9,
  82                 BCV_pll_Res10_v         = 0xa,
  83                 BCV_pll_Res11_v         = 0xb,
  84                 BCV_pll_Res12_v         = 0xc,
  85                 BCV_pll_Res13_v         = 0xd,
  86                 BCV_pll_Res14_v         = 0xe,
  87                 BCV_pll_Res15_v         = 0xf,
  88         BCV_clkDiv_b            = 4,
  89         BCV_clkDiv_m            = 0x00000030,
  90                 BCV_clkDiv_Div1_v       = 0x0,
  91                 BCV_clkDiv_Div2_v       = 0x1,
  92                 BCV_clkDiv_Div4_v       = 0x2,
  93                 BCV_clkDiv_Res3_v       = 0x3,
  94         BCV_bigEndian_b         = 6,
  95         BCV_bigEndian_m         = 0x00000040,
  96         BCV_resetFast_b         = 7,
  97         BCV_resetFast_m         = 0x00000080,
  98         BCV_pciMode_b           = 8,
  99         BCV_pciMode_m           = 0x00000700,
 100                 BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
 101                 BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
 102                 BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
 103                 BCV_pciMode_external_v  = 3,    // host, external arbiter.
 104                 BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
 105                 BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
 106                 BCV_pciMode_res6_v      = 6,
 107                 BCV_pciMode_res7_v      = 7,
 108         BCV_watchDisable_b      = 11,
 109         BCV_watchDisable_m      = 0x00000800,
 110         BCV_res12_b             = 12,
 111         BCV_res12_m             = 0x00001000,
 112         BCV_res13_b             = 13,
 113         BCV_res13_m             = 0x00002000,
 114         BCV_res14_b             = 14,
 115         BCV_res14_m             = 0x00004000,
 116         BCV_res15_b             = 15,
 117         BCV_res15_m             = 0x00008000,
 118 } ;
 119 #endif  // __IDT_RST_H__