6eb4e5fc0392654f1111c8d79df0fefd2ceefb55
1 /**************************************************************************
3 * BRIEF MODULE DESCRIPTION
4 * UART register definitions
6 * Copyright 2004 IDT Inc. (rischelp@idt.com)
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 **************************************************************************
36 **************************************************************************
39 #ifndef __IDT_UART_H__
40 #define __IDT_UART_H__
44 UART0_PhysicalAddress
= 0x1c000000,
45 UART_PhysicalAddress
= UART0_PhysicalAddress
, // Default
47 UART0_VirtualAddress
= 0xbc000000,
48 UART_VirtualAddress
= UART0_VirtualAddress
, // Default
52 * Register definitions are in bytes so we can handle endian problems.
59 u32
const uartrb
; // 0x00 - DLAB=0, read.
60 u32 uartth
; // 0x00 - DLAB=0, write.
61 u32 uartdll
; // 0x00 - DLAB=1, read/write.
66 u32 uartie
; // 0x04 - DLAB=0, read/write.
67 u32 uartdlh
; // 0x04 - DLAB=1, read/write.
71 u32
const uartii
; // 0x08 - DLAB=0, read.
72 u32 uartfc
; // 0x08 - DLAB=0, write.
83 typedef u32
volatile *UARTRR_t
;
88 UARTIE_rda_m
= 0x00000001,
90 UARTIE_the_m
= 0x00000002,
92 UARTIE_rls_m
= 0x00000004,
94 UARTIE_ems_m
= 0x00000008,
97 UARTII_pi_m
= 0x00000001,
99 UARTII_iid_m
= 0x0000000e,
100 UARTII_iid_ms_v
= 0, // Modem stat-CTS,DSR,RI or DCD.
101 UARTII_iid_thre_v
= 1, // Trans. Holding Reg. empty.
102 UARTII_iid_rda_v
= 2, // Receive data available
103 UARTII_iid_rls_v
= 3, // Overrun, parity, etc, error.
104 UARTII_iid_res4_v
= 4, // reserved.
105 UARTII_iid_res5_v
= 5, // reserved.
106 UARTII_iid_cto_v
= 6, // Character timeout.
107 UARTII_iid_res7_v
= 7, // reserved.
110 UARTFC_en_m
= 0x00000001,
112 UARTFC_rr_m
= 0x00000002,
114 UARTFC_tr_m
= 0x00000004,
116 UARTFC_dms_m
= 0x00000008,
118 UARTFC_rt_m
= 0x000000c0,
119 UARTFC_rt_1Byte_v
= 0,
120 UARTFC_rt_4Byte_v
= 1,
121 UARTFC_rt_8Byte_v
= 2,
122 UARTFC_rt_14Byte_v
= 3,
125 UARTLC_wls_m
= 0x00000003,
126 UARTLC_wls_5Bits_v
= 0,
127 UARTLC_wls_6Bits_v
= 1,
128 UARTLC_wls_7Bits_v
= 2,
129 UARTLC_wls_8Bits_v
= 3,
131 UARTLC_stb_m
= 0x00000004,
133 UARTLC_pen_m
= 0x00000008,
135 UARTLC_eps_m
= 0x00000010,
137 UARTLC_sp_m
= 0x00000020,
139 UARTLC_sb_m
= 0x00000040,
141 UARTLC_dlab_m
= 0x00000080,
144 UARTMC_dtr_m
= 0x00000001,
146 UARTMC_rts_m
= 0x00000002,
148 UARTMC_o1_m
= 0x00000004,
150 UARTMC_o2_m
= 0x00000008,
152 UARTMC_lp_m
= 0x00000010,
155 UARTLS_dr_m
= 0x00000001,
157 UARTLS_oe_m
= 0x00000002,
159 UARTLS_pe_m
= 0x00000004,
161 UARTLS_fe_m
= 0x00000008,
163 UARTLS_bi_m
= 0x00000010,
165 UARTLS_thr_m
= 0x00000020,
167 UARTLS_te_m
= 0x00000040,
169 UARTLS_rfe_m
= 0x00000080,
172 UARTMS_dcts_m
= 0x00000001,
174 UARTMS_ddsr_m
= 0x00000002,
176 UARTMS_teri_m
= 0x00000004,
178 UARTMS_ddcd_m
= 0x00000008,
180 UARTMS_cts_m
= 0x00000010,
182 UARTMS_dsr_m
= 0x00000020,
184 UARTMS_ri_m
= 0x00000040,
186 UARTMS_dcd_m
= 0x00000080,
189 #endif // __IDT_UART_H__