target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch

   1 From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Thu, 19 Nov 2020 17:43:09 +0200
   4 Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be
   5  exported and referenced in DT
   6
   7 Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
   8 from phandle in DT.
   9
  10 Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  11 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  12 [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
  13 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  14 Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/at91/sama7g5.c | 6 ++++--
  18  1 file changed, 4 insertions(+), 2 deletions(-)
  19
  20 --- a/drivers/clk/at91/sama7g5.c
  21 +++ b/drivers/clk/at91/sama7g5.c
  22 @@ -117,7 +117,8 @@ static const struct {
  23                   .p = "cpupll_fracck",
  24                   .l = &pll_layout_divpmc,
  25                   .t = PLL_TYPE_DIV,
  26 -                 .c = 1, },
  27 +                 .c = 1,
  28 +                 .eid = PMC_CPUPLL, },
  29         },
  30
  31         [PLL_ID_SYS] = {
  32 @@ -131,7 +132,8 @@ static const struct {
  33                   .p = "syspll_fracck",
  34                   .l = &pll_layout_divpmc,
  35                   .t = PLL_TYPE_DIV,
  36 -                 .c = 1, },
  37 +                 .c = 1,
  38 +                 .eid = PMC_SYSPLL, },
  39         },
  40
  41         [PLL_ID_DDR] = {