target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch

   1 From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 19 Nov 2020 17:43:15 +0200
   4 Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher
   5  than 1GHz
   6
   7 Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
   8 than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
   9 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
  10
  11 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  12 Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
  13 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  14 ---
  15  drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------
  16  1 file changed, 47 insertions(+), 14 deletions(-)
  17
  18 diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
  19 index 29d9781e6712..e0c4d2eb9f59 100644
  20 --- a/drivers/clk/at91/sama7g5.c
  21 +++ b/drivers/clk/at91/sama7g5.c
  22 @@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_layout_divio = {
  23         .endiv_shift    = 30,
  24  };
  25
  26 +/*
  27 + * CPU PLL output range.
  28 + * Notice: The upper limit has been setup to 1000000002 due to hardware
  29 + * block which cannot output exactly 1GHz.
  30 + */
  31 +static const struct clk_range cpu_pll_outputs[] = {
  32 +       { .min = 2343750, .max = 1000000002 },
  33 +};
  34 +
  35 +/* PLL output range. */
  36 +static const struct clk_range pll_outputs[] = {
  37 +       { .min = 2343750, .max = 1200000000 },
  38 +};
  39 +
  40 +/* CPU PLL characteristics. */
  41 +static const struct clk_pll_characteristics cpu_pll_characteristics = {
  42 +       .input = { .min = 12000000, .max = 50000000 },
  43 +       .num_output = ARRAY_SIZE(cpu_pll_outputs),
  44 +       .output = cpu_pll_outputs,
  45 +};
  46 +
  47 +/* PLL characteristics. */
  48 +static const struct clk_pll_characteristics pll_characteristics = {
  49 +       .input = { .min = 12000000, .max = 50000000 },
  50 +       .num_output = ARRAY_SIZE(pll_outputs),
  51 +       .output = pll_outputs,
  52 +};
  53 +
  54  /**
  55   * PLL clocks description
  56   * @n:         clock name
  57   * @p:         clock parent
  58   * @l:         clock layout
  59 + * @c:         clock characteristics
  60   * @t:         clock type
  61   * @f:         clock flags
  62   * @eid:       export index in sama7g5->chws[] array
  63 @@ -102,6 +131,7 @@ static const struct {
  64         const char *n;
  65         const char *p;
  66         const struct clk_pll_layout *l;
  67 +       const struct clk_pll_characteristics *c;
  68         unsigned long f;
  69         u8 t;
  70         u8 eid;
  71 @@ -110,6 +140,7 @@ static const struct {
  72                 { .n = "cpupll_fracck",
  73                   .p = "mainck",
  74                   .l = &pll_layout_frac,
  75 +                 .c = &cpu_pll_characteristics,
  76                   .t = PLL_TYPE_FRAC,
  77                    /*
  78                     * This feeds cpupll_divpmcck which feeds CPU. It should
  79 @@ -120,6 +151,7 @@ static const struct {
  80                 { .n = "cpupll_divpmcck",
  81                   .p = "cpupll_fracck",
  82                   .l = &pll_layout_divpmc,
  83 +                 .c = &cpu_pll_characteristics,
  84                   .t = PLL_TYPE_DIV,
  85                    /* This feeds CPU. It should not be disabled. */
  86                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  87 @@ -130,6 +162,7 @@ static const struct {
  88                 { .n = "syspll_fracck",
  89                   .p = "mainck",
  90                   .l = &pll_layout_frac,
  91 +                 .c = &pll_characteristics,
  92                   .t = PLL_TYPE_FRAC,
  93                    /*
  94                     * This feeds syspll_divpmcck which may feed critial parts
  95 @@ -141,6 +174,7 @@ static const struct {
  96                 { .n = "syspll_divpmcck",
  97                   .p = "syspll_fracck",
  98                   .l = &pll_layout_divpmc,
  99 +                 .c = &pll_characteristics,
 100                   .t = PLL_TYPE_DIV,
 101                    /*
 102                     * This may feed critial parts of the systems like timers.
 103 @@ -154,6 +188,7 @@ static const struct {
 104                 { .n = "ddrpll_fracck",
 105                   .p = "mainck",
 106                   .l = &pll_layout_frac,
 107 +                 .c = &pll_characteristics,
 108                   .t = PLL_TYPE_FRAC,
 109                    /*
 110                     * This feeds ddrpll_divpmcck which feeds DDR. It should not
 111 @@ -164,6 +199,7 @@ static const struct {
 112                 { .n = "ddrpll_divpmcck",
 113                   .p = "ddrpll_fracck",
 114                   .l = &pll_layout_divpmc,
 115 +                 .c = &pll_characteristics,
 116                   .t = PLL_TYPE_DIV,
 117                    /* This feeds DDR. It should not be disabled. */
 118                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 119 @@ -173,12 +209,14 @@ static const struct {
 120                 { .n = "imgpll_fracck",
 121                   .p = "mainck",
 122                   .l = &pll_layout_frac,
 123 +                 .c = &pll_characteristics,
 124                   .t = PLL_TYPE_FRAC,
 125                   .f = CLK_SET_RATE_GATE, },
 126
 127                 { .n = "imgpll_divpmcck",
 128                   .p = "imgpll_fracck",
 129                   .l = &pll_layout_divpmc,
 130 +                 .c = &pll_characteristics,
 131                   .t = PLL_TYPE_DIV,
 132                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 133                        CLK_SET_RATE_PARENT, },
 134 @@ -188,12 +226,14 @@ static const struct {
 135                 { .n = "baudpll_fracck",
 136                   .p = "mainck",
 137                   .l = &pll_layout_frac,
 138 +                 .c = &pll_characteristics,
 139                   .t = PLL_TYPE_FRAC,
 140                   .f = CLK_SET_RATE_GATE, },
 141
 142                 { .n = "baudpll_divpmcck",
 143                   .p = "baudpll_fracck",
 144                   .l = &pll_layout_divpmc,
 145 +                 .c = &pll_characteristics,
 146                   .t = PLL_TYPE_DIV,
 147                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 148                        CLK_SET_RATE_PARENT, },
 149 @@ -203,12 +243,14 @@ static const struct {
 150                 { .n = "audiopll_fracck",
 151                   .p = "main_xtal",
 152                   .l = &pll_layout_frac,
 153 +                 .c = &pll_characteristics,
 154                   .t = PLL_TYPE_FRAC,
 155                   .f = CLK_SET_RATE_GATE, },
 156
 157                 { .n = "audiopll_divpmcck",
 158                   .p = "audiopll_fracck",
 159                   .l = &pll_layout_divpmc,
 160 +                 .c = &pll_characteristics,
 161                   .t = PLL_TYPE_DIV,
 162                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 163                        CLK_SET_RATE_PARENT,
 164 @@ -217,6 +259,7 @@ static const struct {
 165                 { .n = "audiopll_diviock",
 166                   .p = "audiopll_fracck",
 167                   .l = &pll_layout_divio,
 168 +                 .c = &pll_characteristics,
 169                   .t = PLL_TYPE_DIV,
 170                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 171                        CLK_SET_RATE_PARENT,
 172 @@ -227,12 +270,14 @@ static const struct {
 173                 { .n = "ethpll_fracck",
 174                   .p = "main_xtal",
 175                   .l = &pll_layout_frac,
 176 +                 .c = &pll_characteristics,
 177                   .t = PLL_TYPE_FRAC,
 178                   .f = CLK_SET_RATE_GATE, },
 179
 180                 { .n = "ethpll_divpmcck",
 181                   .p = "ethpll_fracck",
 182                   .l = &pll_layout_divpmc,
 183 +                 .c = &pll_characteristics,
 184                   .t = PLL_TYPE_DIV,
 185                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 186                        CLK_SET_RATE_PARENT, },
 187 @@ -793,18 +838,6 @@ static const struct {
 188           .pp_chg_id = INT_MIN, },
 189  };
 190
 191 -/* PLL output range. */
 192 -static const struct clk_range pll_outputs[] = {
 193 -       { .min = 2343750, .max = 1200000000 },
 194 -};
 195 -
 196 -/* PLL characteristics. */
 197 -static const struct clk_pll_characteristics pll_characteristics = {
 198 -       .input = { .min = 12000000, .max = 50000000 },
 199 -       .num_output = ARRAY_SIZE(pll_outputs),
 200 -       .output = pll_outputs,
 201 -};
 202 -
 203  /* MCK0 characteristics. */
 204  static const struct clk_master_characteristics mck0_characteristics = {
 205         .output = { .min = 50000000, .max = 200000000 },
 206 @@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 207                                 hw = sam9x60_clk_register_frac_pll(regmap,
 208                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 209                                         sama7g5_plls[i][j].p, parent_hw, i,
 210 -                                       &pll_characteristics,
 211 +                                       sama7g5_plls[i][j].c,
 212                                         sama7g5_plls[i][j].l,
 213                                         sama7g5_plls[i][j].f);
 214                                 break;
 215 @@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 216                                 hw = sam9x60_clk_register_div_pll(regmap,
 217                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 218                                         sama7g5_plls[i][j].p, i,
 219 -                                       &pll_characteristics,
 220 +                                       sama7g5_plls[i][j].c,
 221                                         sama7g5_plls[i][j].l,
 222                                         sama7g5_plls[i][j].f);
 223                                 break;
 224 --
 225 2.32.0
 226