target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch

   1 From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Fri, 13 Nov 2020 15:24:29 +0200
   4 Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on
   5  last PIO bank
   6
   7 Some products, like sama7g5, do not have a full last bank of PIO lines.
   8 In this case for example, sama7g5 only has 8 lines for the PE bank.
   9 PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
  10 To cope with this situation, added a data attribute that is product dependent,
  11 to specify the number of lines of the last bank.
  12 In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
  13 adjust the total number of lines accordingly.
  14 This will avoid advertising 160 lines instead of the actual 136, as this
  15 product supports, and to avoid reading/writing to invalid register addresses.
  16
  17 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  18 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
  19 Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com
  20 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  21 ---
  22  drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++--
  23  1 file changed, 16 insertions(+), 2 deletions(-)
  24
  25 diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
  26 index 578b387100d9..d267367d94b9 100644
  27 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
  28 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
  29 @@ -71,8 +71,15 @@
  30  /* Custom pinconf parameters */
  31  #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH        (PIN_CONFIG_END + 1)
  32
  33 +/**
  34 + * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
  35 + * @nbanks: number of PIO banks
  36 + * @last_bank_count: number of lines in the last bank (can be less than
  37 + *     the rest of the banks).
  38 + */
  39  struct atmel_pioctrl_data {
  40         unsigned nbanks;
  41 +       unsigned last_bank_count;
  42  };
  43
  44  struct atmel_group {
  45 @@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pctrl_pm_ops = {
  46   * We can have up to 16 banks.
  47   */
  48  static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  49 -       .nbanks         = 4,
  50 +       .nbanks                 = 4,
  51 +       .last_bank_count        = ATMEL_PIO_NPINS_PER_BANK,
  52  };
  53
  54  static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
  55 -       .nbanks         = 5,
  56 +       .nbanks                 = 5,
  57 +       .last_bank_count        = 8, /* sama7g5 has only PE0 to PE7 */
  58  };
  59
  60  static const struct of_device_id atmel_pctrl_of_match[] = {
  61 @@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
  62         atmel_pioctrl_data = match->data;
  63         atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
  64         atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
  65 +       /* if last bank has limited number of pins, adjust accordingly */
  66 +       if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
  67 +               atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
  68 +               atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
  69 +       }
  70
  71         atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
  72         if (IS_ERR(atmel_pioctrl->reg_base))
  73 --
  74 2.32.0
  75