1 From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001
2 From: Eugen Hristev <eugen.hristev@microchip.com>
3 Date: Fri, 16 Oct 2020 12:38:50 +0300
4 Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based
7 SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC.
8 Added support by a new compatible and a layout struct that copes
9 to the specific version considering the compatible string.
10 Only the differences in register map are present in the layout struct.
11 I reworked the register access for this part that has the differences.
12 Also the Source/Destination Interface bits are no longer valid for this
13 variant of the XDMAC. Thus, the layout also has a bool for specifying
14 whether these bits are required or not.
16 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
17 Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com
18 Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++----------
21 1 file changed, 84 insertions(+), 26 deletions(-)
23 --- a/drivers/dma/at_xdmac.c
24 +++ b/drivers/dma/at_xdmac.c
26 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
27 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
28 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
29 -#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
30 -#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
31 -#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
32 -#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
33 -#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
34 -#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
35 -#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
36 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
38 /* Channel relative registers offsets */
40 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
41 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
43 -#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
45 /* Microblock control members */
46 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
47 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
48 @@ -180,6 +171,27 @@ enum atc_status {
49 AT_XDMAC_CHAN_IS_PAUSED,
52 +struct at_xdmac_layout {
53 + /* Global Channel Read Suspend Register */
55 + /* Global Write Suspend Register */
57 + /* Global Channel Read Write Suspend Register */
59 + /* Global Channel Read Write Resume Register */
61 + /* Global Channel Software Request Register */
63 + /* Global channel Software Request Status Register */
65 + /* Global Channel Software Flush Request Register */
67 + /* Channel reg base */
68 + u8 chan_cc_reg_base;
69 + /* Source/Destination Interface must be specified or not */
73 /* ----- Channels ----- */
74 struct at_xdmac_chan {
76 @@ -213,6 +225,7 @@ struct at_xdmac {
79 struct dma_pool *at_xdmac_desc_pool;
80 + const struct at_xdmac_layout *layout;
81 struct at_xdmac_chan chan[];
84 @@ -245,9 +258,33 @@ struct at_xdmac_desc {
85 struct list_head xfer_node;
86 } __aligned(sizeof(u64));
88 +static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
96 + .chan_cc_reg_base = 0x50,
100 +static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
108 + .chan_cc_reg_base = 0x60,
112 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
114 - return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
115 + return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);
118 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
119 @@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a
120 first->active_xfer = true;
122 /* Tell xdmac where to get the first descriptor. */
123 - reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
124 - | AT_XDMAC_CNDA_NDAIF(atchan->memif);
125 + reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);
126 + if (atxdmac->layout->sdif)
127 + reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);
129 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
132 @@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st
133 enum dma_transfer_direction direction)
135 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
136 + struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
139 if (direction == DMA_DEV_TO_MEM) {
140 @@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st
141 AT91_XDMAC_DT_PERID(atchan->perid)
142 | AT_XDMAC_CC_DAM_INCREMENTED_AM
143 | AT_XDMAC_CC_SAM_FIXED_AM
144 - | AT_XDMAC_CC_DIF(atchan->memif)
145 - | AT_XDMAC_CC_SIF(atchan->perif)
146 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
147 | AT_XDMAC_CC_DSYNC_PER2MEM
148 | AT_XDMAC_CC_MBSIZE_SIXTEEN
149 | AT_XDMAC_CC_TYPE_PER_TRAN;
150 + if (atxdmac->layout->sdif)
151 + atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |
152 + AT_XDMAC_CC_SIF(atchan->perif);
154 csize = ffs(atchan->sconfig.src_maxburst) - 1;
156 dev_err(chan2dev(chan), "invalid src maxburst value\n");
157 @@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st
158 AT91_XDMAC_DT_PERID(atchan->perid)
159 | AT_XDMAC_CC_DAM_FIXED_AM
160 | AT_XDMAC_CC_SAM_INCREMENTED_AM
161 - | AT_XDMAC_CC_DIF(atchan->perif)
162 - | AT_XDMAC_CC_SIF(atchan->memif)
163 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
164 | AT_XDMAC_CC_DSYNC_MEM2PER
165 | AT_XDMAC_CC_MBSIZE_SIXTEEN
166 | AT_XDMAC_CC_TYPE_PER_TRAN;
167 + if (atxdmac->layout->sdif)
168 + atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |
169 + AT_XDMAC_CC_SIF(atchan->memif);
171 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
173 dev_err(chan2dev(chan), "invalid src maxburst value\n");
174 @@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d
175 * ERRATA: Even if useless for memory transfers, the PERID has to not
176 * match the one of another channel. If not, it could lead to spurious
178 + * For SAMA7G5x case, the SIF and DIF fields are no longer used.
179 + * Thus, no need to have the SIF/DIF interfaces here.
180 + * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
183 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
184 - | AT_XDMAC_CC_DIF(0)
185 - | AT_XDMAC_CC_SIF(0)
186 | AT_XDMAC_CC_MBSIZE_SIXTEEN
187 | AT_XDMAC_CC_TYPE_MEM_TRAN;
189 @@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan
190 * ERRATA: Even if useless for memory transfers, the PERID has to not
191 * match the one of another channel. If not, it could lead to spurious
193 + * For SAMA7G5x case, the SIF and DIF fields are no longer used.
194 + * Thus, no need to have the SIF/DIF interfaces here.
195 + * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
198 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
199 | AT_XDMAC_CC_DAM_INCREMENTED_AM
200 | AT_XDMAC_CC_SAM_INCREMENTED_AM
201 - | AT_XDMAC_CC_DIF(0)
202 - | AT_XDMAC_CC_SIF(0)
203 | AT_XDMAC_CC_MBSIZE_SIXTEEN
204 | AT_XDMAC_CC_TYPE_MEM_TRAN;
205 unsigned long irqflags;
206 @@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me
207 * ERRATA: Even if useless for memory transfers, the PERID has to not
208 * match the one of another channel. If not, it could lead to spurious
210 + * For SAMA7G5x case, the SIF and DIF fields are no longer used.
211 + * Thus, no need to have the SIF/DIF interfaces here.
212 + * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
215 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
216 | AT_XDMAC_CC_DAM_UBS_AM
217 | AT_XDMAC_CC_SAM_INCREMENTED_AM
218 - | AT_XDMAC_CC_DIF(0)
219 - | AT_XDMAC_CC_SIF(0)
220 | AT_XDMAC_CC_MBSIZE_SIXTEEN
221 | AT_XDMAC_CC_MEMSET_HW_MODE
222 | AT_XDMAC_CC_TYPE_MEM_TRAN;
223 @@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan
224 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
225 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
226 if ((desc->lld.mbr_cfg & mask) == value) {
227 - at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
228 + at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
229 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
232 @@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan
233 * FIFO flush ensures that data are really written.
235 if ((desc->lld.mbr_cfg & mask) == value) {
236 - at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
237 + at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
238 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
241 @@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct
244 spin_lock_irqsave(&atchan->lock, flags);
245 - at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
246 + at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
247 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
248 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
250 @@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct
254 - at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
255 + at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
256 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
257 spin_unlock_irqrestore(&atchan->lock, flags);
259 @@ -1992,6 +2042,10 @@ static int at_xdmac_probe(struct platfor
260 atxdmac->regs = base;
263 + atxdmac->layout = of_device_get_match_data(&pdev->dev);
264 + if (!atxdmac->layout)
267 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
268 if (IS_ERR(atxdmac->clk)) {
269 dev_err(&pdev->dev, "can't get dma_clk\n");
270 @@ -2134,6 +2188,10 @@ static const struct dev_pm_ops atmel_xdm
271 static const struct of_device_id atmel_xdmac_dt_ids[] = {
273 .compatible = "atmel,sama5d4-dma",
274 + .data = &at_xdmac_sama5d4_layout,
276 + .compatible = "microchip,sama7g5-dma",
277 + .data = &at_xdmac_sama7g5_layout,