target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch

   1 From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Fri, 22 Jan 2021 14:21:35 +0200
   4 Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match
   5  masks
   6
   7 SAMA7G5 has different masks for chip ID and chip version on CIDR
   8 register compared to previous AT91 SoCs. For this the commit adapts
   9 the code for SAMA7G5 addition by introducing 2 new members in
  10 struct at91_soc and fill them properly and also preparing the
  11 parsing of proper DT binding.
  12
  13 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  14 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  15 Link: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com
  16 ---
  17  drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++-------------
  18  drivers/soc/atmel/soc.h |   7 +-
  19  2 files changed, 140 insertions(+), 66 deletions(-)
  20
  21 --- a/drivers/soc/atmel/soc.c
  22 +++ b/drivers/soc/atmel/soc.c
  23 @@ -25,135 +25,200 @@
  24  #define AT91_DBGU_EXID                 0x44
  25  #define AT91_CHIPID_CIDR               0x00
  26  #define AT91_CHIPID_EXID               0x04
  27 -#define AT91_CIDR_VERSION(x)           ((x) & 0x1f)
  28 +#define AT91_CIDR_VERSION(x, m)                ((x) & (m))
  29 +#define AT91_CIDR_VERSION_MASK         GENMASK(4, 0)
  30  #define AT91_CIDR_EXT                  BIT(31)
  31  #define AT91_CIDR_MATCH_MASK           GENMASK(30, 5)
  32
  33  static const struct at91_soc socs[] __initconst = {
  34  #ifdef CONFIG_SOC_AT91RM9200
  35 -       AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
  36 +       AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  37 +                AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
  38  #endif
  39  #ifdef CONFIG_SOC_AT91SAM9
  40 -       AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
  41 -       AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
  42 -       AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
  43 -       AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
  44 -       AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
  45 -       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
  46 +       AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  47 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
  48 +       AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  49 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
  50 +       AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  51 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
  52 +       AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  53 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
  54 +       AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  55 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
  56 +       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  57 +                AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
  58                  "at91sam9m11", "at91sam9g45"),
  59 -       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
  60 +       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  61 +                AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
  62                  "at91sam9m10", "at91sam9g45"),
  63 -       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
  64 +       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  65 +                AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
  66                  "at91sam9g46", "at91sam9g45"),
  67 -       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
  68 +       AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  69 +                AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
  70                  "at91sam9g45", "at91sam9g45"),
  71 -       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
  72 +       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  73 +                AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
  74                  "at91sam9g15", "at91sam9x5"),
  75 -       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
  76 +       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  77 +                AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
  78                  "at91sam9g35", "at91sam9x5"),
  79 -       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
  80 +       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  81 +                AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
  82                  "at91sam9x35", "at91sam9x5"),
  83 -       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
  84 +       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  85 +                AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
  86                  "at91sam9g25", "at91sam9x5"),
  87 -       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
  88 +       AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  89 +                AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
  90                  "at91sam9x25", "at91sam9x5"),
  91 -       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
  92 +       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  93 +                AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
  94                  "at91sam9cn12", "at91sam9n12"),
  95 -       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
  96 +       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
  97 +                AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
  98                  "at91sam9n12", "at91sam9n12"),
  99 -       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
 100 +       AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 101 +                AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
 102                  "at91sam9cn11", "at91sam9n12"),
 103 -       AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
 104 -       AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
 105 -       AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
 106 +       AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 107 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
 108 +       AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 109 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
 110 +       AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 111 +                AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
 112  #endif
 113  #ifdef CONFIG_SOC_SAM9X60
 114 -       AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
 115 +       AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 116 +                AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 117 +                "sam9x60", "sam9x60"),
 118         AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
 119 +                AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 120                  "sam9x60 64MiB DDR2 SiP", "sam9x60"),
 121         AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
 122 +                AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 123                  "sam9x60 128MiB DDR2 SiP", "sam9x60"),
 124         AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
 125 +                AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 126                  "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 127  #endif
 128  #ifdef CONFIG_SOC_SAMA5
 129 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
 130 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 131 +                AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
 132                  "sama5d21", "sama5d2"),
 133 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
 134 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 135 +                AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
 136                  "sama5d22", "sama5d2"),
 137 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
 138 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 139 +                AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
 140                  "sama5d225c 16MiB SiP", "sama5d2"),
 141 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
 142 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 143 +                AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
 144                  "sama5d23", "sama5d2"),
 145 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
 146 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 147 +                AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
 148                  "sama5d24", "sama5d2"),
 149 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
 150 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 151 +                AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
 152                  "sama5d24", "sama5d2"),
 153 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
 154 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 155 +                AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
 156                  "sama5d26", "sama5d2"),
 157 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
 158 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 159 +                AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
 160                  "sama5d27", "sama5d2"),
 161 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
 162 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 163 +                AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
 164                  "sama5d27", "sama5d2"),
 165 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
 166 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 167 +                AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
 168                  "sama5d27c 128MiB SiP", "sama5d2"),
 169 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
 170 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 171 +                AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
 172                  "sama5d27c 64MiB SiP", "sama5d2"),
 173 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
 174 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 175 +                AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
 176                  "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
 177 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
 178 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 179 +                AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
 180                  "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
 181 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
 182 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 183 +                AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
 184                  "sama5d28", "sama5d2"),
 185 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
 186 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 187 +                AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
 188                  "sama5d28", "sama5d2"),
 189 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
 190 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 191 +                AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
 192                  "sama5d28c 128MiB SiP", "sama5d2"),
 193 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
 194 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 195 +                AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
 196                  "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
 197 -       AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
 198 +       AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 199 +                AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
 200                  "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
 201 -       AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
 202 +       AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 203 +                AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
 204                  "sama5d31", "sama5d3"),
 205 -       AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
 206 +       AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 207 +                AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
 208                  "sama5d33", "sama5d3"),
 209 -       AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
 210 +       AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 211 +                AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
 212                  "sama5d34", "sama5d3"),
 213 -       AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
 214 +       AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 215 +                AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
 216                  "sama5d35", "sama5d3"),
 217 -       AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
 218 +       AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 219 +                AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
 220                  "sama5d36", "sama5d3"),
 221 -       AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
 222 +       AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 223 +                AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
 224                  "sama5d41", "sama5d4"),
 225 -       AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
 226 +       AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 227 +                AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
 228                  "sama5d42", "sama5d4"),
 229 -       AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
 230 +       AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 231 +                AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
 232                  "sama5d43", "sama5d4"),
 233 -       AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
 234 +       AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 235 +                AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
 236                  "sama5d44", "sama5d4"),
 237  #endif
 238  #ifdef CONFIG_SOC_SAMV7
 239 -       AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
 240 +       AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 241 +                AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
 242                  "same70q21", "same7"),
 243 -       AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
 244 +       AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 245 +                AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
 246                  "same70q20", "same7"),
 247 -       AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
 248 +       AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK
 249 +                AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
 250                  "same70q19", "same7"),
 251 -       AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
 252 +       AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 253 +                AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
 254                  "sams70q21", "sams7"),
 255 -       AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
 256 +       AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 257 +                AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
 258                  "sams70q20", "sams7"),
 259 -       AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
 260 +       AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 261 +                AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
 262                  "sams70q19", "sams7"),
 263 -       AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
 264 +       AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 265 +                AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
 266                  "samv71q21", "samv7"),
 267 -       AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
 268 +       AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 269 +                AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
 270                  "samv71q20", "samv7"),
 271 -       AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
 272 +       AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 273 +                AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
 274                  "samv71q19", "samv7"),
 275 -       AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
 276 +       AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 277 +                AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
 278                  "samv70q20", "samv7"),
 279 -       AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
 280 +       AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 281 +                AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
 282                  "samv70q19", "samv7"),
 283  #endif
 284         { /* sentinel */ },
 285 @@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro
 286  {
 287         struct device_node *np;
 288         void __iomem *regs;
 289 +       static const struct of_device_id chipids[] = {
 290 +               { .compatible = "atmel,sama5d2-chipid" },
 291 +               { },
 292 +       };
 293
 294 -       np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
 295 +       np = of_find_matching_node(NULL, chipids);
 296         if (!np)
 297                 return -ENODEV;
 298
 299 @@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init
 300         }
 301
 302         for (soc = socs; soc->name; soc++) {
 303 -               if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
 304 +               if (soc->cidr_match != (cidr & soc->cidr_mask))
 305                         continue;
 306
 307                 if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
 308 @@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init
 309         soc_dev_attr->family = soc->family;
 310         soc_dev_attr->soc_id = soc->name;
 311         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
 312 -                                          AT91_CIDR_VERSION(cidr));
 313 +                                          AT91_CIDR_VERSION(cidr, soc->version_mask));
 314         soc_dev = soc_device_register(soc_dev_attr);
 315         if (IS_ERR(soc_dev)) {
 316                 kfree(soc_dev_attr->revision);
 317 @@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init
 318         if (soc->family)
 319                 pr_info("Detected SoC family: %s\n", soc->family);
 320         pr_info("Detected SoC: %s, revision %X\n", soc->name,
 321 -               AT91_CIDR_VERSION(cidr));
 322 +               AT91_CIDR_VERSION(cidr, soc->version_mask));
 323
 324         return soc_dev;
 325  }
 326 --- a/drivers/soc/atmel/soc.h
 327 +++ b/drivers/soc/atmel/soc.h
 328 @@ -16,14 +16,19 @@
 329
 330  struct at91_soc {
 331         u32 cidr_match;
 332 +       u32 cidr_mask;
 333 +       u32 version_mask;
 334         u32 exid_match;
 335         const char *name;
 336         const char *family;
 337  };
 338
 339 -#define AT91_SOC(__cidr, __exid, __name, __family)             \
 340 +#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid,  \
 341 +                __name, __family)                              \
 342         {                                                       \
 343                 .cidr_match = (__cidr),                         \
 344 +               .cidr_mask = (__cidr_mask),                     \
 345 +               .version_mask = (__version_mask),               \
 346                 .exid_match = (__exid),                         \
 347                 .name = (__name),                               \
 348                 .family = (__family),                           \