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[openwrt/staging/jow.git] / target / linux / at91 / patches-5.10 / 185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch
1 From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001
2 From: Eugen Hristev <eugen.hristev@microchip.com>
3 Date: Tue, 13 Apr 2021 12:57:29 +0200
4 Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver
5
6 Add driver for the extended variant of the isc, the microchip XISC
7 present on sama7g5 product.
8
9 [hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists]
10 [hverkuil: made isc_sama7g5_config_csc et al static]
11 [hverkuil: made sama7g5_controller_formats et al static]
12
13 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
14 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
15 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
16 ---
17 drivers/media/platform/Makefile | 1 +
18 drivers/media/platform/atmel/Kconfig | 11 +
19 drivers/media/platform/atmel/Makefile | 2 +
20 drivers/media/platform/atmel/atmel-isc-base.c | 2 +-
21 drivers/media/platform/atmel/atmel-isc-regs.h | 26 +
22 .../media/platform/atmel/atmel-sama7g5-isc.c | 630 ++++++++++++++++++
23 6 files changed, 671 insertions(+), 1 deletion(-)
24 create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c
25
26 diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
27 index 62b6cdc8c730..fd15c76402c9 100644
28 --- a/drivers/media/platform/Makefile
29 +++ b/drivers/media/platform/Makefile
30 @@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vin/
31
32 obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel/
33 obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/
34 +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/
35
36 obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/
37
38 diff --git a/drivers/media/platform/atmel/Kconfig b/drivers/media/platform/atmel/Kconfig
39 index 1850fe7f9360..99b51213f871 100644
40 --- a/drivers/media/platform/atmel/Kconfig
41 +++ b/drivers/media/platform/atmel/Kconfig
42 @@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC
43 This module makes the ATMEL Image Sensor Controller available
44 as a v4l2 device.
45
46 +config VIDEO_ATMEL_XISC
47 + tristate "ATMEL eXtended Image Sensor Controller (XISC) support"
48 + depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API
49 + depends on ARCH_AT91 || COMPILE_TEST
50 + select VIDEOBUF2_DMA_CONTIG
51 + select REGMAP_MMIO
52 + select V4L2_FWNODE
53 + help
54 + This module makes the ATMEL eXtended Image Sensor Controller
55 + available as a v4l2 device.
56 +
57 config VIDEO_ATMEL_ISI
58 tristate "ATMEL Image Sensor Interface (ISI) support"
59 depends on VIDEO_V4L2 && OF
60 diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile
61 index 2dba38994a70..c5c01556c653 100644
62 --- a/drivers/media/platform/atmel/Makefile
63 +++ b/drivers/media/platform/atmel/Makefile
64 @@ -1,5 +1,7 @@
65 # SPDX-License-Identifier: GPL-2.0-only
66 atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o
67 +atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o
68
69 obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
70 obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o
71 +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o
72 diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
73 index dcb321ad10b8..46c6e3e20f33 100644
74 --- a/drivers/media/platform/atmel/atmel-isc-base.c
75 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
76 @@ -600,7 +600,7 @@ static int isc_configure(struct isc_device *isc)
77 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
78 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
79 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
80 - ISC_PFE_CFG0_CCIR656;
81 + ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
82
83 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
84
85 diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
86 index 5f99bf7717c1..d06b72228d4f 100644
87 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
88 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
89 @@ -26,6 +26,7 @@
90 #define ISC_PFE_CFG0_PPOL_LOW BIT(2)
91 #define ISC_PFE_CFG0_CCIR656 BIT(9)
92 #define ISC_PFE_CFG0_CCIR_CRC BIT(10)
93 +#define ISC_PFE_CFG0_MIPI BIT(14)
94
95 #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
96 #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
97 @@ -184,6 +185,8 @@
98 /* ISC Gamma Correction Control Register */
99 #define ISC_GAM_CTRL 0x00000094
100
101 +#define ISC_GAM_CTRL_BIPART BIT(4)
102 +
103 /* ISC_Gamma Correction Blue Entry Register */
104 #define ISC_GAM_BENTRY 0x00000098
105
106 @@ -222,6 +225,8 @@
107
108 /* Offset for CSC register specific to sama5d2 product */
109 #define ISC_SAMA5D2_CSC_OFFSET 0
110 +/* Offset for CSC register specific to sama7g5 product */
111 +#define ISC_SAMA7G5_CSC_OFFSET 0x11c
112
113 /* Color Space Conversion Control Register */
114 #define ISC_CSC_CTRL 0x00000398
115 @@ -246,6 +251,8 @@
116
117 /* Offset for CBC register specific to sama5d2 product */
118 #define ISC_SAMA5D2_CBC_OFFSET 0
119 +/* Offset for CBC register specific to sama7g5 product */
120 +#define ISC_SAMA7G5_CBC_OFFSET 0x11c
121
122 /* Contrast And Brightness Control Register */
123 #define ISC_CBC_CTRL 0x000003b4
124 @@ -261,18 +268,30 @@
125 #define ISC_CBC_CONTRAST 0x000003c0
126 #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)
127
128 +/* Hue Register */
129 +#define ISC_CBCHS_HUE 0x4e0
130 +/* Saturation Register */
131 +#define ISC_CBCHS_SAT 0x4e4
132 +
133 /* Offset for SUB422 register specific to sama5d2 product */
134 #define ISC_SAMA5D2_SUB422_OFFSET 0
135 +/* Offset for SUB422 register specific to sama7g5 product */
136 +#define ISC_SAMA7G5_SUB422_OFFSET 0x124
137 +
138 /* Subsampling 4:4:4 to 4:2:2 Control Register */
139 #define ISC_SUB422_CTRL 0x000003c4
140
141 /* Offset for SUB420 register specific to sama5d2 product */
142 #define ISC_SAMA5D2_SUB420_OFFSET 0
143 +/* Offset for SUB420 register specific to sama7g5 product */
144 +#define ISC_SAMA7G5_SUB420_OFFSET 0x124
145 /* Subsampling 4:2:2 to 4:2:0 Control Register */
146 #define ISC_SUB420_CTRL 0x000003cc
147
148 /* Offset for RLP register specific to sama5d2 product */
149 #define ISC_SAMA5D2_RLP_OFFSET 0
150 +/* Offset for RLP register specific to sama7g5 product */
151 +#define ISC_SAMA7G5_RLP_OFFSET 0x124
152 /* Rounding, Limiting and Packing Configuration Register */
153 #define ISC_RLP_CFG 0x000003d0
154
155 @@ -303,6 +322,8 @@
156
157 /* Offset for HIS register specific to sama5d2 product */
158 #define ISC_SAMA5D2_HIS_OFFSET 0
159 +/* Offset for HIS register specific to sama7g5 product */
160 +#define ISC_SAMA7G5_HIS_OFFSET 0x124
161 /* Histogram Control Register */
162 #define ISC_HIS_CTRL 0x000003d4
163
164 @@ -326,6 +347,8 @@
165
166 /* Offset for DMA register specific to sama5d2 product */
167 #define ISC_SAMA5D2_DMA_OFFSET 0
168 +/* Offset for DMA register specific to sama7g5 product */
169 +#define ISC_SAMA7G5_DMA_OFFSET 0x13c
170
171 /* DMA Configuration Register */
172 #define ISC_DCFG 0x000003e0
173 @@ -376,11 +399,14 @@
174
175 /* Offset for version register specific to sama5d2 product */
176 #define ISC_SAMA5D2_VERSION_OFFSET 0
177 +#define ISC_SAMA7G5_VERSION_OFFSET 0x13c
178 /* Version Register */
179 #define ISC_VERSION 0x0000040c
180
181 /* Offset for version register specific to sama5d2 product */
182 #define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0
183 +/* Offset for version register specific to sama7g5 product */
184 +#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c
185 /* Histogram Entry */
186 #define ISC_HIS_ENTRY 0x00000410
187
188 diff --git a/drivers/media/platform/atmel/atmel-sama7g5-isc.c b/drivers/media/platform/atmel/atmel-sama7g5-isc.c
189 new file mode 100644
190 index 000000000000..f2785131ff56
191 --- /dev/null
192 +++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c
193 @@ -0,0 +1,630 @@
194 +// SPDX-License-Identifier: GPL-2.0
195 +/*
196 + * Microchip eXtended Image Sensor Controller (XISC) driver
197 + *
198 + * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries
199 + *
200 + * Author: Eugen Hristev <eugen.hristev@microchip.com>
201 + *
202 + * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
203 + *
204 + * ISC video pipeline integrates the following submodules:
205 + * PFE: Parallel Front End to sample the camera sensor input stream
206 + * DPC: Defective Pixel Correction with black offset correction, green disparity
207 + * correction and defective pixel correction (3 modules total)
208 + * WB: Programmable white balance in the Bayer domain
209 + * CFA: Color filter array interpolation module
210 + * CC: Programmable color correction
211 + * GAM: Gamma correction
212 + *VHXS: Vertical and Horizontal Scaler
213 + * CSC: Programmable color space conversion
214 + *CBHS: Contrast Brightness Hue and Saturation control
215 + * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling
216 + * RLP: This module performs rounding, range limiting
217 + * and packing of the incoming data
218 + * DMA: This module performs DMA master accesses to write frames to external RAM
219 + * HIS: Histogram module performs statistic counters on the frames
220 + */
221 +
222 +#include <linux/clk.h>
223 +#include <linux/clkdev.h>
224 +#include <linux/clk-provider.h>
225 +#include <linux/delay.h>
226 +#include <linux/interrupt.h>
227 +#include <linux/math64.h>
228 +#include <linux/module.h>
229 +#include <linux/of.h>
230 +#include <linux/of_graph.h>
231 +#include <linux/platform_device.h>
232 +#include <linux/pm_runtime.h>
233 +#include <linux/regmap.h>
234 +#include <linux/videodev2.h>
235 +
236 +#include <media/v4l2-ctrls.h>
237 +#include <media/v4l2-device.h>
238 +#include <media/v4l2-event.h>
239 +#include <media/v4l2-image-sizes.h>
240 +#include <media/v4l2-ioctl.h>
241 +#include <media/v4l2-fwnode.h>
242 +#include <media/v4l2-subdev.h>
243 +#include <media/videobuf2-dma-contig.h>
244 +
245 +#include "atmel-isc-regs.h"
246 +#include "atmel-isc.h"
247 +
248 +#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264
249 +#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464
250 +
251 +#define ISC_SAMA7G5_PIPELINE \
252 + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
253 + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
254 +
255 +/* This is a list of the formats that the ISC can *output* */
256 +static const struct isc_format sama7g5_controller_formats[] = {
257 + {
258 + .fourcc = V4L2_PIX_FMT_ARGB444,
259 + },
260 + {
261 + .fourcc = V4L2_PIX_FMT_ARGB555,
262 + },
263 + {
264 + .fourcc = V4L2_PIX_FMT_RGB565,
265 + },
266 + {
267 + .fourcc = V4L2_PIX_FMT_ABGR32,
268 + },
269 + {
270 + .fourcc = V4L2_PIX_FMT_XBGR32,
271 + },
272 + {
273 + .fourcc = V4L2_PIX_FMT_YUV420,
274 + },
275 + {
276 + .fourcc = V4L2_PIX_FMT_UYVY,
277 + },
278 + {
279 + .fourcc = V4L2_PIX_FMT_VYUY,
280 + },
281 + {
282 + .fourcc = V4L2_PIX_FMT_YUYV,
283 + },
284 + {
285 + .fourcc = V4L2_PIX_FMT_YUV422P,
286 + },
287 + {
288 + .fourcc = V4L2_PIX_FMT_GREY,
289 + },
290 + {
291 + .fourcc = V4L2_PIX_FMT_Y10,
292 + },
293 + {
294 + .fourcc = V4L2_PIX_FMT_Y16,
295 + },
296 +};
297 +
298 +/* This is a list of formats that the ISC can receive as *input* */
299 +static struct isc_format sama7g5_formats_list[] = {
300 + {
301 + .fourcc = V4L2_PIX_FMT_SBGGR8,
302 + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
303 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
304 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
305 + },
306 + {
307 + .fourcc = V4L2_PIX_FMT_SGBRG8,
308 + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
309 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
310 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
311 + },
312 + {
313 + .fourcc = V4L2_PIX_FMT_SGRBG8,
314 + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
315 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
316 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
317 + },
318 + {
319 + .fourcc = V4L2_PIX_FMT_SRGGB8,
320 + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
321 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
322 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
323 + },
324 + {
325 + .fourcc = V4L2_PIX_FMT_SBGGR10,
326 + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
327 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
328 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
329 + },
330 + {
331 + .fourcc = V4L2_PIX_FMT_SGBRG10,
332 + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
333 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
334 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
335 + },
336 + {
337 + .fourcc = V4L2_PIX_FMT_SGRBG10,
338 + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
339 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
340 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
341 + },
342 + {
343 + .fourcc = V4L2_PIX_FMT_SRGGB10,
344 + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
345 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
346 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
347 + },
348 + {
349 + .fourcc = V4L2_PIX_FMT_SBGGR12,
350 + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
351 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
352 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
353 + },
354 + {
355 + .fourcc = V4L2_PIX_FMT_SGBRG12,
356 + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
357 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
358 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
359 + },
360 + {
361 + .fourcc = V4L2_PIX_FMT_SGRBG12,
362 + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
363 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
364 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
365 + },
366 + {
367 + .fourcc = V4L2_PIX_FMT_SRGGB12,
368 + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
369 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
370 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
371 + },
372 + {
373 + .fourcc = V4L2_PIX_FMT_GREY,
374 + .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
375 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
376 + },
377 + {
378 + .fourcc = V4L2_PIX_FMT_YUYV,
379 + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
380 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
381 + },
382 + {
383 + .fourcc = V4L2_PIX_FMT_UYVY,
384 + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
385 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
386 + },
387 + {
388 + .fourcc = V4L2_PIX_FMT_RGB565,
389 + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
390 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
391 + },
392 + {
393 + .fourcc = V4L2_PIX_FMT_Y10,
394 + .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
395 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
396 + },
397 +
398 +};
399 +
400 +static void isc_sama7g5_config_csc(struct isc_device *isc)
401 +{
402 + struct regmap *regmap = isc->regmap;
403 +
404 + /* Convert RGB to YUV */
405 + regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
406 + 0x42 | (0x81 << 16));
407 + regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
408 + 0x19 | (0x10 << 16));
409 + regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
410 + 0xFDA | (0xFB6 << 16));
411 + regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
412 + 0x70 | (0x80 << 16));
413 + regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
414 + 0x70 | (0xFA2 << 16));
415 + regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
416 + 0xFEE | (0x80 << 16));
417 +}
418 +
419 +static void isc_sama7g5_config_cbc(struct isc_device *isc)
420 +{
421 + struct regmap *regmap = isc->regmap;
422 +
423 + /* Configure what is set via v4l2 ctrls */
424 + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness);
425 + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast);
426 + /* Configure Hue and Saturation as neutral midpoint */
427 + regmap_write(regmap, ISC_CBCHS_HUE, 0);
428 + regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4));
429 +}
430 +
431 +static void isc_sama7g5_config_cc(struct isc_device *isc)
432 +{
433 + struct regmap *regmap = isc->regmap;
434 +
435 + /* Configure each register at the neutral fixed point 1.0 or 0.0 */
436 + regmap_write(regmap, ISC_CC_RR_RG, (1 << 8));
437 + regmap_write(regmap, ISC_CC_RB_OR, 0);
438 + regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);
439 + regmap_write(regmap, ISC_CC_GB_OG, 0);
440 + regmap_write(regmap, ISC_CC_BR_BG, 0);
441 + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
442 +}
443 +
444 +static void isc_sama7g5_config_ctrls(struct isc_device *isc,
445 + const struct v4l2_ctrl_ops *ops)
446 +{
447 + struct isc_ctrls *ctrls = &isc->ctrls;
448 + struct v4l2_ctrl_handler *hdl = &ctrls->handler;
449 +
450 + ctrls->contrast = 16;
451 +
452 + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16);
453 +}
454 +
455 +static void isc_sama7g5_config_dpc(struct isc_device *isc)
456 +{
457 + u32 bay_cfg = isc->config.sd_format->cfa_baycfg;
458 + struct regmap *regmap = isc->regmap;
459 +
460 + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK,
461 + (64 << ISC_DPC_CFG_BLOFF_SHIFT));
462 + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK,
463 + (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT));
464 +}
465 +
466 +static void isc_sama7g5_config_gam(struct isc_device *isc)
467 +{
468 + struct regmap *regmap = isc->regmap;
469 +
470 + regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART,
471 + ISC_GAM_CTRL_BIPART);
472 +}
473 +
474 +static void isc_sama7g5_config_rlp(struct isc_device *isc)
475 +{
476 + struct regmap *regmap = isc->regmap;
477 + u32 rlp_mode = isc->config.rlp_cfg_mode;
478 +
479 + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
480 + ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH |
481 + ISC_RLP_CFG_YMODE_MASK, rlp_mode);
482 +}
483 +
484 +static void isc_sama7g5_adapt_pipeline(struct isc_device *isc)
485 +{
486 + isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE;
487 +}
488 +
489 +/* Gamma table with gamma 1/2.2 */
490 +static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = {
491 + /* index 0 --> gamma bipartite */
492 + {
493 + 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180,
494 + 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100,
495 + 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0,
496 + 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0,
497 + 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080,
498 + 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a,
499 + 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030,
500 + 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026,
501 + 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020,
502 + 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c,
503 + 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a },
504 +};
505 +
506 +static int xisc_parse_dt(struct device *dev, struct isc_device *isc)
507 +{
508 + struct device_node *np = dev->of_node;
509 + struct device_node *epn = NULL;
510 + struct isc_subdev_entity *subdev_entity;
511 + unsigned int flags;
512 + int ret;
513 + bool mipi_mode;
514 +
515 + INIT_LIST_HEAD(&isc->subdev_entities);
516 +
517 + mipi_mode = of_property_read_bool(np, "microchip,mipi-mode");
518 +
519 + while (1) {
520 + struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 };
521 +
522 + epn = of_graph_get_next_endpoint(np, epn);
523 + if (!epn)
524 + return 0;
525 +
526 + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn),
527 + &v4l2_epn);
528 + if (ret) {
529 + ret = -EINVAL;
530 + dev_err(dev, "Could not parse the endpoint\n");
531 + break;
532 + }
533 +
534 + subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity),
535 + GFP_KERNEL);
536 + if (!subdev_entity) {
537 + ret = -ENOMEM;
538 + break;
539 + }
540 + subdev_entity->epn = epn;
541 +
542 + flags = v4l2_epn.bus.parallel.flags;
543 +
544 + if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
545 + subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW;
546 +
547 + if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
548 + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW;
549 +
550 + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
551 + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;
552 +
553 + if (v4l2_epn.bus_type == V4L2_MBUS_BT656)
554 + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |
555 + ISC_PFE_CFG0_CCIR656;
556 +
557 + if (mipi_mode)
558 + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI;
559 +
560 + list_add_tail(&subdev_entity->list, &isc->subdev_entities);
561 + }
562 + of_node_put(epn);
563 +
564 + return ret;
565 +}
566 +
567 +static int microchip_xisc_probe(struct platform_device *pdev)
568 +{
569 + struct device *dev = &pdev->dev;
570 + struct isc_device *isc;
571 + struct resource *res;
572 + void __iomem *io_base;
573 + struct isc_subdev_entity *subdev_entity;
574 + int irq;
575 + int ret;
576 + u32 ver;
577 +
578 + isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
579 + if (!isc)
580 + return -ENOMEM;
581 +
582 + platform_set_drvdata(pdev, isc);
583 + isc->dev = dev;
584 +
585 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 + io_base = devm_ioremap_resource(dev, res);
587 + if (IS_ERR(io_base))
588 + return PTR_ERR(io_base);
589 +
590 + isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);
591 + if (IS_ERR(isc->regmap)) {
592 + ret = PTR_ERR(isc->regmap);
593 + dev_err(dev, "failed to init register map: %d\n", ret);
594 + return ret;
595 + }
596 +
597 + irq = platform_get_irq(pdev, 0);
598 + if (irq < 0)
599 + return irq;
600 +
601 + ret = devm_request_irq(dev, irq, isc_interrupt, 0,
602 + "microchip-sama7g5-xisc", isc);
603 + if (ret < 0) {
604 + dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
605 + irq, ret);
606 + return ret;
607 + }
608 +
609 + isc->gamma_table = isc_sama7g5_gamma_table;
610 + isc->gamma_max = 0;
611 +
612 + isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH;
613 + isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT;
614 +
615 + isc->config_dpc = isc_sama7g5_config_dpc;
616 + isc->config_csc = isc_sama7g5_config_csc;
617 + isc->config_cbc = isc_sama7g5_config_cbc;
618 + isc->config_cc = isc_sama7g5_config_cc;
619 + isc->config_gam = isc_sama7g5_config_gam;
620 + isc->config_rlp = isc_sama7g5_config_rlp;
621 + isc->config_ctrls = isc_sama7g5_config_ctrls;
622 +
623 + isc->adapt_pipeline = isc_sama7g5_adapt_pipeline;
624 +
625 + isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET;
626 + isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET;
627 + isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET;
628 + isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET;
629 + isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET;
630 + isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET;
631 + isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET;
632 + isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET;
633 + isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET;
634 +
635 + isc->controller_formats = sama7g5_controller_formats;
636 + isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats);
637 + isc->formats_list = sama7g5_formats_list;
638 + isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list);
639 +
640 + /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */
641 + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32;
642 +
643 + ret = isc_pipeline_init(isc);
644 + if (ret)
645 + return ret;
646 +
647 + isc->hclock = devm_clk_get(dev, "hclock");
648 + if (IS_ERR(isc->hclock)) {
649 + ret = PTR_ERR(isc->hclock);
650 + dev_err(dev, "failed to get hclock: %d\n", ret);
651 + return ret;
652 + }
653 +
654 + ret = clk_prepare_enable(isc->hclock);
655 + if (ret) {
656 + dev_err(dev, "failed to enable hclock: %d\n", ret);
657 + return ret;
658 + }
659 +
660 + ret = isc_clk_init(isc);
661 + if (ret) {
662 + dev_err(dev, "failed to init isc clock: %d\n", ret);
663 + goto unprepare_hclk;
664 + }
665 +
666 + isc->ispck = isc->isc_clks[ISC_ISPCK].clk;
667 +
668 + ret = clk_prepare_enable(isc->ispck);
669 + if (ret) {
670 + dev_err(dev, "failed to enable ispck: %d\n", ret);
671 + goto unprepare_hclk;
672 + }
673 +
674 + /* ispck should be greater or equal to hclock */
675 + ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock));
676 + if (ret) {
677 + dev_err(dev, "failed to set ispck rate: %d\n", ret);
678 + goto unprepare_clk;
679 + }
680 +
681 + ret = v4l2_device_register(dev, &isc->v4l2_dev);
682 + if (ret) {
683 + dev_err(dev, "unable to register v4l2 device.\n");
684 + goto unprepare_clk;
685 + }
686 +
687 + ret = xisc_parse_dt(dev, isc);
688 + if (ret) {
689 + dev_err(dev, "fail to parse device tree\n");
690 + goto unregister_v4l2_device;
691 + }
692 +
693 + if (list_empty(&isc->subdev_entities)) {
694 + dev_err(dev, "no subdev found\n");
695 + ret = -ENODEV;
696 + goto unregister_v4l2_device;
697 + }
698 +
699 + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
700 + struct v4l2_async_subdev *asd;
701 +
702 + v4l2_async_notifier_init(&subdev_entity->notifier);
703 +
704 + asd = v4l2_async_notifier_add_fwnode_remote_subdev(
705 + &subdev_entity->notifier,
706 + of_fwnode_handle(subdev_entity->epn),
707 + struct v4l2_async_subdev);
708 +
709 + of_node_put(subdev_entity->epn);
710 + subdev_entity->epn = NULL;
711 +
712 + if (IS_ERR(asd)) {
713 + ret = PTR_ERR(asd);
714 + goto cleanup_subdev;
715 + }
716 +
717 + subdev_entity->notifier.ops = &isc_async_ops;
718 +
719 + ret = v4l2_async_notifier_register(&isc->v4l2_dev,
720 + &subdev_entity->notifier);
721 + if (ret) {
722 + dev_err(dev, "fail to register async notifier\n");
723 + goto cleanup_subdev;
724 + }
725 +
726 + if (video_is_registered(&isc->video_dev))
727 + break;
728 + }
729 +
730 + pm_runtime_set_active(dev);
731 + pm_runtime_enable(dev);
732 + pm_request_idle(dev);
733 +
734 + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
735 + dev_info(dev, "Microchip XISC version %x\n", ver);
736 +
737 + return 0;
738 +
739 +cleanup_subdev:
740 + isc_subdev_cleanup(isc);
741 +
742 +unregister_v4l2_device:
743 + v4l2_device_unregister(&isc->v4l2_dev);
744 +
745 +unprepare_clk:
746 + clk_disable_unprepare(isc->ispck);
747 +unprepare_hclk:
748 + clk_disable_unprepare(isc->hclock);
749 +
750 + isc_clk_cleanup(isc);
751 +
752 + return ret;
753 +}
754 +
755 +static int microchip_xisc_remove(struct platform_device *pdev)
756 +{
757 + struct isc_device *isc = platform_get_drvdata(pdev);
758 +
759 + pm_runtime_disable(&pdev->dev);
760 +
761 + isc_subdev_cleanup(isc);
762 +
763 + v4l2_device_unregister(&isc->v4l2_dev);
764 +
765 + clk_disable_unprepare(isc->ispck);
766 + clk_disable_unprepare(isc->hclock);
767 +
768 + isc_clk_cleanup(isc);
769 +
770 + return 0;
771 +}
772 +
773 +static int __maybe_unused xisc_runtime_suspend(struct device *dev)
774 +{
775 + struct isc_device *isc = dev_get_drvdata(dev);
776 +
777 + clk_disable_unprepare(isc->ispck);
778 + clk_disable_unprepare(isc->hclock);
779 +
780 + return 0;
781 +}
782 +
783 +static int __maybe_unused xisc_runtime_resume(struct device *dev)
784 +{
785 + struct isc_device *isc = dev_get_drvdata(dev);
786 + int ret;
787 +
788 + ret = clk_prepare_enable(isc->hclock);
789 + if (ret)
790 + return ret;
791 +
792 + ret = clk_prepare_enable(isc->ispck);
793 + if (ret)
794 + clk_disable_unprepare(isc->hclock);
795 +
796 + return ret;
797 +}
798 +
799 +static const struct dev_pm_ops microchip_xisc_dev_pm_ops = {
800 + SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL)
801 +};
802 +
803 +static const struct of_device_id microchip_xisc_of_match[] = {
804 + { .compatible = "microchip,sama7g5-isc" },
805 + { }
806 +};
807 +MODULE_DEVICE_TABLE(of, microchip_xisc_of_match);
808 +
809 +static struct platform_driver microchip_xisc_driver = {
810 + .probe = microchip_xisc_probe,
811 + .remove = microchip_xisc_remove,
812 + .driver = {
813 + .name = "microchip-sama7g5-xisc",
814 + .pm = &microchip_xisc_dev_pm_ops,
815 + .of_match_table = of_match_ptr(microchip_xisc_of_match),
816 + },
817 +};
818 +
819 +module_platform_driver(microchip_xisc_driver);
820 +
821 +MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com>");
822 +MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC");
823 +MODULE_LICENSE("GPL v2");
824 --
825 2.32.0
826
Staging tree of Jo-Philipp Wich