target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch

   1 From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 19 Jul 2021 11:03:17 +0300
   4 Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's
   5  master clock
   6
   7 Add register definitions for SAMA7G5's master clock. These would be
   8 also used by architecture specific power saving code.
   9
  10 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  11 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  12 Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com
  13 ---
  14  include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++
  15  1 file changed, 26 insertions(+)
  16
  17 diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
  18 index a4f82e836a7c..ccb3f034bfa9 100644
  19 --- a/include/linux/clk/at91_pmc.h
  20 +++ b/include/linux/clk/at91_pmc.h
  21 @@ -137,6 +137,32 @@
  22  #define                        AT91_PMC_PLLADIV2_ON            (1 << 12)
  23  #define                AT91_PMC_H32MXDIV       BIT(24)
  24
  25 +#define        AT91_PMC_MCR_V2         0x30                            /* Master Clock Register [SAMA7G5 only] */
  26 +#define                AT91_PMC_MCR_V2_ID_MSK  (0xF)
  27 +#define                        AT91_PMC_MCR_V2_ID(_id)         ((_id) & AT91_PMC_MCR_V2_ID_MSK)
  28 +#define                AT91_PMC_MCR_V2_CMD     (1 << 7)
  29 +#define                AT91_PMC_MCR_V2_DIV     (7 << 8)
  30 +#define                        AT91_PMC_MCR_V2_DIV1            (0 << 8)
  31 +#define                        AT91_PMC_MCR_V2_DIV2            (1 << 8)
  32 +#define                        AT91_PMC_MCR_V2_DIV4            (2 << 8)
  33 +#define                        AT91_PMC_MCR_V2_DIV8            (3 << 8)
  34 +#define                        AT91_PMC_MCR_V2_DIV16           (4 << 8)
  35 +#define                        AT91_PMC_MCR_V2_DIV32           (5 << 8)
  36 +#define                        AT91_PMC_MCR_V2_DIV64           (6 << 8)
  37 +#define                        AT91_PMC_MCR_V2_DIV3            (7 << 8)
  38 +#define                AT91_PMC_MCR_V2_CSS     (0x1F << 16)
  39 +#define                        AT91_PMC_MCR_V2_CSS_MD_SLCK     (0 << 16)
  40 +#define                        AT91_PMC_MCR_V2_CSS_TD_SLCK     (1 << 16)
  41 +#define                        AT91_PMC_MCR_V2_CSS_MAINCK      (2 << 16)
  42 +#define                        AT91_PMC_MCR_V2_CSS_MCK0        (3 << 16)
  43 +#define                        AT91_PMC_MCR_V2_CSS_SYSPLL      (5 << 16)
  44 +#define                        AT91_PMC_MCR_V2_CSS_DDRPLL      (6 << 16)
  45 +#define                        AT91_PMC_MCR_V2_CSS_IMGPLL      (7 << 16)
  46 +#define                        AT91_PMC_MCR_V2_CSS_BAUDPLL     (8 << 16)
  47 +#define                        AT91_PMC_MCR_V2_CSS_AUDIOPLL    (9 << 16)
  48 +#define                        AT91_PMC_MCR_V2_CSS_ETHPLL      (10 << 16)
  49 +#define                AT91_PMC_MCR_V2_EN      (1 << 28)
  50 +
  51  #define AT91_PMC_XTALF         0x34                    /* Main XTAL Frequency Register [SAMA7G5 only] */
  52
  53  #define        AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
  54 --
  55 2.32.0
  56